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Hello,
In wlan_mac_pkt_buf_util.h, TX packet buffer assignments are defined (pasted for reference at the bottom).
Here, 3 packet buffers are assigned for CPU_HIGH. I know that the function wlan_mac_high_get_empty_tx_packet_buffer() returns one of these 3 buffers.
My question is, is it ok to change the number of buffers, for example to 1 or 2?
I'd like to use other buffers for transmitting other special type of packets. What would be the impact of reducing the packet buffers assigned to CPU_HIGH? If I need more packet buffers, would it be better to increase the bram size than reduce the number of packet buffers?
Thanks a lot for help.
// Tx packet buffer assignments // The definitions for the MPDU packet buffers are not directly // used. Instead, the actual packet buffer values are used to // make iteration easier. // // Packet Buffers owned by CPU_HIGH at boot #define TX_PKT_BUF_MPDU_1 0 #define TX_PKT_BUF_MPDU_2 1 #define TX_PKT_BUF_MPDU_3 2 // #define TX_PKT_BUF_ 3 // #define TX_PKT_BUF_ 4 #define TX_PKT_BUF_BEACON 5 // Packet Buffers owned by CPU_LOW at boot #define TX_PKT_BUF_RTS 6 #define TX_PKT_BUF_ACK_CTS 7
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The 3-buffer ping/pong flow for Tx packet buffers is new in v1.5 (recently documented in the user guide). We use 3 buffers to minimize the duration where CPU Low might be waiting for a new Tx packet from CPU High. Reducing this to 2 or 1 Tx buffer would increase the chance of "starving" CPU Low of new Tx packets, directly affecting throughput.
In the v1.5 code Tx buffers 3 and 4 are unused, and buffer 6 is only used for RTS. Can your custom scheme work with just these 2 or 3 buffers? We'd be happy to assist with ideas for implementing your scheme if you're able to share more details.
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Also keep in mind that the top-level application (AP, STA, or IBSS) can set up a dedicated Tx queue for certain type of packets. For example, the AP has dedicated queues for multicast data frames and for management frames in addition to the normal per-user data queues. The round-robin poll_tx_queues() implementation gives priority to management queue by ensuring that a dequeue from it is attempted in between every dequeue of other data frames.
It depends on what your application is, but you might not need a dedicated packet buffer. You can can still give different custom packets their own effective priority level by choosing how they are enqueued and dequeued.
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Thanks a lot for the replies.
I get the reason for using the 3-buffer structure... I should keep it that way.
I was trying to see if I could use RF-A and RF-B as two separate physical interfaces tuned to different channels (sort of like dual-band routers). If possible, my goal is to use different MAC for each interface. (e.g. one interfaces uses DCF while the other uses a non-standard MAC).
Just to start something, I was trying to let mb_high select different tx packet buffer index based on some scheduling criteria. Depending on the buffer, the packet is to be sent to RFA or RFB.
I'm still in the initial stage of trying out something so it is very unclear to me even, but to make two interfaces running two different MACs tied to one RF each, I think I should use two sets of MAC and PHY. (mac_hw, phy_tx, phy_rx, etc.)
I am also thinking of using two mb_lows, but that makes things complicated because as described in the packet flow user guide, the peripheral cores are only accessible by one CPU (thus cannot be connected to both mb_lows.). I'm not sure how I should connect the second mac low to hardware support cores like radio_controller, etc.
Do you think what I am intending to do is feasible? If so, what would be a good design strategy of doing this, especially the feasibility of using two mb_low modules and interconnecting peripheral cores (packet buffer, inter-process communication, radio controller, ad controller, etc)?
Any opinion would be very helpful.
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Extending the 802.11 Reference Design to implement 2 independent MAC/PHY is a big undertaking. I'm not entirely sure it would even fit in the V6LX240 device. A few ideas:
-You're right that duplicating CPU Low is probably not a good approach. CPU Low is responsible for more than just the lower MAC; it is also responsible for managing hardware resources with cores (w3_clock_controller_axi, w3_ad_controller_axi, w3_radio_controller, etc) that assume they aren't competing for access to hardware.
-It is conceivable that a single CPU Low core could implement two MAC instances. This would require redesigning the lower MAC to handle two MAC contexts, probably requiring interrupts for interleaved indications from dual wlan_mac_hw cores. But even this approach would require duplicating the (large) Tx/Rx PHY cores and packet buffers.
Does your application actually require simultaneous PHY operation on the two bands? If not, a much more feasible approach would be to:
-Tune RF A and B to different frequencies (the radio_controller_setCenterFrequency() can operate on single interfaces)
-Configure the Rx PHY to detect packets on either interface ("switching diversity" mode in the code)
-Select the desired Tx interface per packet (already supported in the reference code)
-Modify the MAC behaviors in CPU Low depending on the current packet's Tx/Rx interface.
This approach would not achieve a true dual-interface design but would allow implementation of different MAC behaviors for Tx/Rx events on different bands.
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I think I could try to implement two different MACs with a single PHY TX/RX like you suggested.
But before going that way, I was curious to see what happens if I add one more set of PHY TX/RX (and also MAC_HW).
Result is I get the timing problem, similar to another post.
https://warpproject.org/forums/viewtopic.php?id=3058
From the other post I realize that 1ns failure is big. I tried changing the -t parameter in fast_runtime.opt but the result is almost the same.
I want to get your opinion on whether this timing error is hard to overcome (which means having two PHYs is not a feasible approach), or if there are ways to get around this (without substantially re-designing the cores).
Here is the result from the timing analysis. wlan_phy_rx_2 is the second PHY RX I added. I removed the chipscope icon from the design, and that is the only thing changed inside the core.
I am not familiar with this, but the source and destination is both in PHY RX core, so I am curious why adding one more core generates this timing error.
I would appreciate any comments/opinions.
Thanks a lot.
Timing constraint: TS_clk_gen_proc_bus_clks_clk_gen_proc_bus_clks_SIG_MMCM0_CLKOUT1 = PERIOD TIMEGRP "clk_gen_proc_bus_clks_clk_gen_proc_bus_clks_SIG_MMCM0_CLKOUT1" TS_samp_clk * 2 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
15535742 paths analyzed, 546031 endpoints analyzed, 189 failing endpoints
189 timing errors detected. (189 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 7.295ns.
--------------------------------------------------------------------------------
Slack (setup path): -1.045ns (requirement - (data path - clock path skew + uncertainty))
Source: wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register5/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp (FF)
Destination: wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[7].fde_used.u2 (FF)
Requirement: 6.250ns
Data Path Delay: 7.190ns (Levels of Logic = 6)
Clock Path Skew: -0.047ns (0.906 - 0.953)
Source Clock: INIT_BRAM_CTRL_PORT_A_BRAM_Clk rising at 0.000ns
Destination Clock: INIT_BRAM_CTRL_PORT_A_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register5/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp to wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[7].fde_used.u2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X17Y54.DMUX Tshcko 0.357 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/register5_q_net_x1<10>
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register5/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp
SLICE_X18Y55.A1 net (fanout=1) 0.649 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register5_q_net_x0<1>
SLICE_X18Y55.A Tilo 0.061 mb_shared_axi_periph/mb_shared_axi_periph/mi_register_slice_bank/gen_reg_slot[1].register_slice_inst/r_pipe/storage_data1<6>
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mux/Mmux_unregy_join_6_121
DSP48_X0Y23.A1 net (fanout=2) 0.442 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mux_y_net<1>
DSP48_X0Y23.P12 Tdspdo_A_P_MULT 3.236 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/comp4.core_instance4/blk00000001/blk00000004
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/comp4.core_instance4/blk00000001/blk00000004
SLICE_X13Y68.A1 net (fanout=2) 0.982 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/tmp_p<12>
SLICE_X13Y68.A Tilo 0.061 w3_iic_eeprom_onBoard/N168
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o13
SLICE_X13Y68.B3 net (fanout=1) 0.308 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o12
SLICE_X13Y68.B Tilo 0.061 w3_iic_eeprom_onBoard/N168
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o14
SLICE_X11Y61.B6 net (fanout=1) 0.531 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o13
SLICE_X11Y61.B Tilo 0.061 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4_p_net_x0<10>
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o15
SLICE_X9Y61.A5 net (fanout=4) 0.381 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/tmp_p[13]_GND_2879_o_MUX_1955_o
SLICE_X9Y61.CLK Tas 0.060 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4_p_net_x0<7>
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_conv_p111
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[7].fde_used.u2
------------------------------------------------- ---------------------------
Total 7.190ns (3.897ns logic, 3.293ns route)
(54.2% logic, 45.8% route)Last edited by Kevin20 (2016-Apr-27 19:41:37)
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The failure listed above is in a recently modified Rx PHY subsystem. I'll take a deeper look tomorrow to see if there are any obvious optimizations there.
Were all 189 failures in the same Rx PHY subsystem?
I'm actually a bit surprised the timing was that close for a dual-PHY design. What was the total resource usage for your modified design? The easiest place to find this is the system.mrp report (example in the user guide).
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I see.. the design summary of the dual-phy design is attached below.
About the timing errors, all 189 errors were for the same timing constraint.. but I'm not sure all 189 were for phy rx.
The result shows the first 3 results, and at least they are all PHY RX errors (all soft demod/scale and quantize).
Is there a file where I can see the details of all 189 errors?
Update: I found out how to print all errors, and all errors are in PHY RX. All in scale & quantize subsystem, all from registerX to multY.
I don't know anything here, but your note iin Soft Demod/Scale & Quantize, "Explicit fanout for better timing closure. Mux-to-mults was critical path when one 4:1 mux drove all 6 multipliers" seems to be related..
Design Information
------------------
Command Line : map -mt 4 -o system_map.ncd -w -pr b -ol high -t 13 -register_duplication on -timing -detail system.ngd
system.pcf
Target Device : xc6vlx240t
Target Package : ff1156
Target Speed : -2
Mapper Version : virtex6 -- $Revision: 1.55 $
Mapped Date : Wed Apr 27 18:16:50 2016
Design Summary
--------------
Number of errors: 0
Number of warnings: 399
Slice Logic Utilization:
Number of Slice Registers: 112,379 out of 301,440 37%
Number used as Flip Flops: 112,050
Number used as Latches: 3
Number used as Latch-thrus: 0
Number used as AND/OR logics: 326
Number of Slice LUTs: 103,432 out of 150,720 68%
Number used as logic: 84,478 out of 150,720 56%
Number using O6 output only: 65,190
Number using O5 output only: 2,120
Number using O5 and O6: 17,168
Number used as ROM: 0
Number used as Memory: 10,619 out of 58,400 18%
Number used as Dual Port RAM: 3,186
Number using O6 output only: 2,066
Number using O5 output only: 27
Number using O5 and O6: 1,093
Number used as Single Port RAM: 38
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 16
Number used as Shift Register: 7,395
Number using O6 output only: 6,534
Number using O5 output only: 27
Number using O5 and O6: 834
Number used exclusively as route-thrus: 8,335
Number with same-slice register load: 7,507
Number with same-slice carry load: 816
Number with other load: 12
Slice Logic Distribution:
Number of occupied Slices: 35,783 out of 37,680 94%
Number of LUT Flip Flop pairs used: 123,021
Number with an unused Flip Flop: 27,350 out of 123,021 22%
Number with an unused LUT: 19,589 out of 123,021 15%
Number of fully used LUT-FF pairs: 76,082 out of 123,021 61%
Number of unique control sets: 3,674
Number of slice register sites lost
to control set restrictions: 13,561 out of 301,440 4%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 354 out of 600 59%
Number of LOCed IOBs: 354 out of 354 100%
IOB Flip Flops: 116
IOB Master Pads: 10
IOB Slave Pads: 10
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 231 out of 416 55%
Number using RAMB36E1 only: 231
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 65 out of 832 7%
Number using RAMB18E1 only: 65
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 8 out of 32 25%
Number used as BUFGs: 8
Number used as BUFGCTRLs: 0
Number of ILOGICE1/ISERDESE1s: 108 out of 720 15%
Number used as ILOGICE1s: 43
Number used as ISERDESE1s: 65
Number of OLOGICE1/OSERDESE1s: 200 out of 720 27%
Number used as OLOGICE1s: 75
Number used as OSERDESE1s: 125
Number of BSCANs: 1 out of 4 25%
Number of BUFHCEs: 0 out of 144 0%
Number of BUFIODQSs: 10 out of 72 13%
Number of BUFRs: 5 out of 36 13%
Number of LOCed BUFRs: 2 out of 5 40%
Number of CAPTUREs: 0 out of 1 0%
Number of DSP48E1s: 343 out of 768 44%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of GTXE1s: 0 out of 20 0%
Number of IBUFDS_GTXE1s: 0 out of 12 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 5 out of 18 27%
Number of IODELAYE1s: 112 out of 720 15%
Number of LOCed IODELAYE1s: 10 out of 112 8%
Number of MMCM_ADVs: 3 out of 12 25%
Number of PCIE_2_0s: 0 out of 2 0%
Number of STARTUPs: 1 out of 1 100%
Number of SYSMONs: 1 out of 1 100%
Number of TEMAC_SINGLEs: 2 out of 4 50%
Number of RPM macros: 5
Average Fanout of Non-Clock Nets: 3.42Last edited by Kevin20 (2016-Apr-28 02:35:53)
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Just for information, here is the timing analysis for the single-PHY (original reference design) and dual-PHY design for the same
source and destination. Source: register3, Destination: mult4 all in soft_demod/scale_quantize.
Logic delay is increased, but route delay is more significantly increased.
Level of logic increased from 3 to 6.
---------------
SINGLE-PHY
---------------
--------------------------------------------------------------------------------
Slack (setup path): 0.675ns (requirement - (data path - clock path skew + uncertainty))
Source: wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp (FF)
Destination: wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[11].fde_used.u2 (FF)
Requirement: 6.250ns
Data Path Delay: 5.540ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: INIT_BRAM_CTRL_PORT_A_BRAM_Clk rising at 0.000ns
Destination Clock: INIT_BRAM_CTRL_PORT_A_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp to wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[11].fde_used.u2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X134Y226.DQ Tcko 0.322 wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3_q_net_x0<3>
wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp
SLICE_X139Y229.D4 net (fanout=1) 0.499 wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3_q_net_x0<3>
SLICE_X139Y229.D Tilo 0.061 wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register2_q_net_x0<0>
wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mux/Mmux_unregy_join_6_141
DSP48_X6Y89.A3 net (fanout=2) 0.663 wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mux_y_net<3>
DSP48_X6Y89.P13 Tdspdo_A_P_MULT 3.236 wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/comp4.core_instance4/blk00000001/blk00000004
wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/comp4.core_instance4/blk00000001/blk00000004
SLICE_X133Y224.C3 net (fanout=4) 0.699 wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/conv_p<12>
SLICE_X133Y224.CLK Tas 0.060 wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4_p_net_x0<11>
wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_conv_p31
wlan_phy_rx/wlan_phy_rx/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[11].fde_used.u2
------------------------------------------------- ---------------------------
Total 5.540ns (3.679ns logic, 1.861ns route)
(66.4% logic, 33.6% route)---------------
DUAL-PHY
---------------
--------------------------------------------------------------------------------
Slack (setup path): -0.942ns (requirement - (data path - clock path skew + uncertainty))
Source: wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp (FF)
Destination: wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[7].fde_used.u2 (FF)
Requirement: 6.250ns
Data Path Delay: 6.936ns (Levels of Logic = 6)
Clock Path Skew: -0.198ns (1.320 - 1.518)
Source Clock: INIT_BRAM_CTRL_PORT_A_BRAM_Clk rising at 0.000ns
Destination Clock: INIT_BRAM_CTRL_PORT_A_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp to wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[7].fde_used.u2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X18Y163.DMUX Tshcko 0.394 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/register1_q_net_x1<14>
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp
SLICE_X19Y163.D2 net (fanout=1) 0.730 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register3_q_net_x0<2>
SLICE_X19Y163.D Tilo 0.061 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/register6_q_net_x0<1>
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mux/Mmux_unregy_join_6_131
DSP48_X1Y62.A2 net (fanout=2) 0.569 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mux_y_net<2>
DSP48_X1Y62.P20 Tdspdo_A_P_MULT 3.236 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/comp4.core_instance4/blk00000001/blk00000004
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/comp4.core_instance4/blk00000001/blk00000004
SLICE_X18Y157.A2 net (fanout=2) 0.703 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/tmp_p<20>
SLICE_X18Y157.A Tilo 0.061 radio_controller/radio_controller/USER_LOGIC_I/RFB_RxEn_sw
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o13
SLICE_X18Y157.B3 net (fanout=1) 0.314 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o12
SLICE_X18Y157.B Tilo 0.061 radio_controller/radio_controller/USER_LOGIC_I/RFB_RxEn_sw
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o14
SLICE_X21Y157.B6 net (fanout=1) 0.398 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o13
SLICE_X21Y157.B Tilo 0.061 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4_p_net_x0<10>
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_tmp_p[13]_GND_2879_o_MUX_1955_o15
SLICE_X21Y157.A5 net (fanout=4) 0.288 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/tmp_p[13]_GND_2879_o_MUX_1955_o
SLICE_X21Y157.CLK Tas 0.060 wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4_p_net_x0<10>
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/Mmux_conv_p111
wlan_phy_rx_2/wlan_phy_rx_2/sysgen_dut/wlan_phy_rx_pmd_x0/detect_decode_370e444f33/soft_demod_00b0bec4e8/scale_quantize_f2b00e6f45/mult4/latency_gt_0.reg/partial_one.last_srl17e/reg_array[7].fde_used.u2
------------------------------------------------- ---------------------------
Total 6.936ns (3.934ns logic, 3.002ns route)
(56.7% logic, 43.3% route)Last edited by Kevin20 (2016-Apr-28 04:01:28)
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The timing errors above occur in the Rx PHY "Soft Demod" block. This block was redesigned for the v1.5 PHY. The updated design has a few pretty long combinational paths. That the timing report lists "Levels of Logic = 6" is a clear indication of this. I checked the timing report for the reference v1.5 hardware. These paths are indeed among the critical paths.
I just committed an updated Rx PHY model to svn (rev 5491) that has better pipelining through the Soft Demod logic. We will incorporate this updated design in the next release of the reference design (probably v1.6, planned for later this year). The rev 5491 model has no MAC interface or software changes, so you can safely use this model in your local copy of the v1.5 hardware project.
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Thanks. I've tried building the system with the new core.
Timing errors still exist, but it is reduced to less than 0.3ns.
Levels of logic became 3 too.
I am now trying with other "-t" parameters.
UPDATE:
I just realized that these errors are not from the previous paths. I get 31 timing errors and they are all coming from wlan_phy_tx/preamble_outputs/scaling subsystem. Timing errors from wlan_phy_rx are gone!
Maybe I can apply the same strategy here as what you did to wlan_phy_rx.
Thanks.
================================================================================
Timing constraint: TS_clk_gen_proc_bus_clks_clk_gen_proc_bus_clks_SIG_MMCM0_CLKOUT1 = PERIOD TIMEGRP "clk_gen_proc_bus_clks_clk_gen_proc_bus_clks_SIG_MMCM0_CLKOUT1" TS_samp_clk * 2 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
15073089 paths analyzed, 530913 endpoints analyzed, 31 failing endpoints
31 timing errors detected. (31 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 6.536ns.
--------------------------------------------------------------------------------
Slack (setup path): -0.286ns (requirement - (data path - clock path skew + uncertainty))
Source: wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/register5/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp (FF)
Destination: wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mult/latency_gt_0.reg/partial_one.last_srl17e/reg_array[6].fde_used.u2 (FF)
Requirement: 6.250ns
Data Path Delay: 6.371ns (Levels of Logic = 3)
Clock Path Skew: -0.107ns (1.363 - 1.470)
Source Clock: INIT_BRAM_CTRL_PORT_A_BRAM_Clk rising at 0.000ns
Destination Clock: INIT_BRAM_CTRL_PORT_A_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/register5/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp to wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mult/latency_gt_0.reg/partial_one.last_srl17e/reg_array[6].fde_used.u2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X81Y61.BQ Tcko 0.283 wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/register13_q_net_x2<11>
wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/register5/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp
SLICE_X81Y61.D1 net (fanout=8) 0.650 wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/register5_q_net
SLICE_X81Y61.DMUX Tilo 0.170 wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/register13_q_net_x2<11>
wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mux1/Mmux_unregy_join_6_131
DSP48_X4Y24.A11 net (fanout=2) 1.156 wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mux1_y_net<11>
DSP48_X4Y24.P27 Tdspdo_A_P_MULT 3.236 wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mult/comp0.core_instance0/blk00000001/blk00000004
wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mult/comp0.core_instance0/blk00000001/blk00000004
SLICE_X103Y63.C2 net (fanout=11) 0.816 wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mult/tmp_p<27>
SLICE_X103Y63.CLK Tas 0.060 wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/mult_p_net_x1<11>
wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mult/Mmux_conv_p91
wlan_phy_tx_2/wlan_phy_tx_2/sysgen_dut/wlan_phy_tx_pmd_x0/preamble_outputs_82fcc722dc/scaling_a269710a35/mult/latency_gt_0.reg/partial_one.last_srl17e/reg_array[6].fde_used.u2
------------------------------------------------- ---------------------------
Total 6.371ns (3.749ns logic, 2.622ns route)
(58.8% logic, 41.2% route)Last edited by Kevin20 (2016-Apr-29 19:01:25)
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