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SysGenExport: prng_useriosrc.mdl

File prng_useriosrc.mdl, 157.5 KB (added by chunter, 12 years ago)

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1	Model {
2	Name "prng_useriosrc"
3	Version 7.7
4	MdlSubVersion 0
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20	MinMaxOverflowLogging "UseLocalSettings"
21	MinMaxOverflowArchiveMode "Overwrite"
22	MaxMDLFileLineLength 120
23	Created "Mon Aug 06 09:50:40 2012"
24	Creator "chunter"
25	UpdateHistory "UpdateHistoryNever"
26	ModifiedByFormat "%<Auto>"
27	LastModifiedBy "chunter"
28	ModifiedDateFormat "%<Auto>"
29	LastModifiedDate "Wed Aug 22 11:24:41 2012"
30	RTWModifiedTimeStamp 267533865
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146	MinStep "auto"
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670	YMax "5"
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744	GeneratePreprocessorConditionals off
745	infoedit " System Generator"
746	xilinxfamily "virtex6"
747	part "xc6vlx240t"
748	speed "-2"
749	package "ff1156"
750	synthesis_tool "XST"
751	clock_wrapper "Clock Enables"
752	directory "./netlist"
753	proj_type "Project Navigator"
754	Synth_file "XST Defaults"
755	Impl_file "ISE Defaults"
756	testbench off
757	simulink_period "1"
758	sysclk_period "10"
759	dcm_input_clock_period "10"
760	incr_netlist off
761	trim_vbits "Everywhere in SubSystem"
762	dbl_ovrd "According to Block Masks"
763	core_generation "According to Block Masks"
764	run_coregen off
765	deprecated_control off
766	eval_field "0"
767	has_advanced_control "0"
768	sggui_pos "326,241,464,470"
769	block_type "sysgen"
770	sg_icon_stat "50,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]"
771	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]"
772	");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1"
773	"55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3"
774	"6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15"
775	"5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15"
776	"5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph"
777	"ics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');"
778	}
779	Block {
780	BlockType Reference
781	Name "Constant"
782	SID "29"
783	Ports [0, 1]
784	Position [780, 447, 835, 473]
785	LibraryVersion "1.2"
786	SourceBlock "xbsIndex_r4/Constant"
787	SourceType "Xilinx Constant Block Block"
788	const "1"
789	gui_display_data_type "Boolean"
790	arith_type "Boolean"
791	n_bits "16"
792	bin_pt "14"
793	preci_type "Single"
794	exp_width "8"
795	frac_width "24"
796	explicit_period off
797	period "1"
798	dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block."
799	equ "P=C"
800	opselect "C"
801	inp2 "PCIN>>17"
802	opr "+"
803	inp1 "P"
804	carry "CIN"
805	dbl_ovrd off
806	has_advanced_control "0"
807	sggui_pos "-1,-1,-1,-1"
808	block_type "constant"
809	sg_icon_stat "55,26,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]"
810	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0."
811	"82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],["
812	"16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 1"
813	"3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13"
814	".33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 "
815	"7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')"
816	";\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');"
817	}
818	Block {
819	BlockType Constant
820	Name "Constant1"
821	SID "37"
822	Position [80, 265, 110, 295]
823	Value "0"
824	}
825	Block {
826	BlockType Reference
827	Name "Counter"
828	SID "8"
829	Ports [1, 1]
830	Position [305, 415, 365, 475]
831	LibraryVersion "1.2"
832	SourceBlock "xbsIndex_r4/Counter"
833	SourceType "Xilinx Counter Block"
834	infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited cou"
835	"nter is implemented by combining a counter with a comparator."
836	cnt_type "Free Running"
837	cnt_to "Inf"
838	operation "Up"
839	start_count "0"
840	cnt_by_val "1"
841	arith_type "Unsigned"
842	n_bits "32"
843	bin_pt "0"
844	load_pin off
845	rst on
846	en off
847	explicit_period "on"
848	period "1"
849	dbl_ovrd off
850	use_behavioral_HDL off
851	implementation "Fabric"
852	xl_use_area off
853	xl_area "[0,0,0,0,0,0,0]"
854	has_advanced_control "0"
855	sggui_pos "135,567,348,661"
856	block_type "counter"
857	sg_icon_stat "60,60,1,1,white,blue,0,803eba70,right,,[ ],[ ]"
858	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0."
859	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 "
860	"38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 3"
861	"8.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1"
862	" ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 "
863	"0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po"
864	"rt_label('input',1,'rst');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT"
865	": end icon text');"
866	}
867	Block {
868	BlockType SubSystem
869	Name "EDK Processor"
870	SID "11"
871	Ports []
872	Position [89, 30, 151, 94]
873	CopyFcn "xlProcBlockCopyCallback(gcbh);xlBlockMoveCallback(gcbh);"
874	DeleteFcn "xlDestroyGui(gcbh);"
875	LoadFcn "xlBlockLoadCallback(gcbh);"
876	ModelCloseFcn "xlDestroyGui(gcbh);"
877	PreSaveFcn "xlBlockPreSaveCallback(gcbh);"
878	PostSaveFcn "xlBlockPostSaveCallback(gcbh);"
879	DestroyFcn "xlDestroyGui(gcbh);"
880	OpenFcn "bh=gcbh;xlProcBlockCallbacks('populatesharedmemorylistbox',bh);xlOpenGui(bh, 'edkprocessor_gui.x"
881	"ml', @xlProcBlockEnablement, @xlProcBlockAction);"
882	CloseFcn "xlDestroyGui(gcbh);"
883	MoveFcn "xlBlockMoveCallback(gcbh);"
884	MinAlgLoopOccurrences off
885	PropExecContextOutsideSubsystem off
886	RTWSystemCode "Auto"
887	FunctionWithSeparateData off
888	Opaque off
889	RequestExecContextInheritance off
890	MaskHideContents off
891	MaskType "Xilinx EDK Processor Block"
892	MaskDescription "Xilinx EDK Processor"
893	MaskHelp "eval('');xlDoc('-book','sysgen','-topic','EDK_Processor');"
894	MaskPromptString "Configure Processor for\|XPS Project\| \|Available Memories\| \| \|Bus Type\|Base Address\| \|Loc"
895	"k\| \|Dual Clocks\| \|Register Read-Back\|Constraint File\| \|Inherit Device Type\|Initial Program\| \|Enable Co-Debug wit"
896	"h Xilinx SDK (Beta)\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| "
897	MaskStyleString "popup(EDK pcore generation\|HDL netlisting),edit,edit,edit,edit,edit,popup(AXI\|PLB),edit,e"
898	"dit,checkbox,edit,checkbox,edit,checkbox,edit,edit,checkbox,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edi"
899	"t,edit,edit,edit,edit,edit,edit,edit,edit,edit"
900	MaskVariables "mode=&1;xmp=&2;MemVisToProc=&3;AvailableMemories=&4;portInterfaceTable=&5;bus_type_sgadvanc"
901	"ed=&6;bus_type=&7;baseaddr=&8;baseaddr_lock_sgadvanced=&9;baseaddr_lock=@10;dual_clock_sgadvanced=&11;dual_clock"
902	"=@12;reg_readback_sgadvanced=&13;reg_readback=@14;ucf_file=&15;inheritDeviceType_sgadvanced=&16;inheritDeviceTyp"
903	"e=@17;elf_file=&18;codebug_sgadvanced=&19;codebug=@20;clock_name=&21;internalPortList=&22;resetPolarity=&23;memx"
904	"table=&24;procinfo=&25;memmapdirty=&26;blockname=&27;xpsintstyle=&28;has_advanced_control=@29;sggui_pos=&30;bloc"
905	"k_type=&31;block_version=&32;sg_icon_stat=&33;sg_mask_display=&34;sg_list_contents=&35;sg_blockgui_xml=&36;"
906	MaskTunableValueString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,"
907	"on,on,on,on,on,on,on"
908	MaskCallbackString "\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|"
909	MaskEnableString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,o"
910	"n,on,on,on,on,on,on"
911	MaskVisibilityString "on,on,off,on,on,off,on,on,off,on,off,on,off,on,on,off,on,on,off,on,off,off,off,off,off,"
912	"off,off,off,off,off,off,off,off,off,off,off"
913	MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,"
914	"on,on,on,on,on,on,on"
915	MaskInitialization "try\n tmp_gcb = gcb;\n tmp_gcbh = gcbh;\n if (strcmp('SysGenIndex',get_param(bdroot("
916	"tmp_gcbh),'tag')) && ~isempty(regexp(bdroot(tmp_gcb), '^xbs', 'once')))\n return;\n end;\n xlMungeMaskParam"
917	"s;\n\n block_type='edkprocessor';\n\n serialized_declarations = '{''block_type''=>''String''}';\n xledkproces"
918	"sor_init();\n ptable_ = xlblockprep(get_param(tmp_gcb, 'MaskWSVariables'));\n try\n xlBlockMoveCallback(tmp"
919	"_gcbh);\n catch \n clear global xl_updateicon_recursion_guard;\n end;\ncatch\n global dbgsysgen;\n if(~i"
920	"sempty(dbgsysgen) && dbgsysgen)\n e = regexprep(lasterr, '\\n', '\\nError: ');\n disp(['Error: While runni"
921	"ng MaskInit code on block ' tmp_gcb ': ' e]);\n error(e);\n end\nend\n"
922	MaskSelfModifiable on
923	MaskDisplay "fprintf('','COMMENT: begin icon graphics');\npatch([0 62 62 0 0 ],[0 0 64 64 0 ],[0.77 0.82 0"
924	".91 ]);\nplot([0 62 62 0 0 ],[0 0 64 64 0 ]);\npatch([13.2 24.76 32.76 40.76 48.76 32.76 21.2 13.2 ],[40.88 40.8"
925	"8 48.88 40.88 48.88 48.88 48.88 40.88 ],[1 1 1 ]);\npatch([21.2 32.76 24.76 13.2 21.2 ],[32.88 32.88 40.88 40.88"
926	" 32.88 ],[0.931 0.946 0.973 ]);\npatch([13.2 24.76 32.76 21.2 13.2 ],[24.88 24.88 32.88 32.88 24.88 ],[1 1 1 ]);"
927	"\npatch([21.2 48.76 40.76 32.76 24.76 13.2 21.2 ],[16.88 16.88 24.88 16.88 24.88 24.88 16.88 ],[0.931 0.946 0.97"
928	"3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ndisp('');\n\nfprintf("
929	"'','COMMENT: end icon text');"
930	MaskIconFrame off
931	MaskIconOpaque on
932	MaskIconRotate "none"
933	MaskPortRotate "default"
934	MaskIconUnits "autoscale"
935	MaskValueString "EDK pcore generation\|\|<qt bgcolor=\"#FFFFFF\"><div><img src=\"C:/Xilinx/13.4/ISE_DS/ISE/s"
936	"ysgen/data/images/registerplus.gif\"> <<capturePeriod>><br></div><div><img src=\"C:/Xilinx/13.4/ISE_"
937	"DS/ISE/sysgen/data/images/registerplus.gif\"> <<capturedOutput>><br></div></qt>\|<empty>\|{'exposed'=>"
938	"[],'portdir'=>[],'portname'=>[],'shortname'=>[]}\|\|PLB\|0x80000000\|\|off\|\|on\|\|on\|\|\|off\|\|\|on\|plb\|{}\|0\|{'mladdr'=>[0."
939	"00000000000000000,0.00000000000000000],'mlist'=>['prng_useriosrc/From Register','prng_useriosrc/To Register'],'m"
940	"lname'=>['\\\\'capturePeriod\\\\'','\\\\'capturedOutput\\\\''],'mlstate'=>[0.00000000000000000,0.000000000000000"
941	"00]}\|{}\|off\|\|default\|0\|-1,-1,-1,-1\|edkprocessor\|2.7\|62,64,-1,-1,white,blue,0,07734,right,,[ ],[ ]\|fprintf('','CO"
942	"MMENT: begin icon graphics');\npatch([0 62 62 0 0 ],[0 0 64 64 0 ],[0.77 0.82 0.91 ]);\nplot([0 62 62 0 0 ],[0 0"
943	" 64 64 0 ]);\npatch([13.2 24.76 32.76 40.76 48.76 32.76 21.2 13.2 ],[40.88 40.88 48.88 40.88 48.88 48.88 48.88 4"
944	"0.88 ],[1 1 1 ]);\npatch([21.2 32.76 24.76 13.2 21.2 ],[32.88 32.88 40.88 40.88 32.88 ],[0.931 0.946 0.973 ]);\n"
945	"patch([13.2 24.76 32.76 21.2 13.2 ],[24.88 24.88 32.88 32.88 24.88 ],[1 1 1 ]);\npatch([21.2 48.76 40.76 32.76 2"
946	"4.76 13.2 21.2 ],[16.88 16.88 24.88 16.88 24.88 24.88 16.88 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end i"
947	"con graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\|{'table'=>{'Avai"
948	"lableMemories'=>'popup(<empty>)'}}\|"
949	System {
950	Name "EDK Processor"
951	Location [514, 91, 900, 269]
952	Open off
953	ModelBrowserVisibility off
954	ModelBrowserWidth 200
955	ScreenColor "white"
956	PaperOrientation "landscape"
957	PaperPositionMode "auto"
958	PaperType "usletter"
959	PaperUnits "inches"
960	TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
961	TiledPageScale 1
962	ShowPageBoundaries off
963	ZoomFactor "100"
964	SIDHighWatermark "293"
965	Block {
966	BlockType Constant
967	Name "Constant"
968	SID "11:277"
969	Position [40, 125, 60, 145]
970	ShowName off
971	}
972	Block {
973	BlockType Constant
974	Name "Constant1"
975	SID "11:279"
976	Position [40, 190, 60, 210]
977	ShowName off
978	}
979	Block {
980	BlockType Constant
981	Name "Constant2"
982	SID "11:281"
983	Position [40, 260, 60, 280]
984	ShowName off
985	}
986	Block {
987	BlockType Constant
988	Name "Constant3"
989	SID "11:283"
990	Position [40, 325, 60, 345]
991	ShowName off
992	}
993	Block {
994	BlockType Constant
995	Name "Constant4"
996	SID "11:285"
997	Position [40, 395, 60, 415]
998	ShowName off
999	}
1000	Block {
1001	BlockType Reference
1002	Name "Constant5"
1003	SID "11:287"
1004	Ports [0, 1]
1005	Position [20, 52, 75, 78]
1006	ShowName off
1007	LibraryVersion "1.2"
1008	SourceBlock "xbsIndex_r4/Constant"
1009	SourceType "Xilinx Constant Block Block"
1010	const "0"
1011	gui_display_data_type "Fixed-point"
1012	arith_type "Unsigned"
1013	n_bits "1"
1014	bin_pt "0"
1015	preci_type "Single"
1016	exp_width "8"
1017	frac_width "24"
1018	explicit_period on
1019	period "xlGetNormalizedPeriod()"
1020	dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block."
1021	equ "P=C"
1022	opselect "C"
1023	inp2 "PCIN>>17"
1024	opr "+"
1025	inp1 "P"
1026	carry "CIN"
1027	dbl_ovrd off
1028	has_advanced_control "0"
1029	sggui_pos "-1,-1,-1,-1"
1030	block_type "constant"
1031	sg_icon_stat "55,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]"
1032	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91"
1033	" ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[16.33 16.3"
1034	"3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 13.33 16.33 16"
1035	".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1"
1036	" 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946"
1037	" 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port"
1038	"_label('output',1,'0');\nfprintf('','COMMENT: end icon text');"
1039	Port {
1040	PortNumber 1
1041	Name "Sl_wait"
1042	RTWStorageClass "Auto"
1043	DataLoggingNameMode "SignalName"
1044	}
1045	}
1046	Block {
1047	BlockType Constant
1048	Name "Constant6"
1049	SID "11:288"
1050	Position [40, 495, 60, 515]
1051	ShowName off
1052	}
1053	Block {
1054	BlockType Reference
1055	Name "From Register"
1056	SID "11:291"
1057	Ports [0, 1]
1058	Position [400, 582, 460, 638]
1059	AttributesFormatString "<< %<shared_memory_name> >>"
1060	LibraryVersion "1.2"
1061	SourceBlock "xbsIndex_r4/From Register"
1062	SourceType "Xilinx Shared Memory Based From Register Block"
1063	infoedit "Register block that reads data to a shared memory register. Delay of one sample period."
1064	shared_memory_name "'capturedOutput'"
1065	init "0"
1066	period "xlGetNormalizedPeriod()"
1067	ownership "Owned and initialized elsewhere"
1068	gui_display_data_type "Fixed-point"
1069	arith_type "Unsigned"
1070	n_bits "16"
1071	bin_pt "0"
1072	preci_type "Single"
1073	dbl_ovrd off
1074	xl_use_area off
1075	xl_area "[0,0,0,0,0,0,0]"
1076	has_advanced_control "0"
1077	sggui_pos "-1,-1,-1,-1"
1078	block_type "fromreg"
1079	sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]"
1080	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
1081	" ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
1082	"8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
1083	"[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
1084	"2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
1085	"'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d"
1086	"out');\nfprintf('','COMMENT: end icon text');"
1087	Port {
1088	PortNumber 1
1089	Name "capturedOutput_dout"
1090	RTWStorageClass "Auto"
1091	DataLoggingNameMode "SignalName"
1092	}
1093	}
1094	Block {
1095	BlockType Reference
1096	Name "PLB_ABus"
1097	SID "11:280"
1098	Ports [1, 1]
1099	Position [175, 190, 245, 210]
1100	LibraryVersion "1.2"
1101	SourceBlock "xbsIndex_r4/Gateway In"
1102	SourceType "Xilinx Gateway In Block"
1103	infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx"
1104	" fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top level input p"
1105	"orts."
1106	gui_display_data_type "Fixed-point"
1107	arith_type "Unsigned"
1108	n_bits "32"
1109	bin_pt "0"
1110	preci_type "Single"
1111	exp_width "8"
1112	frac_width "24"
1113	quantization "Round (unbiased: +/- Inf)"
1114	overflow "Saturate"
1115	period "xlGetNormalizedPeriod()"
1116	dbl_ovrd off
1117	timing_constraint "None"
1118	locs_specified off
1119	LOCs "{}"
1120	xl_use_area off
1121	xl_area "[0,0,0,0,0,0,0]"
1122	inherit_from_input off
1123	UseAsADC off
1124	ADCChannel "'1'"
1125	hdl_port "on"
1126	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_ABus'}},'iopad'=>{'constraint'=>'#'}}"
1127	has_advanced_control "0"
1128	sggui_pos "-1,-1,-1,-1"
1129	block_type "gatewayin"
1130	sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
1131	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1132	" ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1"
1133	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10"
1134	".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1135	"h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1136	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1137	"\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
1138	"on text');"
1139	Port {
1140	PortNumber 1
1141	Name "PLB_ABus"
1142	RTWStorageClass "Auto"
1143	DataLoggingNameMode "SignalName"
1144	}
1145	}
1146	Block {
1147	BlockType Reference
1148	Name "PLB_PAValid"
1149	SID "11:282"
1150	Ports [1, 1]
1151	Position [175, 260, 245, 280]
1152	LibraryVersion "1.2"
1153	SourceBlock "xbsIndex_r4/Gateway In"
1154	SourceType "Xilinx Gateway In Block"
1155	infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx"
1156	" fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top level input p"
1157	"orts."
1158	gui_display_data_type "Fixed-point"
1159	arith_type "Unsigned"
1160	n_bits "1"
1161	bin_pt "0"
1162	preci_type "Single"
1163	exp_width "8"
1164	frac_width "24"
1165	quantization "Round (unbiased: +/- Inf)"
1166	overflow "Saturate"
1167	period "xlGetNormalizedPeriod()"
1168	dbl_ovrd off
1169	timing_constraint "None"
1170	locs_specified off
1171	LOCs "{}"
1172	xl_use_area off
1173	xl_area "[0,0,0,0,0,0,0]"
1174	inherit_from_input off
1175	UseAsADC off
1176	ADCChannel "'1'"
1177	hdl_port "on"
1178	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_PAValid'}},'iopad'=>{'constraint'=>'#'}}"
1179	has_advanced_control "0"
1180	sggui_pos "-1,-1,-1,-1"
1181	block_type "gatewayin"
1182	sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
1183	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1184	" ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1"
1185	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10"
1186	".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1187	"h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1188	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1189	"\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
1190	"on text');"
1191	Port {
1192	PortNumber 1
1193	Name "PLB_PAValid"
1194	RTWStorageClass "Auto"
1195	DataLoggingNameMode "SignalName"
1196	}
1197	}
1198	Block {
1199	BlockType Reference
1200	Name "PLB_RNW"
1201	SID "11:284"
1202	Ports [1, 1]
1203	Position [175, 325, 245, 345]
1204	LibraryVersion "1.2"
1205	SourceBlock "xbsIndex_r4/Gateway In"
1206	SourceType "Xilinx Gateway In Block"
1207	infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx"
1208	" fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top level input p"
1209	"orts."
1210	gui_display_data_type "Fixed-point"
1211	arith_type "Unsigned"
1212	n_bits "1"
1213	bin_pt "0"
1214	preci_type "Single"
1215	exp_width "8"
1216	frac_width "24"
1217	quantization "Round (unbiased: +/- Inf)"
1218	overflow "Saturate"
1219	period "xlGetNormalizedPeriod()"
1220	dbl_ovrd off
1221	timing_constraint "None"
1222	locs_specified off
1223	LOCs "{}"
1224	xl_use_area off
1225	xl_area "[0,0,0,0,0,0,0]"
1226	inherit_from_input off
1227	UseAsADC off
1228	ADCChannel "'1'"
1229	hdl_port "on"
1230	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_RNW'}},'iopad'=>{'constraint'=>'#'}}"
1231	has_advanced_control "0"
1232	sggui_pos "-1,-1,-1,-1"
1233	block_type "gatewayin"
1234	sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
1235	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1236	" ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1"
1237	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10"
1238	".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1239	"h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1240	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1241	"\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
1242	"on text');"
1243	Port {
1244	PortNumber 1
1245	Name "PLB_RNW"
1246	RTWStorageClass "Auto"
1247	DataLoggingNameMode "SignalName"
1248	}
1249	}
1250	Block {
1251	BlockType Reference
1252	Name "PLB_wrDBus"
1253	SID "11:286"
1254	Ports [1, 1]
1255	Position [175, 395, 245, 415]
1256	LibraryVersion "1.2"
1257	SourceBlock "xbsIndex_r4/Gateway In"
1258	SourceType "Xilinx Gateway In Block"
1259	infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx"
1260	" fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top level input p"
1261	"orts."
1262	gui_display_data_type "Fixed-point"
1263	arith_type "Unsigned"
1264	n_bits "32"
1265	bin_pt "0"
1266	preci_type "Single"
1267	exp_width "8"
1268	frac_width "24"
1269	quantization "Round (unbiased: +/- Inf)"
1270	overflow "Saturate"
1271	period "xlGetNormalizedPeriod()"
1272	dbl_ovrd off
1273	timing_constraint "None"
1274	locs_specified off
1275	LOCs "{}"
1276	xl_use_area off
1277	xl_area "[0,0,0,0,0,0,0]"
1278	inherit_from_input off
1279	UseAsADC off
1280	ADCChannel "'1'"
1281	hdl_port "on"
1282	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_wrDBus'}},'iopad'=>{'constraint'=>'#'}}"
1283	has_advanced_control "0"
1284	sggui_pos "-1,-1,-1,-1"
1285	block_type "gatewayin"
1286	sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
1287	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1288	" ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1"
1289	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10"
1290	".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1291	"h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1292	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1293	"\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
1294	"on text');"
1295	Port {
1296	PortNumber 1
1297	Name "PLB_wrDBus"
1298	RTWStorageClass "Auto"
1299	DataLoggingNameMode "SignalName"
1300	}
1301	}
1302	Block {
1303	BlockType Reference
1304	Name "SPLB_Rst"
1305	SID "11:278"
1306	Ports [1, 1]
1307	Position [175, 125, 245, 145]
1308	LibraryVersion "1.2"
1309	SourceBlock "xbsIndex_r4/Gateway In"
1310	SourceType "Xilinx Gateway In Block"
1311	infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx"
1312	" fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top level input p"
1313	"orts."
1314	gui_display_data_type "Fixed-point"
1315	arith_type "Unsigned"
1316	n_bits "1"
1317	bin_pt "0"
1318	preci_type "Single"
1319	exp_width "8"
1320	frac_width "24"
1321	quantization "Round (unbiased: +/- Inf)"
1322	overflow "Saturate"
1323	period "xlGetNormalizedPeriod()"
1324	dbl_ovrd off
1325	timing_constraint "None"
1326	locs_specified off
1327	LOCs "{}"
1328	xl_use_area off
1329	xl_area "[0,0,0,0,0,0,0]"
1330	inherit_from_input off
1331	UseAsADC off
1332	ADCChannel "'1'"
1333	hdl_port "on"
1334	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'SPLB_Rst'}},'iopad'=>{'constraint'=>'#'}}"
1335	has_advanced_control "0"
1336	sggui_pos "-1,-1,-1,-1"
1337	block_type "gatewayin"
1338	sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
1339	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1340	" ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1"
1341	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10"
1342	".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1343	"h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1344	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1345	"\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
1346	"on text');"
1347	Port {
1348	PortNumber 1
1349	Name "SPLB_Rst"
1350	RTWStorageClass "Auto"
1351	DataLoggingNameMode "SignalName"
1352	}
1353	}
1354	Block {
1355	BlockType Reference
1356	Name "Sl_addrAck"
1357	SID "11:264"
1358	Ports [1, 1]
1359	Position [670, 70, 730, 90]
1360	LibraryVersion "1.2"
1361	SourceBlock "xbsIndex_r4/Gateway Out"
1362	SourceType "Xilinx Gateway Out Block"
1363	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
1364	"link integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top level out"
1365	"put ports or are discarded, depending on how they are configured."
1366	inherit_from_input off
1367	hdl_port on
1368	timing_constraint "None"
1369	locs_specified off
1370	LOCs "{}"
1371	xl_use_area off
1372	xl_area "[0,0,0,0,0,0,0]"
1373	UseAsDAC off
1374	DACChannel "'1'"
1375	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_addrAck'}},'iopad'=>{'constraint'=>'#'}}"
1376	has_advanced_control "0"
1377	sggui_pos "-1,-1,-1,-1"
1378	block_type "gatewayout"
1379	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
1380	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1381	" ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
1382	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
1383	".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1384	"h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1385	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1386	" ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
1387	"con text');"
1388	}
1389	Block {
1390	BlockType Reference
1391	Name "Sl_rdComp"
1392	SID "11:266"
1393	Ports [1, 1]
1394	Position [670, 135, 730, 155]
1395	LibraryVersion "1.2"
1396	SourceBlock "xbsIndex_r4/Gateway Out"
1397	SourceType "Xilinx Gateway Out Block"
1398	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
1399	"link integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top level out"
1400	"put ports or are discarded, depending on how they are configured."
1401	inherit_from_input off
1402	hdl_port on
1403	timing_constraint "None"
1404	locs_specified off
1405	LOCs "{}"
1406	xl_use_area off
1407	xl_area "[0,0,0,0,0,0,0]"
1408	UseAsDAC off
1409	DACChannel "'1'"
1410	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdComp'}},'iopad'=>{'constraint'=>'#'}}"
1411	has_advanced_control "0"
1412	sggui_pos "-1,-1,-1,-1"
1413	block_type "gatewayout"
1414	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
1415	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1416	" ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
1417	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
1418	".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1419	"h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1420	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1421	" ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
1422	"con text');"
1423	}
1424	Block {
1425	BlockType Reference
1426	Name "Sl_rdDAck"
1427	SID "11:268"
1428	Ports [1, 1]
1429	Position [670, 640, 730, 660]
1430	LibraryVersion "1.2"
1431	SourceBlock "xbsIndex_r4/Gateway Out"
1432	SourceType "Xilinx Gateway Out Block"
1433	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
1434	"link integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top level out"
1435	"put ports or are discarded, depending on how they are configured."
1436	inherit_from_input off
1437	hdl_port on
1438	timing_constraint "None"
1439	locs_specified off
1440	LOCs "{}"
1441	xl_use_area off
1442	xl_area "[0,0,0,0,0,0,0]"
1443	UseAsDAC off
1444	DACChannel "'1'"
1445	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDAck'}},'iopad'=>{'constraint'=>'#'}}"
1446	has_advanced_control "0"
1447	sggui_pos "-1,-1,-1,-1"
1448	block_type "gatewayout"
1449	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
1450	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1451	" ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
1452	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
1453	".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1454	"h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1455	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1456	" ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
1457	"con text');"
1458	}
1459	Block {
1460	BlockType Reference
1461	Name "Sl_rdDBus"
1462	SID "11:270"
1463	Ports [1, 1]
1464	Position [670, 705, 730, 725]
1465	LibraryVersion "1.2"
1466	SourceBlock "xbsIndex_r4/Gateway Out"
1467	SourceType "Xilinx Gateway Out Block"
1468	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
1469	"link integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top level out"
1470	"put ports or are discarded, depending on how they are configured."
1471	inherit_from_input off
1472	hdl_port on
1473	timing_constraint "None"
1474	locs_specified off
1475	LOCs "{}"
1476	xl_use_area off
1477	xl_area "[0,0,0,0,0,0,0]"
1478	UseAsDAC off
1479	DACChannel "'1'"
1480	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDBus'}},'iopad'=>{'constraint'=>'#'}}"
1481	has_advanced_control "0"
1482	sggui_pos "-1,-1,-1,-1"
1483	block_type "gatewayout"
1484	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
1485	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1486	" ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
1487	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
1488	".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1489	"h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1490	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1491	" ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
1492	"con text');"
1493	}
1494	Block {
1495	BlockType Reference
1496	Name "Sl_wait"
1497	SID "11:272"
1498	Ports [1, 1]
1499	Position [180, 50, 240, 70]
1500	LibraryVersion "1.2"
1501	SourceBlock "xbsIndex_r4/Gateway Out"
1502	SourceType "Xilinx Gateway Out Block"
1503	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
1504	"link integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top level out"
1505	"put ports or are discarded, depending on how they are configured."
1506	inherit_from_input off
1507	hdl_port on
1508	timing_constraint "None"
1509	locs_specified off
1510	LOCs "{}"
1511	xl_use_area off
1512	xl_area "[0,0,0,0,0,0,0]"
1513	UseAsDAC off
1514	DACChannel "'1'"
1515	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wait'}},'iopad'=>{'constraint'=>'#'}}"
1516	has_advanced_control "0"
1517	sggui_pos "-1,-1,-1,-1"
1518	block_type "gatewayout"
1519	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
1520	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1521	" ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
1522	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
1523	".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1524	"h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1525	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1526	" ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
1527	"con text');"
1528	}
1529	Block {
1530	BlockType Reference
1531	Name "Sl_wrComp"
1532	SID "11:276"
1533	Ports [1, 1]
1534	Position [670, 270, 730, 290]
1535	LibraryVersion "1.2"
1536	SourceBlock "xbsIndex_r4/Gateway Out"
1537	SourceType "Xilinx Gateway Out Block"
1538	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
1539	"link integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top level out"
1540	"put ports or are discarded, depending on how they are configured."
1541	inherit_from_input off
1542	hdl_port on
1543	timing_constraint "None"
1544	locs_specified off
1545	LOCs "{}"
1546	xl_use_area off
1547	xl_area "[0,0,0,0,0,0,0]"
1548	UseAsDAC off
1549	DACChannel "'1'"
1550	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrComp'}},'iopad'=>{'constraint'=>'#'}}"
1551	has_advanced_control "0"
1552	sggui_pos "-1,-1,-1,-1"
1553	block_type "gatewayout"
1554	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
1555	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1556	" ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
1557	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
1558	".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1559	"h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1560	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1561	" ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
1562	"con text');"
1563	}
1564	Block {
1565	BlockType Reference
1566	Name "Sl_wrDAck"
1567	SID "11:274"
1568	Ports [1, 1]
1569	Position [670, 205, 730, 225]
1570	LibraryVersion "1.2"
1571	SourceBlock "xbsIndex_r4/Gateway Out"
1572	SourceType "Xilinx Gateway Out Block"
1573	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
1574	"link integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top level out"
1575	"put ports or are discarded, depending on how they are configured."
1576	inherit_from_input off
1577	hdl_port on
1578	timing_constraint "None"
1579	locs_specified off
1580	LOCs "{}"
1581	xl_use_area off
1582	xl_area "[0,0,0,0,0,0,0]"
1583	UseAsDAC off
1584	DACChannel "'1'"
1585	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrDAck'}},'iopad'=>{'constraint'=>'#'}}"
1586	has_advanced_control "0"
1587	sggui_pos "-1,-1,-1,-1"
1588	block_type "gatewayout"
1589	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
1590	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1591	" ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
1592	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
1593	".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1594	"h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1595	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1596	" ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
1597	"con text');"
1598	}
1599	Block {
1600	BlockType Terminator
1601	Name "Terminator"
1602	SID "11:263"
1603	Position [905, 70, 925, 90]
1604	ShowName off
1605	}
1606	Block {
1607	BlockType Terminator
1608	Name "Terminator1"
1609	SID "11:265"
1610	Position [905, 135, 925, 155]
1611	ShowName off
1612	}
1613	Block {
1614	BlockType Terminator
1615	Name "Terminator2"
1616	SID "11:267"
1617	Position [905, 640, 925, 660]
1618	ShowName off
1619	}
1620	Block {
1621	BlockType Terminator
1622	Name "Terminator3"
1623	SID "11:269"
1624	Position [905, 705, 925, 725]
1625	ShowName off
1626	}
1627	Block {
1628	BlockType Terminator
1629	Name "Terminator4"
1630	SID "11:271"
1631	Position [420, 50, 440, 70]
1632	ShowName off
1633	}
1634	Block {
1635	BlockType Terminator
1636	Name "Terminator5"
1637	SID "11:273"
1638	Position [905, 205, 925, 225]
1639	ShowName off
1640	}
1641	Block {
1642	BlockType Terminator
1643	Name "Terminator6"
1644	SID "11:275"
1645	Position [905, 270, 925, 290]
1646	ShowName off
1647	}
1648	Block {
1649	BlockType Reference
1650	Name "To Register"
1651	SID "11:292"
1652	Ports [2, 1]
1653	Position [885, 507, 945, 563]
1654	AttributesFormatString "<< %<shared_memory_name> >>"
1655	LibraryVersion "1.2"
1656	SourceBlock "xbsIndex_r4/To Register"
1657	SourceType "Xilinx Shared Memory Based To Register Block"
1658	infoedit "Register block that writes data to a shared memory register. Delay of one sample period."
1659	shared_memory_name "'capturePeriod'"
1660	init "0"
1661	ownership "Owned and initialized elsewhere"
1662	explicit_data_type on
1663	gui_display_data_type "Fixed-point"
1664	arith_type "Unsigned"
1665	n_bits "32"
1666	bin_pt "0"
1667	preci_type "Single"
1668	dbl_ovrd off
1669	xl_use_area off
1670	xl_area "[0,0,0,0,0,0,0]"
1671	has_advanced_control "0"
1672	sggui_pos "-1,-1,-1,-1"
1673	block_type "toreg"
1674	sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]"
1675	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
1676	" ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
1677	"8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
1678	"[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
1679	"2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
1680	"'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di"
1681	"n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN"
1682	"T: end icon text');"
1683	Port {
1684	PortNumber 1
1685	Name "capturePeriod_dout"
1686	RTWStorageClass "Auto"
1687	DataLoggingNameMode "SignalName"
1688	}
1689	}
1690	Block {
1691	BlockType Reference
1692	Name "plb_decode"
1693	SID "11:290"
1694	Ports [7, 9]
1695	Position [345, 124, 515, 536]
1696	LibraryVersion "1.2"
1697	SourceBlock "xbsIndex_r4/MCode"
1698	SourceType "Xilinx MCode Block Block"
1699	infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of t"
1700	"he block are input arguments of the function. The output ports of the block are output arguments of the function."
1701	mfname "xlmax"
1702	explicit_period off
1703	period "1"
1704	dbl_ovrd off
1705	enable_stdout off
1706	enable_debug off
1707	xl_use_area off
1708	xl_area "[0,0,0,0,0,0,0]"
1709	mfilecontent "function [wrDBusReg, addrAck, rdComp, wrDAck, bankAddr, RNWReg, rdDAck, rdDBus, linearAddr] = plb_"
1710	"bus_decode(plbRst, plbABus, plbPAValid, plbRNW, plbWrDBus, rdData, addrPref)\n\n% constant variables (TODO: should "
1711	"pass from outside)\nADDRPREF_LEN = 20;\nBANKADDR_LEN = 2;\nLINEARADDR_LEN = 8;\nABUS_LEN = 32;\nDBUS_LEN = 32;\n\n%"
1712	" declare and initialize persistent variables\n% register input bus signals\npersistent plbRstReg_, plbRstReg_ = xl_"
1713	"state(0, {xlBoolean});\npersistent plbABusReg_, plbABusReg_ = xl_state(0, {xlUnsigned, ABUS_LEN, 0});\npersistent p"
1714	"lbPAValidReg_, plbPAValidReg_ = xl_state(0, {xlBoolean});\npersistent plbRNWReg_, plbRNWReg_ = xl_state(0, {xlUnsig"
1715	"ned, 1, 0});\npersistent plbWrDBusReg_, plbWrDBusReg_ = xl_state(0, {xlUnsigned, DBUS_LEN, 0});\n\n% ===== rest of "
1716	"the outputs =====\n\nbankAddr = xl_slice(plbABusReg_, 2+BANKADDR_LEN+LINEARADDR_LEN-1, 2+LINEARADDR_LEN);\nlinear"
1717	"Addr = xl_slice(plbABusReg_, 2+LINEARADDR_LEN-1, 2);\nRNWReg = plbRNWReg_;\nwrDBusReg = plbWrDBusReg_;\n\n% ===== p"
1718	"_select =====\n\n% register PAValid\npersistent aValidReg, aValidReg = xl_state(0, {xlBoolean});\naValidReg = plbPA"
1719	"ValidReg_;\n\n% extract and register the address prefix\naddrPref_in = xl_slice(plbABusReg_, xl_nbits(plbABusReg_)-"
1720	"1, xl_nbits(plbABusReg_)-ADDRPREF_LEN);\nif addrPref_in == addrPref\n ps1 = true;\nelse \n ps1 = false;\nend "
1721	"\n\npersistent ps1Reg, ps1Reg = xl_state(0, ps1);\nps1Reg = ps1;\n\nps = xl_and(ps1Reg, aValidReg);\n\n% ===== addr"
1722	"Ack =====\n\n% register ps\npersistent psReg, psReg = xl_state(0, ps);\n\naddrAck = xfix({xlUnsigned, 1, 0}, xl_and"
1723	"(xl_not(plbRstReg_), ps, xl_not(psReg)));\n\npsReg = ps;\n\n% ===== rdComp, rd/wr DAck =====\n \nrdComp1 = xfix({xl"
1724	"Unsigned, 1, 0}, xl_and(addrAck, RNWReg));\n\nNUM_rdCompDelay = 3;\npersistent rdCompDelay, rdCompDelay = xl_state("
1725	"zeros(1, NUM_rdCompDelay), rdComp1, NUM_rdCompDelay);\nrdComp2 = rdCompDelay.back;\nrdCompDelay.push_front_pop_back"
1726	"(rdComp1);\n\npersistent rdCompReg, rdCompReg = xl_state(0, rdComp1);\nrdComp = rdCompReg;\nrdCompReg = rdComp2;\n\n"
1727	"persistent rdDAckReg, rdDAckReg = xl_state(0, rdComp1);\nrdDAck = rdDAckReg;\nrdDAckReg = rdComp;\n\npersistent wrD"
1728	"AckReg, wrDAckReg = xl_state(0, addrAck);\nwrDAck = wrDAckReg;\nwrDAckReg = xl_and(addrAck, xl_not(RNWReg));\n\n% ="
1729	"==== rdDBus =====\n\nrdSel = xl_or(rdComp2, rdComp);\n\nif rdSel == 1\n rdDBus1 = rdData;\nelse\n rdDBus1 = 0"
1730	";\nend % if\n\npersistent rdDBusReg, rdDBusReg = xl_state(0, rdDBus1);\nrdDBus = rdDBusReg;\nrdDBusReg = rdDBus1;\n"
1731	"\n% rdDBus = xl_concat(rdDBus32, rdDBus32);\n% rdDBus = rdDBus32;\n\n% ===== update the persistent variables =====\n"
1732	"\nplbRstReg_ = plbRst;\nplbABusReg_ = plbABus;\nplbPAValidReg_ = plbPAValid;\nplbRNWReg_ = plbRNW;\nplbWrDBusReg_ ="
1733	" xl_slice(plbWrDBus, DBUS_LEN-1, 0);\n"
1734	suppress_output "on"
1735	defparams "{}"
1736	hide_port_list "{}"
1737	has_advanced_control "0"
1738	sggui_pos "-1,-1,-1,-1"
1739	block_type "mcode"
1740	sg_icon_stat "170,412,7,9,white,blue,0,43a237d5,right,,[ ],[ ]"
1741	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 0 ],[0 0 412 412 0 ],[0.77 0.82 "
1742	"0.91 ]);\nplot([0 170 170 0 0 ],[0 0 412 412 0 ]);\npatch([31.6 66.28 90.28 114.28 138.28 90.28 55.6 31.6 ],[232.64"
1743	" 232.64 256.64 232.64 256.64 256.64 256.64 232.64 ],[1 1 1 ]);\npatch([55.6 90.28 66.28 31.6 55.6 ],[208.64 208.64 "
1744	"232.64 232.64 208.64 ],[0.931 0.946 0.973 ]);\npatch([31.6 66.28 90.28 55.6 31.6 ],[184.64 184.64 208.64 208.64 184"
1745	".64 ],[1 1 1 ]);\npatch([55.6 138.28 114.28 90.28 66.28 31.6 55.6 ],[160.64 160.64 184.64 160.64 184.64 184.64 160."
1746	"64 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nco"
1747	"lor('black');port_label('input',1,'plbRst');\ncolor('black');port_label('input',2,'plbABus');\ncolor('black');port_"
1748	"label('input',3,'plbPAValid');\ncolor('black');port_label('input',4,'plbRNW');\ncolor('black');port_label('input',5"
1749	",'plbWrDBus');\ncolor('black');port_label('input',6,'rdData');\ncolor('black');port_label('input',7,'addrPref');\nc"
1750	"olor('black');port_label('output',1,'wrDBusReg');\ncolor('black');port_label('output',2,'addrAck');\ncolor('black')"
1751	";port_label('output',3,'rdComp');\ncolor('black');port_label('output',4,'wrDAck');\ncolor('black');port_label('outp"
1752	"ut',5,'bankAddr');\ncolor('black');port_label('output',6,'RNWReg');\ncolor('black');port_label('output',7,'rdDAck')"
1753	";\ncolor('black');port_label('output',8,'rdDBus');\ncolor('black');port_label('output',9,'linearAddr');\ncolor('bla"
1754	"ck');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');"
1755	Port {
1756	PortNumber 1
1757	Name "wrDBusReg"
1758	RTWStorageClass "Auto"
1759	DataLoggingNameMode "SignalName"
1760	}
1761	Port {
1762	PortNumber 2
1763	Name "Sl_addrAck"
1764	RTWStorageClass "Auto"
1765	DataLoggingNameMode "SignalName"
1766	}
1767	Port {
1768	PortNumber 3
1769	Name "Sl_rdComp"
1770	RTWStorageClass "Auto"
1771	DataLoggingNameMode "SignalName"
1772	}
1773	Port {
1774	PortNumber 4
1775	Name "Sl_wrDAck"
1776	RTWStorageClass "Auto"
1777	DataLoggingNameMode "SignalName"
1778	}
1779	Port {
1780	PortNumber 5
1781	Name "bankAddr"
1782	RTWStorageClass "Auto"
1783	DataLoggingNameMode "SignalName"
1784	}
1785	Port {
1786	PortNumber 6
1787	Name "RNWReg"
1788	RTWStorageClass "Auto"
1789	DataLoggingNameMode "SignalName"
1790	}
1791	Port {
1792	PortNumber 7
1793	Name "Sl_rdDAck"
1794	RTWStorageClass "Auto"
1795	DataLoggingNameMode "SignalName"
1796	}
1797	Port {
1798	PortNumber 8
1799	Name "Sl_rdDBus"
1800	RTWStorageClass "Auto"
1801	DataLoggingNameMode "SignalName"
1802	}
1803	Port {
1804	PortNumber 9
1805	Name "linearAddr"
1806	RTWStorageClass "Auto"
1807	DataLoggingNameMode "SignalName"
1808	}
1809	}
1810	Block {
1811	BlockType Reference
1812	Name "plb_memmap"
1813	SID "11:293"
1814	Ports [7, 3]
1815	Position [615, 340, 785, 590]
1816	LibraryVersion "1.2"
1817	SourceBlock "xbsIndex_r4/MCode"
1818	SourceType "Xilinx MCode Block Block"
1819	infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of t"
1820	"he block are input arguments of the function. The output ports of the block are output arguments of the function."
1821	mfname "xlmax"
1822	explicit_period off
1823	period "1"
1824	dbl_ovrd off
1825	enable_stdout off
1826	enable_debug off
1827	xl_use_area off
1828	xl_area "[0,0,0,0,0,0,0]"
1829	mfilecontent "function [read_bank_out, sm_capturePeriod_din, sm_capturePeriod_en] = plb_memmap(wrDBus, bankAddr,"
1830	" linearAddr, RNWReg, addrAck, sm_capturedOutput, sm_capturePeriod)\n\n\n% connvert the input data to UFix_32_0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% sm_capturedOutput_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_capturedOutp"
1832	"ut_bus = xl_force(sm_capturedOutput, xlUnsigned, 0);\n\n% 'To Register' blocks\n\n% sm_capturePeriod_dout = xfix({x"
1833	"lUnsigned, 32, 0}, 0);\nsm_capturePeriod_dout = xl_force(sm_capturePeriod, xlUnsigned, 0);\n\n\n% 'From FIFO' block"
1834	"s\n% 'To FIFO' blocks\n% 'Shared Memory' blocks\n\n% 'dout' ports of 'From Register' blocks\n\n% registered registe"
1835	"r mux output\npersistent reg_bank_out_reg; reg_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nreg_bank_out = reg"
1836	"_bank_out_reg;\n\nif linearAddr == 1\n reg_bank_out_reg = sm_capturedOutput_bus;\nelseif linearAddr == 0\n re"
1837	"g_bank_out_reg = sm_capturePeriod_dout;\n\nend\n\n\n% 'From FIFO' and 'To FIFO' blocks\n\n\n\n\n\nopCode = xl_conca"
1838	"t(addrAck, RNWReg, bankAddr, linearAddr);\n\n% 'Shared Memory' blocks\n\n\n\n\n\n% 'din' ports of 'Shared Memory' b"
1839	"locks\n\n\n% 'we' ports of 'Shared Memory' blocks\n\n\n% 'addr' ports of 'Shared Memory' blocks\n\n\n% 're' ports o"
1840	"f 'From FIFO' blocks\n\n\n% 'en' ports of 'To Register' blocks\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10)"
1841	", ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 0))\n sm_capturePeriod_en = true;\nels"
1842	"e\n sm_capturePeriod_en = false;\nend\n\n\n% 'din' ports of 'To FIFO' blocks\n\n\n% 'we' ports of 'To FIFO' bloc"
1843	"ks\n\n\n% 'din' ports of 'To Register' blocks\nsm_capturePeriod_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n "
1844	" xlUnsigned, ...\n 0);\n\n\npersistent read_bank_out_"
1845	"reg; read_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nread_bank_out = read_bank_out_reg;\n\npersistent bankAd"
1846	"dr_reg; bankAddr_reg = xl_state(0, bankAddr);\n\nif bankAddr_reg == 0\n % Bank 0: Shared Memories\n read_bank"
1847	"_out_reg = 0;\nelseif bankAddr_reg == 1\n % Bank 1: From/To FIFOs\n read_bank_out_reg = 0;\nelseif bankAddr_"
1848	"reg == 2\n % Bank 2: From/To Registers\n read_bank_out_reg = reg_bank_out;\nelseif bankAddr_reg == 3\n % B"
1849	"ank 3: Configuration Registers\n read_bank_out_reg = 0;\nend\n\nbankAddr_reg = bankAddr;\n"
1850	suppress_output "on"
1851	defparams "{}"
1852	hide_port_list "{}"
1853	has_advanced_control "0"
1854	sggui_pos "-1,-1,-1,-1"
1855	block_type "mcode"
1856	sg_icon_stat "170,250,7,3,white,blue,0,b2a559b2,right,,[ ],[ ]"
1857	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 0 ],[0 0 250 250 0 ],[0.77 0.82 "
1858	"0.91 ]);\nplot([0 170 170 0 0 ],[0 0 250 250 0 ]);\npatch([31.6 66.28 90.28 114.28 138.28 90.28 55.6 31.6 ],[151.64"
1859	" 151.64 175.64 151.64 175.64 175.64 175.64 151.64 ],[1 1 1 ]);\npatch([55.6 90.28 66.28 31.6 55.6 ],[127.64 127.64 "
1860	"151.64 151.64 127.64 ],[0.931 0.946 0.973 ]);\npatch([31.6 66.28 90.28 55.6 31.6 ],[103.64 103.64 127.64 127.64 103"
1861	".64 ],[1 1 1 ]);\npatch([55.6 138.28 114.28 90.28 66.28 31.6 55.6 ],[79.64 79.64 103.64 79.64 103.64 103.64 79.64 ]"
1862	",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor("
1863	"'black');port_label('input',1,'wrDBus');\ncolor('black');port_label('input',2,'bankAddr');\ncolor('black');port_lab"
1864	"el('input',3,'linearAddr');\ncolor('black');port_label('input',4,'RNWReg');\ncolor('black');port_label('input',5,'a"
1865	"ddrAck');\ncolor('black');port_label('input',6,'sm_capturedOutput');\ncolor('black');port_label('input',7,'sm_captu"
1866	"rePeriod');\ncolor('black');port_label('output',1,'read_bank_out');\ncolor('black');port_label('output',2,'sm_captu"
1867	"rePeriod_din');\ncolor('black');port_label('output',3,'sm_capturePeriod_en');\ncolor('black');disp('\\bf{xlmax}','t"
1868	"exmode','on');\nfprintf('','COMMENT: end icon text');"
1869	Port {
1870	PortNumber 1
1871	Name "rdData"
1872	RTWStorageClass "Auto"
1873	DataLoggingNameMode "SignalName"
1874	}
1875	Port {
1876	PortNumber 2
1877	Name "capturePeriod_din"
1878	RTWStorageClass "Auto"
1879	DataLoggingNameMode "SignalName"
1880	}
1881	Port {
1882	PortNumber 3
1883	Name "capturePeriod_en"
1884	RTWStorageClass "Auto"
1885	DataLoggingNameMode "SignalName"
1886	}
1887	}
1888	Block {
1889	BlockType Reference
1890	Name "sg_plb_addrpref"
1891	SID "11:289"
1892	Ports [1, 1]
1893	Position [175, 495, 245, 515]
1894	LibraryVersion "1.2"
1895	SourceBlock "xbsIndex_r4/Gateway In"
1896	SourceType "Xilinx Gateway In Block"
1897	infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx"
1898	" fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top level input p"
1899	"orts."
1900	gui_display_data_type "Fixed-point"
1901	arith_type "Unsigned"
1902	n_bits "20"
1903	bin_pt "0"
1904	preci_type "Single"
1905	exp_width "8"
1906	frac_width "24"
1907	quantization "Round (unbiased: +/- Inf)"
1908	overflow "Saturate"
1909	period "xlGetNormalizedPeriod()"
1910	dbl_ovrd off
1911	timing_constraint "None"
1912	locs_specified off
1913	LOCs "{}"
1914	xl_use_area off
1915	xl_area "[0,0,0,0,0,0,0]"
1916	inherit_from_input off
1917	UseAsADC off
1918	ADCChannel "'1'"
1919	hdl_port "on"
1920	sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'sg_plb_addrpref'}},'iopad'=>{'constraint'=>'"
1921	"#'}}"
1922	has_advanced_control "0"
1923	sggui_pos "-1,-1,-1,-1"
1924	block_type "gatewayin"
1925	sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
1926	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
1927	" ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1"
1928	"4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10"
1929	".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
1930	"h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
1931	"f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
1932	"\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
1933	"on text');"
1934	Port {
1935	PortNumber 1
1936	Name "addrPref"
1937	RTWStorageClass "Auto"
1938	DataLoggingNameMode "SignalName"
1939	}
1940	}
1941	Line {
1942	Name "Sl_addrAck"
1943	SrcBlock "plb_decode"
1944	SrcPort 2
1945	Points [0, 0]
1946	Branch {
1947	Labels [1, 0]
1948	DstBlock "plb_memmap"
1949	DstPort 5
1950	}
1951	Branch {
1952	Labels [0, 0]
1953	DstBlock "Sl_addrAck"
1954	DstPort 1
1955	}
1956	}
1957	Line {
1958	Name "Sl_wrDAck"
1959	SrcBlock "plb_decode"
1960	SrcPort 4
1961	Points [0, 0]
1962	Branch {
1963	Labels [1, 0]
1964	DstBlock "Sl_wrDAck"
1965	DstPort 1
1966	}
1967	Branch {
1968	Labels [0, 0]
1969	DstBlock "Sl_wrComp"
1970	DstPort 1
1971	}
1972	}
1973	Line {
1974	Name "capturePeriod_en"
1975	Labels [0, 0; 0, 0]
1976	SrcBlock "plb_memmap"
1977	SrcPort 3
1978	DstBlock "To Register"
1979	DstPort 2
1980	}
1981	Line {
1982	Name "capturePeriod_din"
1983	Labels [0, 0; 0, 0]
1984	SrcBlock "plb_memmap"
1985	SrcPort 2
1986	DstBlock "To Register"
1987	DstPort 1
1988	}
1989	Line {
1990	Name "rdData"
1991	Labels [0, 0; 0, 0]
1992	SrcBlock "plb_memmap"
1993	SrcPort 1
1994	DstBlock "plb_decode"
1995	DstPort 6
1996	}
1997	Line {
1998	Name "capturePeriod_dout"
1999	Labels [0, 0; 0, 0]
2000	SrcBlock "To Register"
2001	SrcPort 1
2002	DstBlock "plb_memmap"
2003	DstPort 7
2004	}
2005	Line {
2006	Name "capturedOutput_dout"
2007	Labels [0, 0; 0, 0]
2008	SrcBlock "From Register"
2009	SrcPort 1
2010	DstBlock "plb_memmap"
2011	DstPort 6
2012	}
2013	Line {
2014	Name "RNWReg"
2015	Labels [0, 0; 0, 0]
2016	SrcBlock "plb_decode"
2017	SrcPort 6
2018	DstBlock "plb_memmap"
2019	DstPort 4
2020	}
2021	Line {
2022	Name "linearAddr"
2023	Labels [0, 0; 0, 0]
2024	SrcBlock "plb_decode"
2025	SrcPort 9
2026	DstBlock "plb_memmap"
2027	DstPort 3
2028	}
2029	Line {
2030	Name "bankAddr"
2031	Labels [0, 0; 0, 0]
2032	SrcBlock "plb_decode"
2033	SrcPort 5
2034	DstBlock "plb_memmap"
2035	DstPort 2
2036	}
2037	Line {
2038	Name "wrDBusReg"
2039	Labels [0, 0; 0, 0]
2040	SrcBlock "plb_decode"
2041	SrcPort 1
2042	DstBlock "plb_memmap"
2043	DstPort 1
2044	}
2045	Line {
2046	Name "Sl_rdDBus"
2047	Labels [0, 0; 0, 0]
2048	SrcBlock "plb_decode"
2049	SrcPort 8
2050	DstBlock "Sl_rdDBus"
2051	DstPort 1
2052	}
2053	Line {
2054	Name "Sl_rdDAck"
2055	Labels [0, 0; 0, 0]
2056	SrcBlock "plb_decode"
2057	SrcPort 7
2058	DstBlock "Sl_rdDAck"
2059	DstPort 1
2060	}
2061	Line {
2062	Name "Sl_rdComp"
2063	Labels [0, 0; 0, 0]
2064	SrcBlock "plb_decode"
2065	SrcPort 3
2066	DstBlock "Sl_rdComp"
2067	DstPort 1
2068	}
2069	Line {
2070	Name "addrPref"
2071	Labels [0, 0; 0, 0]
2072	SrcBlock "sg_plb_addrpref"
2073	SrcPort 1
2074	DstBlock "plb_decode"
2075	DstPort 7
2076	}
2077	Line {
2078	Name "PLB_wrDBus"
2079	Labels [0, 0; 0, 0]
2080	SrcBlock "PLB_wrDBus"
2081	SrcPort 1
2082	DstBlock "plb_decode"
2083	DstPort 5
2084	}
2085	Line {
2086	Name "PLB_RNW"
2087	Labels [0, 0; 0, 0]
2088	SrcBlock "PLB_RNW"
2089	SrcPort 1
2090	DstBlock "plb_decode"
2091	DstPort 4
2092	}
2093	Line {
2094	Name "PLB_PAValid"
2095	Labels [0, 0; 0, 0]
2096	SrcBlock "PLB_PAValid"
2097	SrcPort 1
2098	DstBlock "plb_decode"
2099	DstPort 3
2100	}
2101	Line {
2102	Name "PLB_ABus"
2103	Labels [0, 0; 0, 0]
2104	SrcBlock "PLB_ABus"
2105	SrcPort 1
2106	DstBlock "plb_decode"
2107	DstPort 2
2108	}
2109	Line {
2110	Name "SPLB_Rst"
2111	Labels [0, 0; 0, 0]
2112	SrcBlock "SPLB_Rst"
2113	SrcPort 1
2114	DstBlock "plb_decode"
2115	DstPort 1
2116	}
2117	Line {
2118	SrcBlock "Constant6"
2119	SrcPort 1
2120	DstBlock "sg_plb_addrpref"
2121	DstPort 1
2122	}
2123	Line {
2124	Name "Sl_wait"
2125	Labels [0, 0; 0, 0]
2126	SrcBlock "Constant5"
2127	SrcPort 1
2128	DstBlock "Sl_wait"
2129	DstPort 1
2130	}
2131	Line {
2132	SrcBlock "Constant4"
2133	SrcPort 1
2134	DstBlock "PLB_wrDBus"
2135	DstPort 1
2136	}
2137	Line {
2138	SrcBlock "Constant3"
2139	SrcPort 1
2140	DstBlock "PLB_RNW"
2141	DstPort 1
2142	}
2143	Line {
2144	SrcBlock "Constant2"
2145	SrcPort 1
2146	DstBlock "PLB_PAValid"
2147	DstPort 1
2148	}
2149	Line {
2150	SrcBlock "Constant1"
2151	SrcPort 1
2152	DstBlock "PLB_ABus"
2153	DstPort 1
2154	}
2155	Line {
2156	SrcBlock "Constant"
2157	SrcPort 1
2158	DstBlock "SPLB_Rst"
2159	DstPort 1
2160	}
2161	Line {
2162	SrcBlock "Sl_wrComp"
2163	SrcPort 1
2164	DstBlock "Terminator6"
2165	DstPort 1
2166	}
2167	Line {
2168	SrcBlock "Sl_wrDAck"
2169	SrcPort 1
2170	DstBlock "Terminator5"
2171	DstPort 1
2172	}
2173	Line {
2174	SrcBlock "Sl_wait"
2175	SrcPort 1
2176	DstBlock "Terminator4"
2177	DstPort 1
2178	}
2179	Line {
2180	SrcBlock "Sl_rdDBus"
2181	SrcPort 1
2182	DstBlock "Terminator3"
2183	DstPort 1
2184	}
2185	Line {
2186	SrcBlock "Sl_rdDAck"
2187	SrcPort 1
2188	DstBlock "Terminator2"
2189	DstPort 1
2190	}
2191	Line {
2192	SrcBlock "Sl_rdComp"
2193	SrcPort 1
2194	DstBlock "Terminator1"
2195	DstPort 1
2196	}
2197	Line {
2198	SrcBlock "Sl_addrAck"
2199	SrcPort 1
2200	DstBlock "Terminator"
2201	DstPort 1
2202	}
2203	}
2204	}
2205	Block {
2206	BlockType Reference
2207	Name "From Register"
2208	SID "10"
2209	Ports [0, 1]
2210	Position [175, 322, 235, 378]
2211	AttributesFormatString "<< %<shared_memory_name> >>"
2212	LibraryVersion "1.2"
2213	SourceBlock "xbsIndex_r4/From Register"
2214	SourceType "Xilinx Shared Memory Based From Register Block"
2215	infoedit "Register block that reads data to a shared memory register. Delay of one sample period."
2216	shared_memory_name "'capturePeriod'"
2217	init "0"
2218	period "1"
2219	ownership "Locally owned and initialized"
2220	gui_display_data_type "Fixed-point"
2221	arith_type "Unsigned"
2222	n_bits "32"
2223	bin_pt "0"
2224	preci_type "Single"
2225	dbl_ovrd off
2226	xl_use_area off
2227	xl_area "[0,0,0,0,0,0,0]"
2228	has_advanced_control "0"
2229	sggui_pos "-1,-1,-1,-1"
2230	block_type "fromreg"
2231	sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]"
2232	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0."
2233	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 "
2234	"36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 3"
2235	"6.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1"
2236	" ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 "
2237	"0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po"
2238	"rt_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');"
2239	}
2240	Block {
2241	BlockType Reference
2242	Name "Inverter"
2243	SID "31"
2244	Ports [1, 1]
2245	Position [305, 251, 360, 309]
2246	LibraryVersion "1.2"
2247	SourceBlock "xbsIndex_r4/Inverter"
2248	SourceType "Xilinx Inverter Block"
2249	infoedit "Bitwise logical negation (one's complement) operator."
2250	en off
2251	latency "0"
2252	dbl_ovrd off
2253	xl_use_area off
2254	xl_area "[0,0,0,0,0,0,0]"
2255	has_advanced_control "0"
2256	sggui_pos "-1,-1,-1,-1"
2257	block_type "inv"
2258	sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]"
2259	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0."
2260	"82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],["
2261	"36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.77 2"
2262	"9.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.77 29"
2263	".77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.77 22."
2264	"77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te"
2265	"xt');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');"
2266	}
2267	Block {
2268	BlockType Reference
2269	Name "LFSR"
2270	SID "2"
2271	Ports [0, 1]
2272	Position [175, 170, 235, 230]
2273	LibraryVersion "1.2"
2274	SourceBlock "xbsIndex_r4/LFSR"
2275	SourceType "Xilinx Linear Feedback Shift Register Block"
2276	lfsr_type "Fibonacci"
2277	gate_type "XOR"
2278	n_bits "16"
2279	polynomial "'B401'"
2280	rst_value "'6C'"
2281	rst off
2282	en off
2283	reloadable_seed off
2284	input_type off
2285	output_type on
2286	arith_type "Unsigned"
2287	bin_pt "0"
2288	dbl_ovrd off
2289	explicit_period off
2290	period "1"
2291	xl_use_area off
2292	xl_area "[0,0,0,0,0,0,0]"
2293	has_advanced_control "0"
2294	sggui_pos "-1,-1,-1,-1"
2295	block_type "lfsr"
2296	sg_icon_stat "60,60,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]"
2297	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0."
2298	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 "
2299	"38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 3"
2300	"8.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1"
2301	" ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 "
2302	"0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po"
2303	"rt_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');"
2304	}
2305	Block {
2306	BlockType Reference
2307	Name "Logical"
2308	SID "35"
2309	Ports [2, 1]
2310	Position [550, 265, 605, 325]
2311	LibraryVersion "1.2"
2312	SourceBlock "xbsIndex_r4/Logical"
2313	SourceType "Xilinx Logical Block Block"
2314	logical_function "AND"
2315	inputs "2"
2316	en off
2317	latency "0"
2318	precision "Full"
2319	arith_type "Unsigned"
2320	n_bits "16"
2321	bin_pt "0"
2322	align_bp on
2323	dbl_ovrd off
2324	xl_use_area off
2325	xl_area "[0,0,0,0,0,0,0]"
2326	has_advanced_control "0"
2327	sggui_pos "-1,-1,-1,-1"
2328	block_type "logical"
2329	sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]"
2330	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0."
2331	"82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],["
2332	"37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 3"
2333	"0.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30"
2334	".77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23."
2335	"77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te"
2336	"xt');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');"
2337	}
2338	Block {
2339	BlockType Reference
2340	Name "Register"
2341	SID "27"
2342	Ports [2, 1]
2343	Position [670, 187, 730, 243]
2344	LibraryVersion "1.2"
2345	SourceBlock "xbsIndex_r4/Register"
2346	SourceType "Xilinx Register Block"
2347	init "0"
2348	rst off
2349	en on
2350	dbl_ovrd off
2351	xl_use_area off
2352	xl_area "[0,0,0,0,0,0,0]"
2353	has_advanced_control "0"
2354	sggui_pos "-1,-1,-1,-1"
2355	block_type "register"
2356	sg_icon_stat "60,56,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]"
2357	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0."
2358	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 "
2359	"36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 3"
2360	"6.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1"
2361	" ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 "
2362	"0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po"
2363	"rt_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');"
2364	"\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');"
2365	}
2366	Block {
2367	BlockType Reference
2368	Name "Relational"
2369	SID "9"
2370	Ports [2, 1]
2371	Position [425, 372, 480, 428]
2372	LibraryVersion "1.2"
2373	SourceBlock "xbsIndex_r4/Relational"
2374	SourceType "Xilinx Arithmetic Relational Operator Block"
2375	mode "a=b"
2376	en off
2377	latency "0"
2378	dbl_ovrd off
2379	xl_use_area off
2380	xl_area "[0,0,0,0,0,0,0]"
2381	has_advanced_control "0"
2382	sggui_pos "-1,-1,-1,-1"
2383	block_type "relational"
2384	sg_icon_stat "55,56,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]"
2385	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0."
2386	"82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],["
2387	"35.77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 2"
2388	"8.77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28"
2389	".77 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21."
2390	"77 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te"
2391	"xt');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port"
2392	"_label('output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');"
2393	}
2394	Block {
2395	BlockType Scope
2396	Name "Scope"
2397	SID "26"
2398	Ports [4]
2399	Position [1130, 191, 1215, 389]
2400	Floating off
2401	Location [41, 52, 714, 624]
2402	Open on
2403	NumInputPorts "4"
2404	ZoomMode "xonly"
2405	List {
2406	ListType AxesTitles
2407	axes1 "%<SignalLabel>"
2408	axes2 "%<SignalLabel>"
2409	axes3 "%<SignalLabel>"
2410	axes4 "%<SignalLabel>"
2411	}
2412	YMin "-5~-5~-5~-5"
2413	YMax "5~5~5~5"
2414	DataFormat "StructureWithTime"
2415	SampleTime "0"
2416	}
2417	Block {
2418	BlockType Reference
2419	Name "Slice"
2420	SID "13"
2421	Ports [1, 1]
2422	Position [875, 200, 935, 230]
2423	LibraryVersion "1.2"
2424	SourceBlock "xbsIndex_r4/Slice"
2425	SourceType "Xilinx Bit Slice Extractor Block"
2426	infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outpu"
2427	"t type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><"
2428	"br>Hardware notes: In hardware this block costs nothing."
2429	nbits "7"
2430	boolean_output off
2431	mode "Upper Bit Location + Width"
2432	bit1 "0"
2433	base1 "MSB of Input"
2434	bit0 "0"
2435	base0 "LSB of Input"
2436	dbl_ovrd off
2437	has_advanced_control "0"
2438	sggui_pos "-1,-1,-1,-1"
2439	block_type "slice"
2440	sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
2441	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0."
2442	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.44 "
2443	"19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.44 1"
2444	"9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1"
2445	" ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.97"
2446	"3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port"
2447	"_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
2448	}
2449	Block {
2450	BlockType Reference
2451	Name "Slice1"
2452	SID "20"
2453	Ports [1, 1]
2454	Position [875, 250, 935, 280]
2455	LibraryVersion "1.2"
2456	SourceBlock "xbsIndex_r4/Slice"
2457	SourceType "Xilinx Bit Slice Extractor Block"
2458	infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outpu"
2459	"t type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><"
2460	"br>Hardware notes: In hardware this block costs nothing."
2461	nbits "7"
2462	boolean_output off
2463	mode "Lower Bit Location + Width"
2464	bit1 "0"
2465	base1 "MSB of Input"
2466	bit0 "0"
2467	base0 "LSB of Input"
2468	dbl_ovrd off
2469	has_advanced_control "0"
2470	sggui_pos "-1,-1,-1,-1"
2471	block_type "slice"
2472	sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
2473	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0."
2474	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.44 "
2475	"19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.44 1"
2476	"9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1"
2477	" ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.97"
2478	"3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port"
2479	"_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
2480	}
2481	Block {
2482	BlockType Reference
2483	Name "Slice2"
2484	SID "22"
2485	Ports [1, 1]
2486	Position [875, 300, 935, 330]
2487	LibraryVersion "1.2"
2488	SourceBlock "xbsIndex_r4/Slice"
2489	SourceType "Xilinx Bit Slice Extractor Block"
2490	infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outpu"
2491	"t type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><"
2492	"br>Hardware notes: In hardware this block costs nothing."
2493	nbits "4"
2494	boolean_output off
2495	mode "Upper Bit Location + Width"
2496	bit1 "0"
2497	base1 "MSB of Input"
2498	bit0 "0"
2499	base0 "LSB of Input"
2500	dbl_ovrd off
2501	has_advanced_control "0"
2502	sggui_pos "-1,-1,-1,-1"
2503	block_type "slice"
2504	sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
2505	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0."
2506	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.44 "
2507	"19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.44 1"
2508	"9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1"
2509	" ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.97"
2510	"3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port"
2511	"_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
2512	}
2513	Block {
2514	BlockType Reference
2515	Name "Slice3"
2516	SID "24"
2517	Ports [1, 1]
2518	Position [875, 350, 935, 380]
2519	LibraryVersion "1.2"
2520	SourceBlock "xbsIndex_r4/Slice"
2521	SourceType "Xilinx Bit Slice Extractor Block"
2522	infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outpu"
2523	"t type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><"
2524	"br>Hardware notes: In hardware this block costs nothing."
2525	nbits "4"
2526	boolean_output off
2527	mode "Lower Bit Location + Width"
2528	bit1 "0"
2529	base1 "MSB of Input"
2530	bit0 "0"
2531	base0 "LSB of Input"
2532	dbl_ovrd off
2533	has_advanced_control "0"
2534	sggui_pos "-1,-1,-1,-1"
2535	block_type "slice"
2536	sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
2537	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0."
2538	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.44 "
2539	"19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.44 1"
2540	"9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1"
2541	" ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.97"
2542	"3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port"
2543	"_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
2544	}
2545	Block {
2546	BlockType Reference
2547	Name "To Register"
2548	SID "28"
2549	Ports [2, 1]
2550	Position [875, 417, 935, 473]
2551	AttributesFormatString "<< %<shared_memory_name> >>"
2552	LibraryVersion "1.2"
2553	SourceBlock "xbsIndex_r4/To Register"
2554	SourceType "Xilinx Shared Memory Based To Register Block"
2555	infoedit "Register block that writes data to a shared memory register. Delay of one sample period."
2556	shared_memory_name "'capturedOutput'"
2557	init "0"
2558	ownership "Locally owned and initialized"
2559	explicit_data_type on
2560	gui_display_data_type "Fixed-point"
2561	arith_type "Unsigned"
2562	n_bits "16"
2563	bin_pt "0"
2564	preci_type "Single"
2565	dbl_ovrd off
2566	xl_use_area off
2567	xl_area "[0,0,0,0,0,0,0]"
2568	has_advanced_control "0"
2569	sggui_pos "-1,-1,-1,-1"
2570	block_type "toreg"
2571	sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]"
2572	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0."
2573	"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 "
2574	"36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 3"
2575	"6.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1"
2576	" ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 "
2577	"0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po"
2578	"rt_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'do"
2579	"ut');\nfprintf('','COMMENT: end icon text');"
2580	}
2581	Block {
2582	BlockType Reference
2583	Name "hexdisp_left"
2584	SID "3"
2585	Ports [1, 1]
2586	Position [1000, 205, 1060, 225]
2587	LibraryVersion "1.2"
2588	SourceBlock "xbsIndex_r4/Gateway Out"
2589	SourceType "Xilinx Gateway Out Block"
2590	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
2591	"pe Simulink integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top"
2592	" level output ports or are discarded, depending on how they are configured."
2593	inherit_from_input off
2594	hdl_port on
2595	timing_constraint "None"
2596	locs_specified off
2597	LOCs "{}"
2598	xl_use_area off
2599	xl_area "[0,0,0,0,0,0,0]"
2600	UseAsDAC off
2601	DACChannel "'1'"
2602	has_advanced_control "0"
2603	sggui_pos "-1,-1,-1,-1"
2604	block_type "gatewayout"
2605	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
2606	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
2607	"93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
2608	"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
2609	"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
2610	"[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
2611	"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
2612	"port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
2613	"printf('','COMMENT: end icon text');"
2614	Port {
2615	PortNumber 1
2616	Name "Left Hex"
2617	RTWStorageClass "Auto"
2618	DataLoggingNameMode "SignalName"
2619	}
2620	}
2621	Block {
2622	BlockType Reference
2623	Name "hexdisp_right"
2624	SID "21"
2625	Ports [1, 1]
2626	Position [1000, 255, 1060, 275]
2627	LibraryVersion "1.2"
2628	SourceBlock "xbsIndex_r4/Gateway Out"
2629	SourceType "Xilinx Gateway Out Block"
2630	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
2631	"pe Simulink integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top"
2632	" level output ports or are discarded, depending on how they are configured."
2633	inherit_from_input off
2634	hdl_port on
2635	timing_constraint "None"
2636	locs_specified off
2637	LOCs "{}"
2638	xl_use_area off
2639	xl_area "[0,0,0,0,0,0,0]"
2640	UseAsDAC off
2641	DACChannel "'1'"
2642	has_advanced_control "0"
2643	sggui_pos "-1,-1,-1,-1"
2644	block_type "gatewayout"
2645	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
2646	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
2647	"93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
2648	"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
2649	"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
2650	"[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
2651	"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
2652	"port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
2653	"printf('','COMMENT: end icon text');"
2654	Port {
2655	PortNumber 1
2656	Name "Right Hex"
2657	RTWStorageClass "Auto"
2658	DataLoggingNameMode "SignalName"
2659	}
2660	}
2661	Block {
2662	BlockType Reference
2663	Name "leds_green"
2664	SID "25"
2665	Ports [1, 1]
2666	Position [1000, 355, 1060, 375]
2667	LibraryVersion "1.2"
2668	SourceBlock "xbsIndex_r4/Gateway Out"
2669	SourceType "Xilinx Gateway Out Block"
2670	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
2671	"pe Simulink integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top"
2672	" level output ports or are discarded, depending on how they are configured."
2673	inherit_from_input off
2674	hdl_port on
2675	timing_constraint "None"
2676	locs_specified off
2677	LOCs "{}"
2678	xl_use_area off
2679	xl_area "[0,0,0,0,0,0,0]"
2680	UseAsDAC off
2681	DACChannel "'1'"
2682	has_advanced_control "0"
2683	sggui_pos "-1,-1,-1,-1"
2684	block_type "gatewayout"
2685	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
2686	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
2687	"93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
2688	"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
2689	"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
2690	"[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
2691	"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
2692	"port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
2693	"printf('','COMMENT: end icon text');"
2694	Port {
2695	PortNumber 1
2696	Name "Green LEDs"
2697	RTWStorageClass "Auto"
2698	DataLoggingNameMode "SignalName"
2699	}
2700	}
2701	Block {
2702	BlockType Reference
2703	Name "leds_red"
2704	SID "23"
2705	Ports [1, 1]
2706	Position [1000, 305, 1060, 325]
2707	LibraryVersion "1.2"
2708	SourceBlock "xbsIndex_r4/Gateway Out"
2709	SourceType "Xilinx Gateway Out Block"
2710	infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
2711	"pe Simulink integer, single, double, or fixed point.<br><br>Hardware notes: In hardware these blocks become top"
2712	" level output ports or are discarded, depending on how they are configured."
2713	inherit_from_input off
2714	hdl_port on
2715	timing_constraint "None"
2716	locs_specified off
2717	LOCs "{}"
2718	xl_use_area off
2719	xl_area "[0,0,0,0,0,0,0]"
2720	UseAsDAC off
2721	DACChannel "'1'"
2722	has_advanced_control "0"
2723	sggui_pos "-1,-1,-1,-1"
2724	block_type "gatewayout"
2725	sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
2726	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
2727	"93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
2728	"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
2729	"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
2730	"[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
2731	"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
2732	"port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
2733	"printf('','COMMENT: end icon text');"
2734	Port {
2735	PortNumber 1
2736	Name "Red LEDs"
2737	RTWStorageClass "Auto"
2738	DataLoggingNameMode "SignalName"
2739	}
2740	}
2741	Block {
2742	BlockType Reference
2743	Name "pause"
2744	SID "32"
2745	Ports [1, 1]
2746	Position [175, 270, 240, 290]
2747	LibraryVersion "1.2"
2748	SourceBlock "xbsIndex_r4/Gateway In"
2749	SourceType "Xilinx Gateway In Block"
2750	infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to "
2751	" Xilinx fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top lev"
2752	"el input ports."
2753	gui_display_data_type "Boolean"
2754	arith_type "Boolean"
2755	n_bits "16"
2756	bin_pt "14"
2757	preci_type "Single"
2758	exp_width "8"
2759	frac_width "24"
2760	quantization "Round (unbiased: +/- Inf)"
2761	overflow "Saturate"
2762	period "1"
2763	dbl_ovrd off
2764	timing_constraint "None"
2765	locs_specified off
2766	LOCs "{}"
2767	xl_use_area off
2768	xl_area "[0,0,0,0,0,0,0]"
2769	inherit_from_input off
2770	UseAsADC off
2771	ADCChannel "'1'"
2772	hdl_port "on"
2773	has_advanced_control "0"
2774	sggui_pos "-1,-1,-1,-1"
2775	block_type "gatewayin"
2776	sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
2777	sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0."
2778	"93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12."
2779	"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 1"
2780	"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
2781	"[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
2782	"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
2783	"port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfp"
2784	"rintf('','COMMENT: end icon text');"
2785	}
2786	Line {
2787	SrcBlock "Register"
2788	SrcPort 1
2789	Points [70, 0]
2790	Branch {
2791	DstBlock "Slice"
2792	DstPort 1
2793	}
2794	Branch {
2795	Points [0, 50]
2796	Branch {
2797	DstBlock "Slice1"
2798	DstPort 1
2799	}
2800	Branch {
2801	Points [0, 50]
2802	Branch {
2803	DstBlock "Slice2"
2804	DstPort 1
2805	}
2806	Branch {
2807	Points [0, 50]
2808	Branch {
2809	DstBlock "Slice3"
2810	DstPort 1
2811	}
2812	Branch {
2813	Points [0, 65]
2814	DstBlock "To Register"
2815	DstPort 1
2816	}
2817	}
2818	}
2819	}
2820	}
2821	Line {
2822	SrcBlock "Counter"
2823	SrcPort 1
2824	Points [0, -30]
2825	DstBlock "Relational"
2826	DstPort 2
2827	}
2828	Line {
2829	SrcBlock "From Register"
2830	SrcPort 1
2831	Points [140, 0; 0, 35]
2832	DstBlock "Relational"
2833	DstPort 1
2834	}
2835	Line {
2836	SrcBlock "Relational"
2837	SrcPort 1
2838	Points [25, 0]
2839	Branch {
2840	Points [0, 95; -220, 0]
2841	DstBlock "Counter"
2842	DstPort 1
2843	}
2844	Branch {
2845	Points [0, -90]
2846	DstBlock "Logical"
2847	DstPort 2
2848	}
2849	}
2850	Line {
2851	SrcBlock "Slice"
2852	SrcPort 1
2853	DstBlock "hexdisp_left"
2854	DstPort 1
2855	}
2856	Line {
2857	SrcBlock "Slice1"
2858	SrcPort 1
2859	DstBlock "hexdisp_right"
2860	DstPort 1
2861	}
2862	Line {
2863	SrcBlock "Slice2"
2864	SrcPort 1
2865	DstBlock "leds_red"
2866	DstPort 1
2867	}
2868	Line {
2869	SrcBlock "Slice3"
2870	SrcPort 1
2871	DstBlock "leds_green"
2872	DstPort 1
2873	}
2874	Line {
2875	Name "Left Hex"
2876	Labels [0, 0]
2877	SrcBlock "hexdisp_left"
2878	SrcPort 1
2879	DstBlock "Scope"
2880	DstPort 1
2881	}
2882	Line {
2883	Name "Right Hex"
2884	Labels [0, 0]
2885	SrcBlock "hexdisp_right"
2886	SrcPort 1
2887	DstBlock "Scope"
2888	DstPort 2
2889	}
2890	Line {
2891	Name "Red LEDs"
2892	Labels [0, 0]
2893	SrcBlock "leds_red"
2894	SrcPort 1
2895	DstBlock "Scope"
2896	DstPort 3
2897	}
2898	Line {
2899	Name "Green LEDs"
2900	Labels [0, 0]
2901	SrcBlock "leds_green"
2902	SrcPort 1
2903	DstBlock "Scope"
2904	DstPort 4
2905	}
2906	Line {
2907	SrcBlock "LFSR"
2908	SrcPort 1
2909	DstBlock "Register"
2910	DstPort 1
2911	}
2912	Line {
2913	SrcBlock "Constant"
2914	SrcPort 1
2915	DstBlock "To Register"
2916	DstPort 2
2917	}
2918	Line {
2919	SrcBlock "pause"
2920	SrcPort 1
2921	DstBlock "Inverter"
2922	DstPort 1
2923	}
2924	Line {
2925	SrcBlock "Constant1"
2926	SrcPort 1
2927	DstBlock "pause"
2928	DstPort 1
2929	}
2930	Line {
2931	SrcBlock "Inverter"
2932	SrcPort 1
2933	DstBlock "Logical"
2934	DstPort 1
2935	}
2936	Line {
2937	SrcBlock "Logical"
2938	SrcPort 1
2939	Points [15, 0; 0, -65]
2940	DstBlock "Register"
2941	DstPort 2
2942	}
2943	Annotation {
2944	Name "'capturePeriod' Register:\n(assuming 80MHz bus)\n\ndisplay update rate = \n80e6/(speed+1)"
2945	Position [155, 440]
2946	HorizontalAlignment "left"
2947	}
2948	Annotation {
2949	Name "This core uses a linear feedback shift register to drive pseudorandom numbers\nto the w3_userio cor"
2950	"e. Because this core will run at whatever speed the bus is\n(likely 80MHz), a small piece of logic is included t"
2951	"o latch the outputs of the LFSR\nto make the changes viewable to the naked eye when looking at the board. This\n"
2952	"system is controlled by a register called 'speed' that can be written by C-code in\nthe Xilinx SDK.\n\nThis core"
2953	" is not intended to be a proper source of randomness for designs. It\nis only for the purposes of exercising the"
2954	" WARP hardware with User I/O with\ninteresting outputs."
2955	Position [175, 95]
2956	HorizontalAlignment "left"
2957	}
2958	}
2959	}
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2961	NumRecords 1
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3057	" @ $ 4 ( 0 < ! ! ' =FER=&5X-@ . 0 8 ( ! % \" "
3058	" $ * 0 0 \"@ 'AC-G9L>#(T,'0 . , 8 ( ! % \" $ \" 0 "
3059	" 0 ( +3( X X !@ @ $ 4 ( 0 8 ! ! & 9F8Q,34V . , "
3060	" 8 ( ! % \" 0 0 X P !@ @ $ 4 ( 0 "
3061	", ! ! P!84U0 #@ # & \" 0 !0 @ $ $ . 0 8"
3062	" ( ! % \" $ - 0 0 #0 $-L;V-K($5N86)L97, . 0 8 ( ! "
3063	" % \" $ ) 0 0 \"0 \"XO;F5T;&ES= . , 8 ( ! % \" "
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3067	" % \" 0 0 X ! !@ @ $ 4 ( 0 P ! ! "
3068	" , 25-%($1E9F%U;'1S X P !@ @ $ 4 ( ! ! #@ # "
3069	"& \" 0 !0 @ ! P $ $ # &]F9@ . , 8 ( ! % \" $ "
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3071	" \" 0 !0 @ $ $ . , 8 ( ! % \" "
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3086	"+C S,3,W,C4@,\"XR,3DV,#@@72D[\"G!A=&-H*%LQ+C8S-S4@,38N.#$@,C<N,S$@,3(N,3,W-2 Q+C8S-S4@72Q;,34N-C4U(#$U+C8U-2 R-BXQ"
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3141	" <V=G=6E?<&]S 8FQO8VM?='EP90 8FQO8VM?=F5R<VEO;@ "
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3145	":6QE 8V5?8VQR <')E<V5R=F5?:&EE<F%R8VAY #@"
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3212	"&5S #@ $ & \" 0 !0 @ ! \"0 $ $ D N+VYE=&QI<W0 #@ # "
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3228	"#@ & \" 0 !0 @ ! !@ $ $ 8 !S>7-G96X X P !@ @ $ "
3229	"4 ( ! ! #@ & & \" 0 !0 @ ! +@ $ $ \""
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3234	",Y,C(@,\"XQ-#$Q-S8@72D[\"G!A=&-H*%LQ,BXQ,S<U(#(W+C,Q(#$V+C@Q(#$N-C,W-2 Q,BXQ,S<U(%TL6S(V+C$U-2 R-BXQ-34@,S8N-C4U(#"
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3238	"34N-C4U(#4N,34U(%TL6S N-CDX,#,Y(# N,#,Q,S<R-2 P+C(Q.38P.\"!=3L9G!R:6YT9B@G)RPG0T]-345.5#H@96YD(&EC;VX@9W)A<&AI8W"
3239	",G3L9G!R:6YT9B@G)RPG0T]-345.5#H@8F5G:6X@:6-O;B!T97AT)RD[\"F9P<FEN=&8H)R<L)T-/34U%3E0Z(&5N9\"!I8V]N('1E>'0G*3L #@"
3240	" # & \" 0 !0 @ $ $ . , 8 ( ! % \" "
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3243	" $ $ 0 0 0 5DA$3 X ! !@ @ $ 4 ( 0 T ! ! - 6%-4($"
3244	"1E9F%U;'1S@ X ! !@ @ $ 4 ( 0 T ! ! - 25-%($1E9F%U;'1S@ X "
3245	" X !@ @ & 4 ( 0 $ ! D ( . . 8 ( !@ "
3246	" % \" $ ! 0 ) \" #@ #@ & \" 0 !0 @ ! !@ $ "
3247	" $ 8 Y+C(N,#$ X ! !@ @ $ 4 ( 0 T ! ! - >&QE9&MS971"
3248	"T:6YG<P X ! !@ @ $ 4 ( 0 \\ ! ! / >&QE9&MP<F5C;VUP:6QE X ! "
3249	" !@ @ $ 4 ( 0 T ! ! - >&QE9&MU<&1A=&5F;@ X \"8! !@ @ \""
3250	" 4 ( 0 $ ! 4 ! 8 0 #@! !E>'!O<G0 !E>'!O<G1D:7( "
3251	" !S96QE8W1I;VYT86< !E>'!O<G1D:7)P871H !M86IO<@ !M:6YO"
3252	"<@ !H=U]C;VUP871I8FEL:71Y !M86I?<VQI9&5R !M:6YO<E]S;&ED97( "
3253	" !H=U]C;VUP871I8FEL:71Y7W-L:61E<@!I<T1E=F5L;W!M96YT !U<V5#=7-T;VU\"=7-);G1E<F9A8V4 !C=7-T;VU"
3254	"\"=7-);G1E<F9A8V5686QU90 . . 8 ( !@ % \" $ ! 0 ) \" #@"
3255	" # & \" 0 !0 @ $ $ . 0 8 ( ! % \" "
3256	" $ 0 0 0 $ '1A<F=E=%]D:7)E8W1O<GD. , 8 ( ! % \" 0 "
3257	" 0 X X !@ @ & 4 ( 0 $ ! D ( \\#\\. . "
3258	" 8 ( !@ % \" $ ! 0 ) \" ! #@ # & \" 0 !0"
3259	" @ ! 0 $ $ ! &$ . . 8 ( !@ % \" $ ! 0 ) \" "
3260	" / _#@ #@ & \" 8 !0 @ ! 0 $ \"0 @ ##]2A<C\\('0 X X !"
3261	"@ @ & 4 ( 0 $ ! D ( ! 6$ . . 8 ( !@ % \" "
3262	" $ ! 0 ) \" / _#@ #@ & \" 8 !0 @ ! 0 $ \""
3263	"0 @ X P !@ @ & 4 ( ! D "
3264	}
3265	}

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