| 1 | #FPGA Board v2.2 I/O constraints for Other I/O Devices |
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| 2 | # |
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| 3 | #16-bits of Digital I/O at 20-pin 0.1" header (component J20) |
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| 4 | # 4 corner pins of 20-pin header are ground |
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| 5 | # Bit 0 is pin 0, as labeled on the board |
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| 6 | Net DIGITAL_IO<0> LOC = L20 | IOSTANDARD = LVTTL; |
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| 7 | Net DIGITAL_IO<1> LOC = J21 | IOSTANDARD = LVTTL; |
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| 8 | Net DIGITAL_IO<2> LOC = G20 | IOSTANDARD = LVTTL; |
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| 9 | Net DIGITAL_IO<3> LOC = J20 | IOSTANDARD = LVTTL; |
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| 10 | Net DIGITAL_IO<4> LOC = K21 | IOSTANDARD = LVTTL; |
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| 11 | Net DIGITAL_IO<5> LOC = F20 | IOSTANDARD = LVTTL; |
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| 12 | Net DIGITAL_IO<6> LOC = H20 | IOSTANDARD = LVTTL; |
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| 13 | Net DIGITAL_IO<7> LOC = L21 | IOSTANDARD = LVTTL; |
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| 14 | Net DIGITAL_IO<8> LOC = H18 | IOSTANDARD = LVTTL; |
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| 15 | Net DIGITAL_IO<9> LOC = H19 | IOSTANDARD = LVTTL; |
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| 16 | Net DIGITAL_IO<10> LOC = K19 | IOSTANDARD = LVTTL; |
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| 17 | Net DIGITAL_IO<11> LOC = G18 | IOSTANDARD = LVTTL; |
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| 18 | Net DIGITAL_IO<12> LOC = F19 | IOSTANDARD = LVTTL; |
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| 19 | Net DIGITAL_IO<13> LOC = L19 | IOSTANDARD = LVTTL; |
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| 20 | Net DIGITAL_IO<14> LOC = J19 | IOSTANDARD = LVTTL; |
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| 21 | Net DIGITAL_IO<15> LOC = F18 | IOSTANDARD = LVTTL; |
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| 22 | # |
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| 23 | #RS-232 UART Interface (DB9 connector J50) |
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| 24 | # Rx is FPGA input, Tx is FPGA output |
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| 25 | Net UART_DB9_RX LOC = L24 | IOSTANDARD = LVCMOS25; |
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| 26 | Net UART_DB9_TX LOC = K24 | IOSTANDARD = LVCMOS25; |
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| 27 | # |
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| 28 | #USB-UART Interface (USB connector J58) |
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| 29 | # Rx is FPGA input, Tx is FPGA output |
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| 30 | Net UART_USB_RX LOC = C23 | IOSTANDARD = LVTTL; |
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| 31 | Net UART_USB_TX LOC = AA23 | IOSTANDARD = LVTTL; |
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