| 1 | #FPGA Board v2.2 I/O constraints for User I/O Devices |
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| 2 | # |
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| 3 | # 8 LEDs directly controlled using the FPGA I/O pins (D10, D11, D13, |
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| 4 | # D14, D18, D19, D20, D21) |
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| 5 | NET LED<0> LOC = N24 | IOSTANDARD = LVCMOS25; #RED D11 |
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| 6 | NET LED<1> LOC = N20 | IOSTANDARD = LVCMOS25; #RED D14 |
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| 7 | NET LED<2> LOC = L18 | IOSTANDARD = LVCMOS25; #RED D19 |
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| 8 | NET LED<3> LOC = N18 | IOSTANDARD = LVCMOS25; #RED D21 |
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| 9 | NET LED<4> LOC = M18 | IOSTANDARD = LVCMOS25; #GREEN D10 |
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| 10 | NET LED<5> LOC = M25 | IOSTANDARD = LVCMOS25; #GREEN D13 |
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| 11 | NET LED<6> LOC = N19 | IOSTANDARD = LVCMOS25; #GREEN D18 |
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| 12 | NET LED<7> LOC = P19 | IOSTANDARD = LVCMOS25; #GREEN D20 |
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| 13 | # |
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| 14 | # 5 pushbuttons arranged a cross orientation. |
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| 15 | NET PUSHB_CENTER LOC = L23 | IOSTANDARD = LVCMOS25; |
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| 16 | NET PUSHB_DOWN LOC = M21 | IOSTANDARD = LVCMOS25; |
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| 17 | NET PUSHB_LEFT LOC = N22 | IOSTANDARD = LVCMOS25; |
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| 18 | NET PUSHB_RIGHT LOC = M23 | IOSTANDARD = LVCMOS25; |
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| 19 | NET PUSHB_UP LOC = N23 | IOSTANDARD = LVCMOS25; |
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| 20 | # |
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| 21 | # 4-bit DIP Switch (SW5) |
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| 22 | NET DIPSW<0> LOC = M17 | IOSTANDARD = LVCMOS25; |
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| 23 | NET DIPSW<1> LOC = R18 | IOSTANDARD = LVCMOS25; |
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| 24 | NET DIPSW<2> LOC = P17 | IOSTANDARD = LVCMOS25; |
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| 25 | NET DIPSW<3> LOC = M16 | IOSTANDARD = LVCMOS25; |
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| 26 | # |
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| 27 | # 2 IO Expanders that control the three hex displays (D30, D31, D32) and |
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| 28 | # and 8 additional LEDs (D16, D17, D33, D34, D35, D36, D37, D38) |
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| 29 | NET HEX_SDA LOC = AL18 | IOSTANDARD = LVCMOS33; |
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| 30 | NET HEX_SCL LOC = AK17 | IOSTANDARD = LVCMOS33; |
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