The WARP v3 configuration CPLD code implements two functions:
 * SPI flash configuration: The CPLD passes through the signals for the Virtex-6
	"Master SPI" configuration mode, connecting them to the 128Mb SPI flash chip.
 * SD card configuration: The CPLD implmenets an SPI master for reading .bin files from
	the SD card and writing the configuration data to the Vitex-6 via "Slave Serial" mode

The code for the SD card configuration mode is based on the SPI Boot project at Open Cores
(http://opencores.org/project,spi_boot).  The original SPI boot source on which we based our design
is included in the spi_boot_OpenCores_src subdirectory of our source folder.

The source code for the WARP v3 config CPLD design is organized as:

w3_cpld_sd_config.v - top-level module
 |-spi_boot.vhd - top-level of SPI boot core
	|-spi_boot_pack-p.vhd
	|-spi_counter.vhd

Our verison of spi_boot.vhd has very minor changes realtive to the Open Cores version. Our
version includes two extra lines (diff output below) to explicitly drive the FPGA's PROG
signal high when the Virtex-6 state machine requires it.

====================================================================================================
Unified diff between original spi_boot.vhd and the verison used in the WARP v3 config CPLD design

--- /WARP/Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot.vhd	Sat Jun 23 22:44:34 2012
+++ /WARP/Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot_OpenCores_src/rtl/vhdl/spi_boot.vhd	Sat Jun 23 12:28:00 2012
@@ -582,9 +582,6 @@
       when WAIT_START =>
         spi_cs_n_s     <= '1';
 
-		--POM 2012-06-23: Adding de-assertion of PROG
-        config_n_o   <= '1';
-
         -- detect rising edge of start_i
         if start_i = '1' and start_q = '0' then
           -- decide which mode is requested
@@ -621,9 +618,6 @@
       when WAIT_INIT_HIGH =>
         spi_cs_n_s   <= '1';
 
-		--POM 2012-06-23: Adding de-assertion of PROG
-        config_n_o   <= '1';
-
         if cfg_init_n_i = '1' and cmd_finished_s then
           ctrl_fsm_s <= CMD18;
         else
====================================================================================================


Licensing:

It is unclear udner which license the Open Cores spi_boot project is distributed. The source
code includes a copy of the GPL v2, but the source file headers don't mention the GPL in thier
copyright sections (instead they include BSD-like distribution terms).

Just to be safe, we'll assume the author intended his code be distributed under the GPL v2. As such,
our full config CPLD design is likewise made available under GPL v2. The Mango-owned code (w3_cpld_sd_config.v)
is dual-licensed, also available under the standard WAPR license (http://warp.rice.edu/license).

Our adoption of the GPL v2 for the CPLD design does not extend to any designs running in the Virtex-6 FPGA.
These designs will continue to be licensed under the BSD-based WARP license (http://warp.rice.edu/license).

If you have any questions or concerns, please contact Patrick Murphy at Mango (patrick [at] mangocomm.com).