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| 2 | README for the spi_boot core |
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| 3 | ============================ |
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| 4 | Version: $Id: README 77 2009-04-01 19:53:14Z arniml $ |
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| 5 | |
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| 6 | |
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| 7 | Description |
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| 8 | ----------- |
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| 9 | |
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| 10 | The SD/MMC Bootloader is a CPLD design that manages configuration and |
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| 11 | bootstrapping of FPGAs. It is able to retrieve the required data from |
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| 12 | SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA |
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| 13 | configuration process. SD cards as well as MMCs are operated in SPI mode which |
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| 14 | is part of both standards thus eliminating the need for dedicated |
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| 15 | implementations. The SD/MMC Bootloader fits both. Beyond configuration, this |
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| 16 | core supports a bootstrapping strategy where multiple images are stored on one |
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| 17 | single memory card. |
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| 18 | For example consider a system completely based on SRAM. The bootloader |
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| 19 | provides the initial configuration data from the first image to the FPGA. This |
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| 20 | image contains a design which pulls the next image from the memory card and |
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| 21 | transfers this data to SRAM. In the third step the final FPGA design is loaded |
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| 22 | from the third image. |
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| 23 | These images are clustered in sets which can be selected by external switches |
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| 24 | for example. Several configuration sets can be stored on one memory card |
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| 25 | allowing you to provide a number of applications which are downloaded quickly |
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| 26 | to the FPGA. |
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| 27 | The schematic (rev. B) shows how the core can be used with an FPGA board. I |
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| 28 | use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300 |
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| 29 | board. SV2 fits the "SERIAL MODE" connector on this board but you will have to |
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| 30 | add a separate wire from R6 to attach INIT. Please check the proper use of the |
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| 31 | pull-up resistors for your specific board. |
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| 32 | |
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| 33 | |
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| 34 | Features |
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| 35 | -------- |
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| 36 | |
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| 37 | * Configuration mode: configures SRAM based FPGAs via slave serial mode |
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| 38 | (Xilinx and Altera) |
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| 39 | * Data mode: provides stored data over a simple synchronous serial interface |
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| 40 | * Broad compatability using SPI mode |
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| 41 | + SecureDigital cards using dedicated initialization command |
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| 42 | + MultiMediaCards (see below) |
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| 43 | * Operation triggerd by power-up or card insertion |
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| 44 | * Multiple configuration sets stored on on single memory card |
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| 45 | |
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| 46 | |
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| 47 | Compatability |
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| 48 | ------------- |
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| 49 | |
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| 50 | These cards have been tested with the SD/MMC Bootloader: |
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| 51 | |
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| 52 | * Hama 64 MB SD |
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| 53 | * SanDisk 128 MB SD |
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| 54 | * SanDisk 64 MB MMC |
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| 55 | * Panasonic 32 MB SD |
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| 56 | |
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| 57 | Some MMC might fail with this core as not all cards support CMD18 |
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| 58 | (READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific |
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| 59 | model. In case your MMC does not implement CMD18 you might want to have a look |
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| 60 | at the FPGA MMC-Card Config project. |
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| 61 | |
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| 62 | |
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| 63 | Tools |
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| 64 | ----- |
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| 65 | |
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| 66 | Downloading the configuration data to the card is a straight forward |
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| 67 | process. The images have to be written starting at dedicated locations. For |
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| 68 | the provided toplevel designs, these locations are multiples of 256 K. I.e. 0, |
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| 69 | 0x40000, 0x80000 and so forth. |
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| 70 | |
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| 71 | dd (part of the GNU coreutils) serves this purpose: |
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| 72 | $ dd if=ram_loader.bin of=/dev/sdX bs=512 |
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| 73 | $ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512 |
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| 74 | $ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024 |
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| 75 | |
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| 76 | The name of the device node depends on how the card reader is attached to the |
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| 77 | kernel. For Linux systems this is most often something like /dev/sdX with X |
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| 78 | ranging from a-z. Please note that it is essential to use the device without |
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| 79 | any trailing numbers as they refer to partitions leading to wrong offsets for |
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| 80 | data written to the card. |
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| 81 | All this works perfectly for my Spartan IIe device as this FPGA expects the |
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| 82 | configuration data as it is delivered from the card: Consecutive bytes each |
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| 83 | with its most significant bit first. Altera devices like the FLEX family are |
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| 84 | different here. They expect the bytes with least significant bit |
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| 85 | first. Therefore, the configuration data has to be swapped bitwise before it |
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| 86 | is written to the card. Michael Libeskind kindly provided a program that |
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| 87 | accimplishes this task. Find it in sw/misc/bit_reverse.c. |
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| 88 | |
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| 89 | |
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| 90 | Verification |
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| 91 | ------------ |
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| 92 | |
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| 93 | The spi_boot core comes with a simple testbench that simulates an SD/MMC |
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| 94 | card. All four implementations of the core are verified there in parallel |
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| 95 | while transferring the data for several sets. |
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| 96 | You should normally not need to run the testbench. But in case you modified |
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| 97 | the VHDL code the testbench gives some hints if the design has been broken. |
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| 98 | |
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| 99 | |
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| 100 | Directory Structure |
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| 101 | ------------------- |
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| 102 | |
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| 103 | The core's directory structure follows the proposal of OpenCores.org. |
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| 104 | |
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| 105 | spi_boot |
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| 106 | | |
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| 107 | \--+-- doc : Documentation |
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| 108 | | | |
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| 109 | | \-- src : Source files of documentation |
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| 110 | | |
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| 111 | +-- rtl |
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| 112 | | | |
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| 113 | | \-- vhdl : VHDL code containing the RTL description |
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| 114 | | of the core. |
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| 115 | | |
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| 116 | +-- bench |
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| 117 | | | |
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| 118 | | \-- vhdl : VHDL testbench code. |
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| 119 | | |
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| 120 | \-- sim |
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| 121 | | |
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| 122 | \-- rtl_sim : Directory for running simulations. |
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| 123 | |
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| 124 | |
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| 125 | RAM Loader |
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| 126 | ---------- |
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| 127 | |
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| 128 | Directory rtl/vhdl/ram_loader contains the sample design which loads the next |
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| 129 | image from the card and stores its contents to external asynchronous |
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| 130 | RAM. After reading 64 KB it triggers a new configuration process for the final |
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| 131 | FPGA design. |
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| 132 | Refer to the code for the mechanisms involved. |
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| 133 | |
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| 134 | |
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| 135 | Compiling the VHDL Code |
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| 136 | ----------------------- |
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| 137 | |
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| 138 | VHDL compilation and simulation tasks take place inside in sim/rtl_sim |
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| 139 | directory. The project setup supports only the GHDL simulator (see |
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| 140 | http://ghdl.free.fr). |
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| 141 | |
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| 142 | To compile the code simply type at the shell |
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| 143 | |
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| 144 | $ make |
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| 145 | |
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| 146 | This should result in a file called tb_behav_c0 which can be executed as any |
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| 147 | other executable. |
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| 148 | |
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| 149 | The basic simple sequence list can be found in COMPILE_LIST. This can be |
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| 150 | useful to quickly set up the analyze stage of any compiler or |
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| 151 | synthesizer. Especially when synthesizing the code, you want to skip the VHDL |
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| 152 | configurations in *-c.vhd and everything below the bench/ directory. |
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| 153 | |
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| 154 | |
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| 155 | References |
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| 156 | ---------- |
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| 157 | |
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| 158 | * SanDisk SD Card Product Manual |
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| 159 | http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf |
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| 160 | |
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| 161 | * SanDisk MMC Product Manual |
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| 162 | http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf |
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| 163 | |
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| 164 | * Toshiba SD Card Specification |
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| 165 | http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf |
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| 166 | |
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| 167 | * BurchED |
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| 168 | http://burched.biz/ |
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| 169 | |
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| 170 | * FPGA MMC-Card Config project |
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| 171 | http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview |
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