[2384] | 1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
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| 2 | <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
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| 3 | |
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| 4 | <header> |
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| 5 | <!-- ISE source project file created by Project Navigator. --> |
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| 6 | <!-- --> |
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| 7 | <!-- This file contains project source information including a list of --> |
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| 8 | <!-- project source files, project and process properties. This file, --> |
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| 9 | <!-- along with the project source files, is sufficient to open and --> |
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| 10 | <!-- implement in ISE Project Navigator. --> |
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| 11 | <!-- --> |
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| 12 | <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> |
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| 13 | </header> |
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| 14 | |
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| 15 | <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> |
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| 16 | |
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| 17 | <files> |
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| 18 | <file xil_pn:name="src/spi_boot.vhd" xil_pn:type="FILE_VHDL"> |
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| 19 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
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| 20 | <association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
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| 21 | </file> |
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| 22 | <file xil_pn:name="src/spi_boot_pack-p.vhd" xil_pn:type="FILE_VHDL"> |
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| 23 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
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| 24 | <association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
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| 25 | </file> |
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| 26 | <file xil_pn:name="src/spi_counter.vhd" xil_pn:type="FILE_VHDL"> |
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| 27 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
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| 28 | <association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
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| 29 | </file> |
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| 30 | <file xil_pn:name="src/w3_cpld_sd_config.ucf" xil_pn:type="FILE_UCF"> |
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| 31 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 32 | </file> |
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| 33 | <file xil_pn:name="src/w3_cpld_sd_config.v" xil_pn:type="FILE_VERILOG"> |
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| 34 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
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| 35 | <association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
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| 36 | </file> |
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| 37 | </files> |
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| 38 | |
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| 39 | <properties> |
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| 40 | <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 41 | <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 42 | <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 43 | <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
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| 44 | <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 45 | <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 46 | <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 47 | <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 48 | <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 49 | <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
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| 50 | <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
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| 51 | <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
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| 52 | <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 53 | <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/> |
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| 54 | <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/> |
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| 55 | <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 56 | <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 57 | <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 58 | <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 59 | <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 60 | <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 61 | <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/> |
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| 62 | <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
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| 63 | <property xil_pn:name="Device" xil_pn:value="xc2c128" xil_pn:valueState="non-default"/> |
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| 64 | <property xil_pn:name="Device Family" xil_pn:value="CoolRunner2 CPLDs" xil_pn:valueState="non-default"/> |
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| 65 | <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/> |
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| 66 | <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 67 | <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 68 | <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 69 | <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
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| 70 | <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 71 | <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
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| 72 | <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 73 | <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/> |
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| 74 | <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
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| 75 | <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
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| 76 | <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
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| 77 | <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 78 | <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 79 | <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 80 | <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 81 | <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
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| 82 | <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 83 | <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 84 | <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
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| 85 | <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
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| 86 | <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
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| 87 | <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/> |
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| 88 | <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
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| 89 | <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/> |
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| 90 | <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
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| 91 | <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/> |
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| 92 | <property xil_pn:name="Implementation Top" xil_pn:value="Module|w3_config_cpld" xil_pn:valueState="non-default"/> |
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| 93 | <property xil_pn:name="Implementation Top File" xil_pn:value="src/w3_cpld_sd_config.v" xil_pn:valueState="non-default"/> |
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| 94 | <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/w3_config_cpld" xil_pn:valueState="non-default"/> |
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| 95 | <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 96 | <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 97 | <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 98 | <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 99 | <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 100 | <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/> |
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| 101 | <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 102 | <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
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| 103 | <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
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| 104 | <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/> |
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| 105 | <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
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| 106 | <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
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| 107 | <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
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| 108 | <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 109 | <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 110 | <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
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| 111 | <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 112 | <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/> |
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| 113 | <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 114 | <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 115 | <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/> |
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| 116 | <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
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| 117 | <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
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| 118 | <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
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| 119 | <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
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| 120 | <property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/> |
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| 121 | <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
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| 122 | <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
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| 123 | <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 124 | <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 125 | <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/> |
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| 126 | <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
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| 127 | <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
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| 128 | <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
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| 129 | <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 130 | <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 131 | <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 132 | <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 133 | <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
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| 134 | <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/> |
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| 135 | <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 136 | <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 137 | <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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| 138 | <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 139 | <property xil_pn:name="Output File Name" xil_pn:value="w3_config_cpld" xil_pn:valueState="default"/> |
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| 140 | <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/> |
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| 141 | <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 142 | <property xil_pn:name="Package" xil_pn:value="VQ100" xil_pn:valueState="default"/> |
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| 143 | <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
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| 144 | <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="w3_config_cpld_map.v" xil_pn:valueState="default"/> |
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| 145 | <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="w3_config_cpld_timesim.v" xil_pn:valueState="default"/> |
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| 146 | <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="w3_config_cpld_synthesis.v" xil_pn:valueState="default"/> |
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| 147 | <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="w3_config_cpld_translate.v" xil_pn:valueState="default"/> |
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| 148 | <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
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| 149 | <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 150 | <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 151 | <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
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| 152 | <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
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| 153 | <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
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| 154 | <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
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| 155 | <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
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| 156 | <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> |
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| 157 | <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
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| 158 | <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
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| 159 | <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 160 | <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 161 | <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 162 | <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 163 | <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 164 | <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 165 | <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
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| 166 | <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
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| 167 | <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
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| 168 | <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
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| 169 | <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
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| 170 | <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
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| 171 | <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 172 | <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
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| 173 | <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
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| 174 | <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
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| 175 | <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
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| 176 | <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
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| 177 | <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
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| 178 | <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
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| 179 | <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> |
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| 180 | <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/> |
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| 181 | <property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="non-default"/> |
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| 182 | <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
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| 183 | <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
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| 184 | <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/> |
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| 185 | <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
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| 186 | <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
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| 187 | <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/> |
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| 188 | <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 189 | <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 190 | <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 191 | <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 192 | <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 193 | <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 194 | <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 195 | <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 196 | <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 197 | <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 198 | <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 199 | <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 200 | <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 201 | <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 202 | <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 203 | <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 204 | <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 205 | <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/> |
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| 206 | <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 207 | <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 208 | <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 209 | <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 210 | <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
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| 211 | <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
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| 212 | <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
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| 213 | <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 214 | <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
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| 215 | <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/> |
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| 216 | <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
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| 217 | <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/> |
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| 218 | <!-- --> |
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| 219 | <!-- The following properties are for internal use only. These should not be modified.--> |
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| 220 | <!-- --> |
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| 221 | <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
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| 222 | <property xil_pn:name="PROP_DesignName" xil_pn:value="w3_config_cpld" xil_pn:valueState="non-default"/> |
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| 223 | <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xbr" xil_pn:valueState="default"/> |
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| 224 | <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
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| 225 | <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
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| 226 | <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
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| 227 | <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
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| 228 | <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
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| 229 | <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
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| 230 | <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
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| 231 | <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-11-12T11:19:35" xil_pn:valueState="non-default"/> |
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| 232 | <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="409EC63038DD4049A9765966A1D78507" xil_pn:valueState="non-default"/> |
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| 233 | <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
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| 234 | <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
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| 235 | </properties> |
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| 236 | |
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| 237 | <bindings/> |
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| 238 | |
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| 239 | <libraries/> |
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| 240 | |
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| 241 | <autoManagedFiles> |
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| 242 | <!-- The following files are identified by `include statements in verilog --> |
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| 243 | <!-- source files and are automatically managed by Project Navigator. --> |
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| 244 | <!-- --> |
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| 245 | <!-- Do not hand-edit this section, as it will be overwritten when the --> |
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| 246 | <!-- project is analyzed based on files automatically identified as --> |
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| 247 | <!-- include files. --> |
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| 248 | </autoManagedFiles> |
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| 249 | |
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| 250 | </project> |
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