1 | ###################################################################
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2 | # Copyright (c) 2006 Rice University
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3 | # All Rights Reserved
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4 | # This code is covered by the Rice-WARP license
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5 | # See http://warp.rice.edu/license/ for details
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6 | ###################################################################
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7 |
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8 | BEGIN analog_bridge
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9 |
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10 | ## Peripheral Options
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11 | OPTION IPTYPE = IP
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12 | OPTION IMP_NETLIST = TRUE
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13 | OPTION HDL = VERILOG
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14 | OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE)
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15 | OPTION IP_GROUP = USER
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16 | OPTION USAGE_LEVEL = BASE_USER
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17 |
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18 | IO_INTERFACE IO_IF = analog_bridge, IO_TYPE = WARP_ANALOGBRIDGE_V1
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19 |
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20 | ## Ports
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21 | ####################################################################################
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22 | ## User Ports
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23 | ## The user must connect sources/sinks to these ports in XPS in order to use
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24 | ## the analog board. The rest of the board's connections are made automatically
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25 | ####################################################################################
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26 | PORT user_DAC1_A = "", DIR = I, VEC = [0:13], IO_IS = userDAC1A
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27 | PORT user_DAC1_B = "", DIR = I, VEC = [0:13], IO_IS = userDAC1B
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28 | PORT user_DAC2_A = "", DIR = I, VEC = [0:13], IO_IS = userDAC2A
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29 | PORT user_DAC2_B = "", DIR = I, VEC = [0:13], IO_IS = userDAC2B
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30 |
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31 | PORT user_DAC1_sleep = "net_gnd", DIR = I
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32 | PORT user_DAC2_sleep = "net_gnd", DIR = I
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33 |
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34 | PORT user_ADC_A = "", DIR = O, VEC = [0:13], IO_IS = userADCA
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35 | PORT user_ADC_B = "", DIR = O, VEC = [0:13], IO_IS = userADCB
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36 |
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37 | PORT user_ADC_DFS = "net_vcc", DIR = I
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38 | PORT user_ADC_DCS = "net_gnd", DIR = I
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39 | PORT user_ADC_pdwnA = "net_gnd", DIR = I
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40 | PORT user_ADC_pdwnB = "net_gnd", DIR = I
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41 | PORT user_ADC_otrA = "", DIR = O
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42 | PORT user_ADC_otrB = "", DIR = O
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43 | PORT user_LED = "", DIR = I, VEC = [0:2]
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44 |
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45 | ####################################################################################
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46 |
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47 | #Automatically tied to sys_clk_s, the OPB clock created by BSB
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48 | # Custom clock setups may need to change this
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49 | # Show defaults in System Assembly to view and change this assignment
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50 | PORT clock_in = "sys_clk_s", DIR = I, SIGIS = CLK
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51 |
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52 | PORT clock_out = "", DIR = O, SIGIS = CLK
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53 |
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54 | PORT analog_DAC1_A = "", DIR = O, VEC = [13:0], IO_IS = analogDAC1A, ENDIAN = LITTLE
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55 | PORT analog_DAC1_B = "", DIR = O, VEC = [13:0], IO_IS = analogDAC1B, ENDIAN = LITTLE
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56 | PORT analog_DAC2_A = "", DIR = O, VEC = [13:0], IO_IS = analogDAC2A, ENDIAN = LITTLE
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57 | PORT analog_DAC2_B = "", DIR = O, VEC = [13:0], IO_IS = analogDAC2B, ENDIAN = LITTLE
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58 | PORT analog_DAC1_sleep = "", DIR = O
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59 | PORT analog_DAC2_sleep = "", DIR = O
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60 |
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61 | PORT analog_ADC_A = "", DIR = I, VEC = [13:0], IO_IS = analogADCA, ENDIAN = LITTLE
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62 | PORT analog_ADC_B = "", DIR = I, VEC = [13:0], IO_IS = analogADCB, ENDIAN = LITTLE
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63 | PORT analog_ADC_DFS = "", DIR = O
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64 | PORT analog_ADC_DCS = "", DIR = O
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65 | PORT analog_ADC_pdwnA = "", DIR = O
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66 | PORT analog_ADC_pdwnB = "", DIR = O
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67 | PORT analog_ADC_otrA = "", DIR = I
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68 | PORT analog_ADC_otrB = "", DIR = I
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69 | PORT analog_LED = "", DIR = O, VEC = [0:2], IO_IS = analogLED
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70 |
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71 | END
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