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##
## Name     : clock_board_config
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN clock_board_config

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION USAGE_LEVEL = BASE_USER
OPTION DESC = WARP Clock Board Configuration Core
OPTION LONG_DESC = "Configures the Clock Board after FPGA configuration- requied to use the Clock Board oscillators as the master FPGA clock, sampling clock for Radio Boards and RF refence clock for Radio Boards."
OPTION IP_GROUP = USER
OPTION ARCH_SUPPORT_MAP = (virtex4=PREFERRED, virtex2p=PREFERRED, others=AVAILABLE)
OPTION RUN_NGCBUILD = FALSE
OPTION STYLE = HDL

IO_INTERFACE IO_IF = clock_board_config, IO_TYPE = WARP_CLKBRD_CONFIG_V1

## Bus Interfaces
# This core is not attached to any busses

## Generics for VHDL or Parameters for Verilog

PARAMETER radio_clk_source_sel_mode = 0, DT = std_logic, DESC = Selects whether to use radio_clk_src_sel port at boot to select radio RF clock source, VALUES = (0=Use Parameter, 1=Use Port), PERMIT = BASE_USER
PARAMETER logic_clk_source_sel_mode = 0, DT = std_logic, DESC = Selects whether to use logic_clk_src_sel port at boot to select sampling clock source, VALUES = (0=Use Parameter, 1=Use Port), PERMIT = BASE_USER

#platgen will infer these hex values and defparam them in the Verilog like "defparam clkbrdconfig_0.fpga_radio_clk_source = 'h1AFF;"
#since they're 16 bits anyway, the ambiguous bit length in the defparam'd value is no problem
#PARAMETER fpga_radio_clk_source = 0x1AFF, DT = std_logic_vector, DESC = Selects radio reference clock source, VALUES = (0x1AFF=Oscillator, 0x1DFF=External Coax), PERMIT = BASE_USER
#PARAMETER fpga_logic_clk_source = 0x1AFF, DT = std_logic_vector, DESC = Selects FPGA/sampling clock source, VALUES = (0x1AFF=Oscillator, 0x1DFF=External Coax), PERMIT = BASE_USER
PARAMETER fpga_radio_clk_source = 0, DT = std_logic, DESC = Selects radio reference clock source, VALUES = (0=Oscillator, 1=External Coax), PERMIT = BASE_USER
PARAMETER fpga_logic_clk_source = 0, DT = std_logic, DESC = Selects FPGA/sampling clock source, VALUES = (0=Oscillator, 1=External Coax), PERMIT = BASE_USER

# Parameters controlling en/disable on radio reference clk outputs
#  0x01ff disables the corresponding output
#  0x1eff enables the corresponding ouptput
# By default, outputs for slots 2 and 3 are enabled, matching
#  the hardware config for a WARP MIMO kit
PARAMETER radio_clk_out4_mode = 0x01ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock on J12 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
PARAMETER radio_clk_out5_mode = 0x1eff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock on J11 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
PARAMETER radio_clk_out6_mode = 0x1eff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock on J10 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
PARAMETER radio_clk_out7_mode = 0x01ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock on J6 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER

# Parameters controlling en/disable on radio sampling clk outputs
#  0x02ff disables the corresponding output
#  0x04ff enables the corresponding output with min (340mV) drive
#  0x08ff enables the corresponding output with max (810mV) drive
# By default, outputs for slots 2 and 3 are enabled, matching
#  the hardware config for a WARP MIMO kit
PARAMETER logic_clk_out0_mode = 0x02ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock on J8 - disabled by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x00ff=Enabled - 500mV drive, 0x0Cff=Enabled - 660mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
PARAMETER logic_clk_out1_mode = 0x02ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock on J7 - disabled by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x00ff=Enabled - 500mV drive, 0x0Cff=Enabled - 660mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
PARAMETER logic_clk_out2_mode = 0x08ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock on J9 - 810mV drive by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x00ff=Enabled - 500mV drive, 0x0Cff=Enabled - 660mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
PARAMETER logic_clk_out3_mode = 0x08ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock on J13 - 810mV drive by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x00ff=Enabled - 500mV drive, 0x0Cff=Enabled - 660mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER

# Parameters controlling the clock outputs for off-board use
#  These ports are only used when sharing clocks between nodes
PARAMETER radio_clk_forward_out_mode = 0x0BFF, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock forward port for off-board use - disabled by default, VALUES = (0x0BFF=Disabled, 0x08FF=Enabled), PERMIT = BASE_USER
PARAMETER logic_clk_forward_out_mode = 0x1FFF, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock forward port for off-board use - disabled by default, VALUES = (0x1FFF=Disabled, 0x1EFF=Enabled), PERMIT = BASE_USER

PARAMETER sys_clk_freq_hz = 0x05f5e100, DT = std_logic_vector, DESC = Frequency of clock at sys_clk input, VALUES = (0x05f5e100=100MHz, 0x1F78A40=33MHz), PERMIT = BASE_USER
PARAMETER scp_min_freq_hz = 0x002625a0, DT = std_logic_vector, DESC = Minimum serial I/O frequency, VALUES = (0x002625a0=25MHz), PERMIT = BASE_USER

PARAMETER scp_cyc_leng_a = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
PARAMETER scp_cyc_leng_b = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
PARAMETER scp_cyc_leng = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER

## Ports
PORT sys_clk = "", DIR = I, SIGIS = CLK, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_CLKIN, PERMIT = BASE_USER
PORT sys_rst = "net_gnd", DIR = I, SIGIS = RST, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RST, PERMIT = BASE_USER
PORT cfg_radio_dat_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFDOUT, PERMIT = BASE_USER
PORT cfg_radio_csb_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFCS, PERMIT = BASE_USER
PORT cfg_radio_en_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFEN, PERMIT = BASE_USER
PORT cfg_radio_clk_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFSCLK, PERMIT = BASE_USER
PORT cfg_logic_dat_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPDOUT, PERMIT = BASE_USER
PORT cfg_logic_csb_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPCS, PERMIT = BASE_USER
PORT cfg_logic_en_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPEN, PERMIT = BASE_USER
PORT cfg_logic_clk_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPSCLK, PERMIT = BASE_USER

PORT radio_clk_src_sel = "net_gnd", DIR = I, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFSRCSEL, PERMIT = BASE_USER
PORT logic_clk_src_sel = "net_gnd", DIR = I, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPSRCSEL, PERMIT = BASE_USER


#This output must be connected to the reset of the project's
# clock generator, in order to hold the system's DCMs in reset
# until the clock board outputs are providing valid clock signals
#Unfortunately it seems BSB can't make this connection automatically, 
# since BSB infers the DCM later, when instantiating the clock_genertor
#The ASSIGNMENT=REQUIRE here throws an early error on purpose
#  (vs. waiting to see things not work in hardware)
PORT config_invalid = "", DIR = O, ASSIGNMENT = REQUIRE, SIGIS = RST, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_CLKINV, PERMIT = BASE_USER

END