1 | // The two clocks fed to the FPGA over the clock board |
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2 | // header orginate in the AD9510 that supplied A/D and |
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3 | // D/A (logic) clocks. OUT5 supplies the two series |
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4 | // terminated CMOS outputs, while OUT4 supplies the LVDS |
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5 | // outputs that are (should be) parallel terminated at |
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6 | // the inputs of the FPGA. |
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7 | // |
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8 | // To support various operating modes, a variable is |
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9 | // defined to specify the operating modes for OUT4 and |
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10 | // OUT5. |
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11 | // |
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12 | // OUT 5 supplies + and - CMOS outputs (test mode) : 16'h1EFF |
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13 | // OUT 5 supplies + CMOS output only (normal mode) : 16'h0EFF |
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14 | // OUT 5 powered down : 16'h0FFF |
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15 | |
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16 | `define fpga_clk_out5_reg 16'h0EFF |
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17 | |
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18 | // OUT 4 supplies + and - CMOS outputs (test mode) : 16'h1EFF |
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19 | // OUT 4 powered down (normal mode) : 16'h07FF |
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20 | // OUT 4 supplies LVDS outputs : 16'h06FF |
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21 | |
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22 | `define fpga_clk_out4_reg 16'h07FF |
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23 | |
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24 | module clock_board_config ( |
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25 | sys_clk, |
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26 | sys_rst, |
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27 | |
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28 | cfg_radio_dat_out, |
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29 | cfg_radio_csb_out, |
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30 | cfg_radio_en_out, |
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31 | cfg_radio_clk_out, |
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32 | |
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33 | cfg_logic_dat_out, |
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34 | cfg_logic_csb_out, |
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35 | cfg_logic_en_out, |
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36 | cfg_logic_clk_out, |
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37 | |
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38 | radio_clk_src_sel, |
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39 | logic_clk_src_sel, |
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40 | |
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41 | config_invalid |
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42 | ); |
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43 | |
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44 | parameter sys_clk_freq_hz = 120000000; |
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45 | |
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46 | // Select whether to use ports or parameters to select the clock sources |
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47 | // 0: Use parameter (fpga_radio_clk_source or fpga_logic_clk_source) |
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48 | // 1: Use port (radio_clk_src_sel or logic_clk_src_sel) |
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49 | parameter radio_clk_source_sel_mode = 1'b0; |
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50 | parameter logic_clk_source_sel_mode = 1'b0; |
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51 | |
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52 | // Select the input source for the radio clocks. |
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53 | // CLK source for radio distribution = oscillator : 0; //16'h1AFF |
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54 | // CLK source for radio distribution = external coax : 1; //16'h1DFF |
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55 | //parameter fpga_radio_clk_source = 16'h1Aff; |
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56 | parameter fpga_radio_clk_source = 1'b0; |
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57 | |
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58 | // Select the input source for the logic (A/D and D/A) clocks. |
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59 | // CLK source for logic distribution = oscillator : 0; //16'h1AFF |
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60 | // CLK source for logic distribution = external coax : 1; //16'h1DFF |
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61 | //parameter fpga_logic_clk_source = 16'h1Aff; |
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62 | parameter fpga_logic_clk_source = 1'b0; |
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63 | |
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64 | // Parameters controlling en/disable on radio reference clk outputs |
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65 | // 0x01ff disables the corresponding output |
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66 | // 0x1eff enables the corresponding ouptput |
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67 | // By default, outputs for slots 2 and 3 are enabled, matching |
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68 | // the hardware config for a WARP MIMO kit |
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69 | parameter radio_clk_out4_mode = 16'h01ff; //J12 |
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70 | parameter radio_clk_out5_mode = 16'h1eff; //J11 (usually radio in slot 3) |
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71 | parameter radio_clk_out6_mode = 16'h1eff; //J10 (usually radio in slot 2) |
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72 | parameter radio_clk_out7_mode = 16'h01ff; //J6 |
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73 | |
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74 | // Parameter controlling whether to enable the off-board output of |
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75 | // the radio reference clock (used for dasiy-chaining clocks) |
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76 | // 0x0BFF is disabled; 0x08FF is enabled |
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77 | parameter radio_clk_forward_out_mode = 16'h0BFF; |
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78 | |
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79 | // Parameters controlling en/disable on radio sampling clk outputs |
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80 | // 0x02ff disables the corresponding output |
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81 | // 0x04ff enables the corresponding output with min (340mV) drive |
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82 | // 0x08ff enables the corresponding output with max (810mV) drive |
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83 | // By default, outputs for slots 2 and 3 are enabled, matching |
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84 | // the hardware config for a WARP MIMO kit |
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85 | parameter logic_clk_out0_mode = 16'h02ff; //J8 |
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86 | parameter logic_clk_out1_mode = 16'h02ff; //J7 |
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87 | parameter logic_clk_out2_mode = 16'h08ff; //J9 (usually radio in slot 3) |
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88 | parameter logic_clk_out3_mode = 16'h08ff; //J13 (usually radio in slot 2) |
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89 | |
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90 | // Parameter controlling whether to enable the off-board output of |
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91 | // the radio sampling clock (used for dasiy-chaining clocks) |
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92 | // 0xh1FFF is disabled; 0xh1EFF is enabled |
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93 | parameter logic_clk_forward_out_mode = 16'h1FFF; |
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94 | |
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95 | input sys_clk; |
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96 | input sys_rst; |
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97 | |
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98 | output cfg_radio_dat_out; reg cfg_radio_dat_out = 1'b1; |
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99 | output cfg_radio_csb_out; reg cfg_radio_csb_out = 1'b1; |
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100 | output cfg_radio_en_out; reg cfg_radio_en_out = 1'b1; |
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101 | output cfg_radio_clk_out; reg cfg_radio_clk_out = 1'b1; |
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102 | |
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103 | output cfg_logic_dat_out; reg cfg_logic_dat_out = 1'b1; |
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104 | output cfg_logic_csb_out; reg cfg_logic_csb_out = 1'b1; |
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105 | output cfg_logic_en_out; reg cfg_logic_en_out = 1'b1; |
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106 | output cfg_logic_clk_out; reg cfg_logic_clk_out = 1'b1; |
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107 | |
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108 | input radio_clk_src_sel; |
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109 | input logic_clk_src_sel; |
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110 | |
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111 | wire srl11_radio_src_sel_ext_Q; |
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112 | wire srl11_radio_src_sel_osc_Q; |
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113 | wire srl11_logic_src_sel_ext_Q; |
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114 | wire srl11_logic_src_sel_osc_Q; |
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115 | wire srl11_radio_Q; |
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116 | wire srl11_logic_Q; |
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117 | |
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118 | output config_invalid; |
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119 | |
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120 | // SCP_CNT [7:0] increments throughout each clock period |
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121 | // of the AD9510 serial control port (SCP). The absolute |
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122 | // maximum clock frequency for the SCP is 25 MHz, but I'm |
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123 | // limiting it to 12.5 MHz to be conservative. If the |
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124 | // system clock operates at exactly 87.5 MHz, then the |
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125 | // minimum SCP clock period would equal exactly seven |
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126 | // SYS_CLK periods. In this case, SCP_CNT cycles through |
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127 | // seven values -- 0, 1, 2, ..., 6 -- durin each SCP clock |
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128 | // period. The result is an SCP clock period of 80 nsec |
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129 | // (12.5 MHz).. |
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130 | // |
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131 | // SCP_CYC_START and SCP_CYC_MID detect the start and middle |
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132 | // of each SCP cycle, respectively. The assertion of |
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133 | // SCP_CYC_START, when appropriate, causes the SCP clock |
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134 | // to go low. In this state, the assertion of SCP_CYC_MID |
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135 | // causes the SCP clock to return to its high state. |
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136 | |
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137 | parameter scp_min_freq_hz = 2500000; |
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138 | |
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139 | // a : How many SYS_CLK cycles per SCP cycle -- CEIL(X/Y)? |
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140 | // b : Impose a minimum of 2 SYS_CLK cycles per SCP cycle. |
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141 | |
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142 | parameter scp_cyc_leng_a = ((sys_clk_freq_hz + scp_min_freq_hz - 1) / scp_min_freq_hz); |
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143 | parameter scp_cyc_leng_b = (scp_cyc_leng_a < 2) ? 2 : scp_cyc_leng_a; |
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144 | parameter scp_cyc_leng = scp_cyc_leng_b; |
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145 | |
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146 | reg [3:0] scp_cnt_en = 4'b0000; // enable used for graceful power-up |
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147 | reg [7:0] scp_cnt = 8'b00000000; // SCP cycle counter |
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148 | reg scp_cnt_tc = 1'b0; // pulses HIGH during last SCP cycle to reset counter |
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149 | reg scp_cyc_start = 1'b0; // pulses high to denote start of each SCP clock period |
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150 | reg scp_cyc_mid = 1'b0; // pulses high to denote middle of each SCP clock period |
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151 | |
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152 | always @ (posedge sys_clk) |
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153 | begin |
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154 | scp_cnt_en [3:0] <= {1'b1,scp_cnt_en [3:1]}; |
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155 | |
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156 | if (~scp_cnt_en [0]) |
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157 | begin |
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158 | scp_cnt [7:0] <= 8'b00000000; |
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159 | scp_cnt_tc <= 1'b0; |
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160 | scp_cyc_start <= 1'b0; |
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161 | scp_cyc_mid <= 1'b0; |
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162 | end |
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163 | |
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164 | else |
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165 | begin |
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166 | if (~scp_cnt_tc) scp_cnt [7:0] <= scp_cnt [7:0] + 1; |
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167 | else scp_cnt [7:0] <= 8'b00000000; |
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168 | |
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169 | scp_cnt_tc <= (scp_cnt [7:0] == ((scp_cyc_leng + 0) - 2)); |
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170 | scp_cyc_start <= (scp_cnt [7:0] == 0 ); |
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171 | scp_cyc_mid <= (scp_cnt [7:0] == ((scp_cyc_leng + 1) / 2)); |
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172 | end |
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173 | |
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174 | end |
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175 | |
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176 | |
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177 | |
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178 | reg [3:0] sys_rst_lock = 4'b1111; |
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179 | reg [2:0] sys_rst_sync = 3'b111; |
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180 | |
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181 | always @ (posedge sys_clk or posedge sys_rst) |
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182 | begin |
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183 | if (sys_rst) sys_rst_lock [3] <= 1'b1; |
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184 | else sys_rst_lock [3] <= 1'b0; |
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185 | end |
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186 | |
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187 | always @ (posedge sys_clk or posedge sys_rst_lock [3]) |
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188 | begin |
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189 | if (sys_rst_lock [3]) sys_rst_lock [2:0] <= 3'b111; |
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190 | else sys_rst_lock [2:0] <= {1'b0,sys_rst_lock [2:1]}; |
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191 | end |
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192 | |
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193 | always @ (posedge sys_clk) |
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194 | begin |
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195 | sys_rst_sync [2:0] <= {sys_rst_lock [0],sys_rst_sync [2:1]}; |
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196 | end |
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197 | |
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198 | |
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199 | |
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200 | // CFG_CYC [9:0] increments by 1 following each assertion |
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201 | // of SCP_CYC_MID, until it finally "rolls over" to 0. |
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202 | // Coincident with this roll-over is the assertion of |
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203 | // CFG_CYC_DONE, thereby preventing any further increments |
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204 | // to CFG_CYC. The net result?... SCP_CYC_START and |
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205 | // SCP_CYC_MID each pulse high 1024 times while |
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206 | // CFG_CYC_DONE is deasserted (low). After this, |
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207 | // CFG_CYC_START and CFG_CYC_MID continue to pulse, but |
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208 | // CFG_CYC_DONE is asserted to mask of any "events" that |
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209 | // depend upon the START and MID pulses. |
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210 | // |
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211 | // EXAMPLE : SCP_CYC_LENG = 6... |
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212 | // |
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213 | // SYS_CLK : \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ |
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214 | // SCP_CYC_START : 0|0|0|0|0|0|0|0|0|1|0|0|0|0|0|1|0|0|0|0|0|1| ... |0|0|0|1|0|0|0|0|0|1|0|0|0|0|0|1| |
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215 | // SCP_CYC_MID : 0|0|0|0|0|0|0|0|0|0|0|0|1|0|0|0|0|0|1|0|0|0| ... |1|0|0|0|0|0|1|0|0|0|0|0|1|0|0|0| |
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216 | // CFG_CYC : 0 | 1 | 2 ... | 1023 | 0 |
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217 | // CFG_DONE : 0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0| ... |0|0|0|0|0|0|0|1|1|1|1|1|1|1|1|1| |
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218 | // |
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219 | // EXAMPLE : SCP_CYC_LENG = 2... |
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220 | // |
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221 | // Same as in the previous example, except that |
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222 | // SCP_CYC_START and SCP_CYC_MID are alternately pulsing |
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223 | // high and low 180 degrees out of phase with respect to |
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224 | // one another. |
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225 | |
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226 | reg [9:0] cfg_cyc = 10'b0000000000; |
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227 | reg cfg_cyc_done = 1'b1; |
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228 | reg cfg_restart = 1'b0; |
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229 | reg cfg_clk_low = 1'b0; |
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230 | reg cfg_clk_high = 1'b0; |
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231 | |
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232 | reg cfg_cyc_done_d1 = 1'b1; |
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233 | |
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234 | always @ (posedge sys_clk) |
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235 | begin |
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236 | cfg_cyc_done_d1 <= cfg_cyc_done; |
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237 | end |
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238 | |
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239 | |
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240 | |
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241 | always @ (posedge sys_clk) |
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242 | begin |
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243 | |
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244 | if (~scp_cyc_mid) |
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245 | begin |
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246 | cfg_cyc [9:0] <= cfg_cyc [9:0]; |
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247 | cfg_cyc_done <= cfg_cyc_done; |
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248 | end |
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249 | |
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250 | else |
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251 | begin |
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252 | if (cfg_cyc_done) |
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253 | begin |
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254 | cfg_cyc [9:0] <= 10'b0000000000; |
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255 | cfg_cyc_done <= ~cfg_restart; |
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256 | end |
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257 | |
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258 | else |
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259 | begin |
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260 | cfg_cyc [9:0] <= cfg_cyc [9:0] + 1; |
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261 | cfg_cyc_done <= (cfg_cyc [9:0] == 10'b1111111111); |
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262 | end |
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263 | end |
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264 | |
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265 | cfg_restart <= ~cfg_restart & cfg_cyc_done & (sys_rst_sync [1:0] == 2'b01) |
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266 | | cfg_restart & cfg_cyc_done & ~scp_cyc_mid; |
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267 | |
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268 | cfg_clk_low <= ~cfg_cyc_done & scp_cyc_start; |
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269 | cfg_clk_high <= ~cfg_cyc_done & scp_cyc_mid; |
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270 | end |
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271 | |
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272 | |
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273 | |
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274 | // For a given sequence generation register (chain of |
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275 | // SRLs), the SRL having index 0 delivers its data |
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276 | // first, followed by the SRL having index 1. The SRL |
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277 | // having index 63 delivers its data last. Hence the |
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278 | // input of SRL N is fed by the output of SRL N + 1. |
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279 | // The last SRL in each chain is fed with the output |
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280 | // of the first SRL in he chain so that the configuration |
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281 | // may be repeated on demand. |
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282 | // |
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283 | // Two sequence generators are defined, one for the |
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284 | // AD9510 that clocks the radio ICs for up- and down- |
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285 | // conversion, and another that clocks the FPGA and |
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286 | // the radio boards' converters. |
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287 | |
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288 | wire srl_shift; |
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289 | |
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290 | wire [63:0] srl_radio_d; |
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291 | wire [63:0] srl_radio_q; |
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292 | |
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293 | wire [63:0] srl_logic_d; |
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294 | wire [63:0] srl_logic_q; |
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295 | |
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296 | assign srl_shift = cfg_clk_low; |
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297 | //assign srl_radio_d [63:0] = {srl_radio_q [0],srl_radio_q [63:1]}; |
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298 | //assign srl_logic_d [63:0] = {srl_logic_q [0],srl_logic_q [63:1]}; |
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299 | assign srl_radio_d [63:0] = {srl_radio_q[0], srl_radio_q[63:12], srl11_radio_Q, srl_radio_q[10:1]}; |
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300 | assign srl_logic_d [63:0] = {srl_logic_q[0], srl_logic_q[63:12], srl11_logic_Q, srl_logic_q[10:1]}; |
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301 | |
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302 | //Select which srl will provide the clock source register value |
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303 | // if: |
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304 | // param x_clk_source_sel_mode==1 AND port x_clk_src_sel==1, select srl for external source |
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305 | // param x_clk_source_sel_mode==0 AND parameter fpga_x_clk_source==1, select srl for external source |
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306 | // else: |
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307 | // select srl for on-board oscillator |
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308 | assign srl11_radio_Q = ( (radio_clk_source_sel_mode & radio_clk_src_sel) | (~radio_clk_source_sel_mode & fpga_radio_clk_source) ) ? srl11_radio_src_sel_ext_Q : srl11_radio_src_sel_osc_Q; |
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309 | assign srl11_logic_Q = ( (logic_clk_source_sel_mode & logic_clk_src_sel) | (~logic_clk_source_sel_mode & fpga_logic_clk_source) ) ? srl11_logic_src_sel_ext_Q : srl11_logic_src_sel_osc_Q; |
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310 | |
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311 | reg config_invalid = 1'b1; |
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312 | |
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313 | always @(posedge sys_clk) |
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314 | begin |
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315 | if(cfg_cyc_done & ~cfg_cyc_done_d1) |
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316 | config_invalid <= 1'b0; |
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317 | else if(cfg_restart) |
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318 | config_invalid <= 1'b1; |
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319 | end |
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320 | |
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321 | // ALL SRLs in this module are configured for a static |
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322 | // shift length of 16. For a given 16-bit SRL INIT |
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323 | // value, the high order bit will be shifted out first, |
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324 | // while the low order bit will be shifted out last. |
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325 | // It is, therefore, VERY convenient to operate the |
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326 | // AD9510s in MSB first mode. Pros : This is the |
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327 | // default operating mode for the AD9510, and requires |
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328 | // no additional hocus pocus. Cons : Addresses are |
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329 | // decremented as data is written into each device. |
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330 | // This requires an extra control access to address |
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331 | // 5A in order to force the update -- not rocket science, |
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332 | // but very important to remember. See the AD9510 data |
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333 | // sheet, revision A, pages 42 and 43 for details. |
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334 | |
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335 | genvar ii; |
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336 | generate |
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337 | for (ii = 0 ; ii < 64 ; ii = ii + 1) |
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338 | begin : gen_srls |
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339 | |
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340 | SRL16E srl_radio ( |
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341 | .Q (srl_radio_q [ii]), |
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342 | .A0 (1'b1 ), |
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343 | .A1 (1'b1 ), |
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344 | .A2 (1'b1 ), |
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345 | .A3 (1'b1 ), |
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346 | .CE (srl_shift ), |
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347 | .CLK (sys_clk ), |
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348 | .D (srl_radio_d [ii]) |
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349 | ); |
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350 | |
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351 | SRL16E srl_logic ( |
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352 | .Q (srl_logic_q [ii]), |
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353 | .A0 (1'b1 ), |
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354 | .A1 (1'b1 ), |
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355 | .A2 (1'b1 ), |
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356 | .A3 (1'b1 ), |
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357 | .CE (srl_shift ), |
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358 | .CLK (sys_clk ), |
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359 | .D (srl_logic_d [ii]) |
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360 | ); |
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361 | |
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362 | end |
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363 | endgenerate |
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364 | |
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365 | SRL16E srl11_radio_src_sel_ext ( |
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366 | .Q (srl11_radio_src_sel_ext_Q), |
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367 | .A0 (1'b1 ), |
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368 | .A1 (1'b1 ), |
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369 | .A2 (1'b1 ), |
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370 | .A3 (1'b1 ), |
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371 | .CE (srl_shift ), |
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372 | .CLK (sys_clk ), |
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373 | .D (srl_radio_d [11]) |
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374 | ); |
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375 | |
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376 | SRL16E srl11_radio_src_sel_osc ( |
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377 | .Q (srl11_radio_src_sel_osc_Q), |
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378 | .A0 (1'b1 ), |
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379 | .A1 (1'b1 ), |
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380 | .A2 (1'b1 ), |
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381 | .A3 (1'b1 ), |
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382 | .CE (srl_shift ), |
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383 | .CLK (sys_clk ), |
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384 | .D (srl_radio_d [11]) |
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385 | ); |
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386 | |
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387 | SRL16E srl11_logic_src_sel_ext ( |
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388 | .Q (srl11_logic_src_sel_ext_Q), |
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389 | .A0 (1'b1 ), |
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390 | .A1 (1'b1 ), |
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391 | .A2 (1'b1 ), |
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392 | .A3 (1'b1 ), |
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393 | .CE (srl_shift ), |
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394 | .CLK (sys_clk ), |
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395 | .D (srl_logic_d [11]) |
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396 | ); |
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397 | |
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398 | SRL16E srl11_logic_src_sel_osc ( |
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399 | .Q (srl11_logic_src_sel_osc_Q), |
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400 | .A0 (1'b1 ), |
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401 | .A1 (1'b1 ), |
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402 | .A2 (1'b1 ), |
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403 | .A3 (1'b1 ), |
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404 | .CE (srl_shift ), |
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405 | .CLK (sys_clk ), |
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406 | .D (srl_logic_d [11]) |
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407 | ); |
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408 | |
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409 | defparam srl11_logic_src_sel_osc.INIT = 16'h1AFF; |
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410 | defparam srl11_logic_src_sel_ext.INIT = 16'h1DFF; |
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411 | defparam srl11_radio_src_sel_osc.INIT = 16'h1AFF; |
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412 | defparam srl11_radio_src_sel_ext.INIT = 16'h1DFF; |
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413 | |
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414 | // Here's where we define the register contents |
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415 | // Each "defparam gen_srls" corresponds to one 16 bit SPI transaction |
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416 | |
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417 | // Register contents for the radio reference generator |
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418 | |
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419 | // Leave some emtpy clock cycles at boot to let things settle |
---|
420 | defparam gen_srls[ 0].srl_radio.INIT = 16'hFFFF; // CYCLES 0 - 15 |
---|
421 | defparam gen_srls[ 1].srl_radio.INIT = 16'hFFFF; // CYCLES 16 - 31 |
---|
422 | defparam gen_srls[ 2].srl_radio.INIT = 16'hFFFF; // CYCLES 32 - 47 |
---|
423 | defparam gen_srls[ 3].srl_radio.INIT = 16'hFFFF; // CYCLES 48 - 63 |
---|
424 | defparam gen_srls[ 4].srl_radio.INIT = 16'hFFFF; // CYCLES 64 - 79 |
---|
425 | defparam gen_srls[ 5].srl_radio.INIT = 16'hFFFF; // CYCLES 80 - 95 |
---|
426 | |
---|
427 | // Issue soft-reset; does *not* require write to 5A to take effect |
---|
428 | // reg[0] <= 30, then 10 (assert, then de-assert reset bit) |
---|
429 | defparam gen_srls[ 6].srl_radio.INIT = 16'h0000; // CYCLES 96 - 111 |
---|
430 | defparam gen_srls[ 7].srl_radio.INIT = 16'h30FF; // CYCLES 112 - 127 |
---|
431 | |
---|
432 | defparam gen_srls[ 8].srl_radio.INIT = 16'h0000; // CYCLES 128 - 143 |
---|
433 | defparam gen_srls[ 9].srl_radio.INIT = 16'h10FF; // CYCLES 144 - 159 |
---|
434 | |
---|
435 | // Switch clock input to CLK2; power-down CLK1 and PLL input |
---|
436 | // reg[45] <= 1A |
---|
437 | defparam gen_srls[10].srl_radio.INIT = 16'h0045; // CYCLES 160 - 175 |
---|
438 | defparam gen_srls[11].srl_radio.INIT = fpga_radio_clk_source; // CYCLES 176 - 191 |
---|
439 | |
---|
440 | // Bypass dividers on all clocks |
---|
441 | // reg[49,4B,4D,4F,51,53,55,57] <= 80 |
---|
442 | |
---|
443 | defparam gen_srls[12].srl_radio.INIT = 16'h0049; // CYCLES 192 - 207 |
---|
444 | defparam gen_srls[13].srl_radio.INIT = 16'h80FF; // CYCLES 208 - 223 |
---|
445 | |
---|
446 | defparam gen_srls[14].srl_radio.INIT = 16'h004B; // CYCLES 224 - 239 |
---|
447 | defparam gen_srls[15].srl_radio.INIT = 16'h80FF; // CYCLES 240 - 255 |
---|
448 | |
---|
449 | defparam gen_srls[16].srl_radio.INIT = 16'h004D; // CYCLES 256 - 271 |
---|
450 | defparam gen_srls[17].srl_radio.INIT = 16'h80FF; // CYCLES 272 - 287 |
---|
451 | |
---|
452 | defparam gen_srls[18].srl_radio.INIT = 16'h004F; // CYCLES 288 - 303 |
---|
453 | defparam gen_srls[19].srl_radio.INIT = 16'h80FF; // CYCLES 304 - 319 |
---|
454 | |
---|
455 | defparam gen_srls[20].srl_radio.INIT = 16'h0051; // CYCLES 320 - 335 |
---|
456 | defparam gen_srls[21].srl_radio.INIT = 16'h80FF; // CYCLES 336 - 351 |
---|
457 | |
---|
458 | defparam gen_srls[22].srl_radio.INIT = 16'h0053; // CYCLES 352 - 367 |
---|
459 | defparam gen_srls[23].srl_radio.INIT = 16'h80FF; // CYCLES 368 - 383 |
---|
460 | |
---|
461 | defparam gen_srls[24].srl_radio.INIT = 16'h0055; // CYCLES 384 - 399 |
---|
462 | defparam gen_srls[25].srl_radio.INIT = 16'h80FF; // CYCLES 400 - 415 |
---|
463 | |
---|
464 | defparam gen_srls[26].srl_radio.INIT = 16'h0057; // CYCLES 416 - 431 |
---|
465 | defparam gen_srls[27].srl_radio.INIT = 16'h80FF; // CYCLES 432 - 447 |
---|
466 | |
---|
467 | // Configure the output properties on the CMOS clock outputs. |
---|
468 | // Enabled outputs require CMOS (not LVDS), invertered output enabled |
---|
469 | // reg[40,41,42,43] <= 1E means output is enabled |
---|
470 | // reg[40,41,42,43] <= 01 means output is disabled |
---|
471 | defparam gen_srls[28].srl_radio.INIT = 16'h0040; // CYCLES 448 - 463 |
---|
472 | defparam gen_srls[29].srl_radio.INIT = radio_clk_out4_mode; // CYCLES 464 - 479 |
---|
473 | |
---|
474 | defparam gen_srls[30].srl_radio.INIT = 16'h0041; // CYCLES 480 - 495 |
---|
475 | defparam gen_srls[31].srl_radio.INIT = radio_clk_out5_mode; // CYCLES 496 - 511 |
---|
476 | |
---|
477 | defparam gen_srls[32].srl_radio.INIT = 16'h0042; // CYCLES 512 - 527 |
---|
478 | defparam gen_srls[33].srl_radio.INIT = radio_clk_out6_mode; // CYCLES 528 - 543 |
---|
479 | |
---|
480 | defparam gen_srls[34].srl_radio.INIT = 16'h0043; // CYCLES 544 - 559 |
---|
481 | defparam gen_srls[35].srl_radio.INIT = radio_clk_out7_mode; // CYCLES 560 - 575 |
---|
482 | |
---|
483 | // Configure the output properties on the PECL clock outputs |
---|
484 | // OUT0 enabled, 810mV drive; OUT1/2/3 disabled |
---|
485 | // reg[3C] <= 08; reg[3D,3E,3F] <= 0B |
---|
486 | defparam gen_srls[36].srl_radio.INIT = 16'h003C; // CYCLES 576 - 591 |
---|
487 | //defparam gen_srls[37].srl_radio.INIT = 16'h08FF; // CYCLES 592 - 607 |
---|
488 | defparam gen_srls[37].srl_radio.INIT = radio_clk_forward_out_mode; // CYCLES 592 - 607 |
---|
489 | |
---|
490 | defparam gen_srls[38].srl_radio.INIT = 16'h003D; // CYCLES 608 - 623 |
---|
491 | defparam gen_srls[39].srl_radio.INIT = 16'h0BFF; // CYCLES 624 - 639 |
---|
492 | |
---|
493 | defparam gen_srls[40].srl_radio.INIT = 16'h003E; // CYCLES 640 - 655 |
---|
494 | defparam gen_srls[41].srl_radio.INIT = 16'h0BFF; // CYCLES 656 - 671 |
---|
495 | |
---|
496 | defparam gen_srls[42].srl_radio.INIT = 16'h003F; // CYCLES 672 - 687 |
---|
497 | defparam gen_srls[43].srl_radio.INIT = 16'h0BFF; // CYCLES 688 - 703 |
---|
498 | |
---|
499 | |
---|
500 | // Latch the loaded values into the actual config registers |
---|
501 | // reg[5A] <= FF |
---|
502 | defparam gen_srls[44].srl_radio.INIT = 16'h005A; // CYCLES 704 - 719 |
---|
503 | defparam gen_srls[45].srl_radio.INIT = 16'hFFFF; // CYCLES 720 - 735 |
---|
504 | |
---|
505 | // unused cycles |
---|
506 | defparam gen_srls[46].srl_radio.INIT = 16'hFFFF; // CYCLES 736 - 751 |
---|
507 | defparam gen_srls[47].srl_radio.INIT = 16'hFFFF; // CYCLES 752 - 767 |
---|
508 | defparam gen_srls[48].srl_radio.INIT = 16'hFFFF; // CYCLES 768 - 783 |
---|
509 | defparam gen_srls[49].srl_radio.INIT = 16'hFFFF; // CYCLES 784 - 799 |
---|
510 | defparam gen_srls[50].srl_radio.INIT = 16'hFFFF; // CYCLES 800 - 815 |
---|
511 | defparam gen_srls[51].srl_radio.INIT = 16'hFFFF; // CYCLES 816 - 831 |
---|
512 | defparam gen_srls[52].srl_radio.INIT = 16'hFFFF; // CYCLES 832 - 847 |
---|
513 | defparam gen_srls[53].srl_radio.INIT = 16'hFFFF; // CYCLES 848 - 863 |
---|
514 | defparam gen_srls[54].srl_radio.INIT = 16'hFFFF; // CYCLES 864 - 879 |
---|
515 | defparam gen_srls[55].srl_radio.INIT = 16'hFFFF; // CYCLES 880 - 895 |
---|
516 | defparam gen_srls[56].srl_radio.INIT = 16'hFFFF; // CYCLES 896 - 911 |
---|
517 | defparam gen_srls[57].srl_radio.INIT = 16'hFFFF; // CYCLES 912 - 927 |
---|
518 | defparam gen_srls[58].srl_radio.INIT = 16'hFFFF; // CYCLES 928 - 943 |
---|
519 | defparam gen_srls[59].srl_radio.INIT = 16'hFFFF; // CYCLES 944 - 959 |
---|
520 | defparam gen_srls[60].srl_radio.INIT = 16'hFFFF; // CYCLES 960 - 975 |
---|
521 | defparam gen_srls[61].srl_radio.INIT = 16'hFFFF; // CYCLES 976 - 991 |
---|
522 | defparam gen_srls[62].srl_radio.INIT = 16'hFFFF; // CYCLES 992 - 1007 |
---|
523 | defparam gen_srls[63].srl_radio.INIT = 16'hFFFF; // CYCLES 1008 - 1023 |
---|
524 | |
---|
525 | // Here's some m-code that will help generate these vectors: |
---|
526 | // csb_low = 96 + 32*[0:15];sprintf('cfg_cyc == %d | ',csb_low) |
---|
527 | // csb_high = 96-8 + 32*[1:16];sprintf('cfg_cyc == %d | ',csb_high) |
---|
528 | |
---|
529 | `define RADIO_CSB_LOW_DECODE ((cfg_cyc == 96) | (cfg_cyc == 128) | (cfg_cyc == 160) | (cfg_cyc == 192) | (cfg_cyc == 224) | (cfg_cyc == 256) | (cfg_cyc == 288) | (cfg_cyc == 320) | (cfg_cyc == 352) | (cfg_cyc == 384) | (cfg_cyc == 416) | (cfg_cyc == 448) | (cfg_cyc == 480) | (cfg_cyc == 512) | (cfg_cyc == 544) | (cfg_cyc == 576) | (cfg_cyc == 608) | (cfg_cyc == 640) | (cfg_cyc == 672) | (cfg_cyc == 704)) |
---|
530 | `define RADIO_CSB_HIGH_DECODE ((cfg_cyc == 120) | (cfg_cyc == 152) | (cfg_cyc == 184) | (cfg_cyc == 216) | (cfg_cyc == 248) | (cfg_cyc == 280) | (cfg_cyc == 312) | (cfg_cyc == 344) | (cfg_cyc == 376) | (cfg_cyc == 408) | (cfg_cyc == 440) | (cfg_cyc == 472) | (cfg_cyc == 504) | (cfg_cyc == 536) | (cfg_cyc == 568) | (cfg_cyc == 600) | (cfg_cyc == 632) | (cfg_cyc == 664) | (cfg_cyc == 696) | (cfg_cyc == 728)) |
---|
531 | `define RADIO_EN_LOW_DECODE ( cfg_cyc == 0) |
---|
532 | `define RADIO_EN_HIGH_DECODE ( cfg_cyc == 4) |
---|
533 | |
---|
534 | //Register contents for the converter clock generator |
---|
535 | |
---|
536 | // Leave some emtpy clock cycles at boot to let things settle |
---|
537 | defparam gen_srls[ 0].srl_logic.INIT = 16'hFFFF; // CYCLES 0 - 15 |
---|
538 | defparam gen_srls[ 1].srl_logic.INIT = 16'hFFFF; // CYCLES 16 - 31 |
---|
539 | defparam gen_srls[ 2].srl_logic.INIT = 16'hFFFF; // CYCLES 32 - 47 |
---|
540 | defparam gen_srls[ 3].srl_logic.INIT = 16'hFFFF; // CYCLES 48 - 63 |
---|
541 | defparam gen_srls[ 4].srl_logic.INIT = 16'hFFFF; // CYCLES 64 - 79 |
---|
542 | defparam gen_srls[ 5].srl_logic.INIT = 16'hFFFF; // CYCLES 80 - 95 |
---|
543 | |
---|
544 | // Issue soft-reset; does *not* require write to 5A to take effect |
---|
545 | // reg[0] <= 30, then 10 (assert, then de-assert reset bit) |
---|
546 | defparam gen_srls[ 6].srl_logic.INIT = 16'h0000; // CYCLES 96 - 111 |
---|
547 | defparam gen_srls[ 7].srl_logic.INIT = 16'h30FF; // CYCLES 112 - 127 |
---|
548 | |
---|
549 | defparam gen_srls[ 8].srl_logic.INIT = 16'h0000; // CYCLES 128 - 143 |
---|
550 | defparam gen_srls[ 9].srl_logic.INIT = 16'h10FF; // CYCLES 144 - 159 |
---|
551 | |
---|
552 | // Switch clock input to CLK2; power-down CLK1 and PLL input |
---|
553 | // reg[45] <= 1A |
---|
554 | // defparam gen_srls[10].srl_logic.INIT = 16'h0045; // CYCLES 160 - 175 |
---|
555 | // defparam gen_srls[11].srl_logic.INIT = 16'h1AFF; // CYCLES 176 - 191 |
---|
556 | |
---|
557 | // For now, switch clock input to CLK1; power-down CLK2 and PLL input |
---|
558 | // reg[45] <= 1D |
---|
559 | defparam gen_srls[10].srl_logic.INIT = 16'h0045; // CYCLES 160 - 175 |
---|
560 | defparam gen_srls[11].srl_logic.INIT = fpga_logic_clk_source; // CYCLES 176 - 191 |
---|
561 | |
---|
562 | // Bypass dividers on all clocks |
---|
563 | // reg[49,4B,4D,4F,51,53,55,57] <= 80 |
---|
564 | |
---|
565 | defparam gen_srls[12].srl_logic.INIT = 16'h0049; // CYCLES 192 - 207 |
---|
566 | defparam gen_srls[13].srl_logic.INIT = 16'h80FF; // CYCLES 208 - 223 |
---|
567 | |
---|
568 | defparam gen_srls[14].srl_logic.INIT = 16'h004B; // CYCLES 224 - 239 |
---|
569 | defparam gen_srls[15].srl_logic.INIT = 16'h80FF; // CYCLES 240 - 255 |
---|
570 | |
---|
571 | defparam gen_srls[16].srl_logic.INIT = 16'h004D; // CYCLES 256 - 271 |
---|
572 | defparam gen_srls[17].srl_logic.INIT = 16'h80FF; // CYCLES 272 - 287 |
---|
573 | |
---|
574 | defparam gen_srls[18].srl_logic.INIT = 16'h004F; // CYCLES 288 - 303 |
---|
575 | defparam gen_srls[19].srl_logic.INIT = 16'h80FF; // CYCLES 304 - 319 |
---|
576 | |
---|
577 | defparam gen_srls[20].srl_logic.INIT = 16'h0051; // CYCLES 320 - 335 |
---|
578 | defparam gen_srls[21].srl_logic.INIT = 16'h80FF; // CYCLES 336 - 351 |
---|
579 | |
---|
580 | defparam gen_srls[22].srl_logic.INIT = 16'h0053; // CYCLES 352 - 367 |
---|
581 | defparam gen_srls[23].srl_logic.INIT = 16'h80FF; // CYCLES 368 - 383 |
---|
582 | |
---|
583 | defparam gen_srls[24].srl_logic.INIT = 16'h0055; // CYCLES 384 - 399 |
---|
584 | defparam gen_srls[25].srl_logic.INIT = 16'h80FF; // CYCLES 400 - 415 |
---|
585 | |
---|
586 | defparam gen_srls[26].srl_logic.INIT = 16'h0057; // CYCLES 416 - 431 |
---|
587 | defparam gen_srls[27].srl_logic.INIT = 16'h80FF; // CYCLES 432 - 447 |
---|
588 | |
---|
589 | // Configure the output properties on the PECL clock outputs |
---|
590 | // OUT0-OUT3 enabled, 810mV drive; |
---|
591 | // reg[3C,3D,3E,3F] <= 08; enables outputs with max (810mV) drive |
---|
592 | // reg[3C,3D,3E,3F] <= 04; enables outputs with min (340mV) drive |
---|
593 | // reg[3C,3D,3E,3F] <= 02; disables outputs |
---|
594 | |
---|
595 | defparam gen_srls[28].srl_logic.INIT = 16'h003C; // CYCLES 448 - 463 |
---|
596 | defparam gen_srls[29].srl_logic.INIT = logic_clk_out0_mode; // CYCLES 464 - 479 |
---|
597 | |
---|
598 | defparam gen_srls[30].srl_logic.INIT = 16'h003D; // CYCLES 480 - 495 |
---|
599 | defparam gen_srls[31].srl_logic.INIT = logic_clk_out1_mode; // CYCLES 496 - 511 |
---|
600 | |
---|
601 | defparam gen_srls[32].srl_logic.INIT = 16'h003E; // CYCLES 512 - 527 |
---|
602 | defparam gen_srls[33].srl_logic.INIT = logic_clk_out2_mode; // CYCLES 528 - 543 |
---|
603 | |
---|
604 | defparam gen_srls[34].srl_logic.INIT = 16'h003F; // CYCLES 544 - 559 |
---|
605 | defparam gen_srls[35].srl_logic.INIT = logic_clk_out3_mode; // CYCLES 560 - 575 |
---|
606 | |
---|
607 | // Configure the output properties for the forwarded clock (OUT7) |
---|
608 | // CMOS (not LVDS), inverted output enabled, maximum drive current |
---|
609 | // reg[43] <= 1E; |
---|
610 | defparam gen_srls[36].srl_logic.INIT = 16'h0043; // CYCLES 576 - 591 |
---|
611 | //defparam gen_srls[37].srl_logic.INIT = 16'h1EFF; // CYCLES 592 - 607 |
---|
612 | defparam gen_srls[37].srl_logic.INIT = logic_clk_forward_out_mode; // CYCLES 592 - 607 |
---|
613 | |
---|
614 | // Power down CMOS OUT6 |
---|
615 | // reg[42] <= 1F; |
---|
616 | defparam gen_srls[38].srl_logic.INIT = 16'h0042; // CYCLES 608 - 623 |
---|
617 | defparam gen_srls[39].srl_logic.INIT = 16'h1FFF; // CYCLES 624 - 639 |
---|
618 | |
---|
619 | // OUT5 : See comments at the top of this file |
---|
620 | defparam gen_srls[40].srl_logic.INIT = 16'h0041; // CYCLES 640 - 655 |
---|
621 | defparam gen_srls[41].srl_logic.INIT = `fpga_clk_out5_reg; // CYCLES 656 - 671 |
---|
622 | |
---|
623 | // OUT4 : See comments at the top of this file |
---|
624 | defparam gen_srls[42].srl_logic.INIT = 16'h0040; // CYCLES 672 - 687 |
---|
625 | defparam gen_srls[43].srl_logic.INIT = `fpga_clk_out4_reg; // CYCLES 688 - 703 |
---|
626 | |
---|
627 | // Latch the loaded values into the actual config registers |
---|
628 | // reg[5A] <= FF |
---|
629 | |
---|
630 | defparam gen_srls[44].srl_logic.INIT = 16'h005A; // CYCLES 704 - 719 |
---|
631 | defparam gen_srls[45].srl_logic.INIT = 16'hFFFF; // CYCLES 720 - 735 |
---|
632 | |
---|
633 | // unused cycles |
---|
634 | defparam gen_srls[46].srl_logic.INIT = 16'h0000; // CYCLES 736 - 751 |
---|
635 | defparam gen_srls[47].srl_logic.INIT = 16'h0000; // CYCLES 752 - 767 |
---|
636 | defparam gen_srls[48].srl_logic.INIT = 16'h0000; // CYCLES 768 - 783 |
---|
637 | defparam gen_srls[49].srl_logic.INIT = 16'h0000; // CYCLES 784 - 799 |
---|
638 | defparam gen_srls[50].srl_logic.INIT = 16'h0000; // CYCLES 800 - 815 |
---|
639 | defparam gen_srls[51].srl_logic.INIT = 16'h0000; // CYCLES 816 - 831 |
---|
640 | defparam gen_srls[52].srl_logic.INIT = 16'h0000; // CYCLES 832 - 847 |
---|
641 | defparam gen_srls[53].srl_logic.INIT = 16'h0000; // CYCLES 848 - 863 |
---|
642 | defparam gen_srls[54].srl_logic.INIT = 16'h0000; // CYCLES 864 - 879 |
---|
643 | defparam gen_srls[55].srl_logic.INIT = 16'h0000; // CYCLES 880 - 895 |
---|
644 | defparam gen_srls[56].srl_logic.INIT = 16'h0000; // CYCLES 896 - 911 |
---|
645 | defparam gen_srls[57].srl_logic.INIT = 16'h0000; // CYCLES 912 - 927 |
---|
646 | defparam gen_srls[58].srl_logic.INIT = 16'h0000; // CYCLES 928 - 943 |
---|
647 | defparam gen_srls[59].srl_logic.INIT = 16'h0000; // CYCLES 944 - 959 |
---|
648 | defparam gen_srls[60].srl_logic.INIT = 16'h0000; // CYCLES 960 - 975 |
---|
649 | defparam gen_srls[61].srl_logic.INIT = 16'h0000; // CYCLES 976 - 991 |
---|
650 | defparam gen_srls[62].srl_logic.INIT = 16'h0000; // CYCLES 992 - 1007 |
---|
651 | defparam gen_srls[63].srl_logic.INIT = 16'h0000; // CYCLES 1008 - 1023 |
---|
652 | |
---|
653 | `define LOGIC_CSB_LOW_DECODE ((cfg_cyc == 96) | (cfg_cyc == 128) | (cfg_cyc == 160) | (cfg_cyc == 192) | (cfg_cyc == 224) | (cfg_cyc == 256) | (cfg_cyc == 288) | (cfg_cyc == 320) | (cfg_cyc == 352) | (cfg_cyc == 384) | (cfg_cyc == 416) | (cfg_cyc == 448) | (cfg_cyc == 480) | (cfg_cyc == 512) | (cfg_cyc == 544) | (cfg_cyc == 576) | (cfg_cyc == 608) | (cfg_cyc == 640) | (cfg_cyc == 672) | (cfg_cyc == 704)) |
---|
654 | `define LOGIC_CSB_HIGH_DECODE ((cfg_cyc == 120) | (cfg_cyc == 152) | (cfg_cyc == 184) | (cfg_cyc == 216) | (cfg_cyc == 248) | (cfg_cyc == 280) | (cfg_cyc == 312) | (cfg_cyc == 344) | (cfg_cyc == 376) | (cfg_cyc == 408) | (cfg_cyc == 440) | (cfg_cyc == 472) | (cfg_cyc == 504) | (cfg_cyc == 536) | (cfg_cyc == 568) | (cfg_cyc == 600) | (cfg_cyc == 632) | (cfg_cyc == 664) | (cfg_cyc == 696) | (cfg_cyc == 728)) |
---|
655 | `define LOGIC_EN_LOW_DECODE (cfg_cyc == 0) |
---|
656 | `define LOGIC_EN_HIGH_DECODE (cfg_cyc == 4) |
---|
657 | |
---|
658 | // Decode various values of CFG_CYC to assert and deassert |
---|
659 | // control signals at various bit positions within the |
---|
660 | // configuration sequences. CFG_RADIO_CSB_LOW, for example, |
---|
661 | // should decode the value of CFG_CYC corresponding to the |
---|
662 | // first bit of an SCP command. CFG_RADIO_CSB_HIGH should |
---|
663 | // likewise decode the value corresponding to the first |
---|
664 | // bit FOLLOWING a streaming register access. |
---|
665 | |
---|
666 | reg cfg_radio_csb_low = 1'b0; |
---|
667 | reg cfg_radio_csb_high = 1'b0; |
---|
668 | reg cfg_radio_en_low = 1'b0; |
---|
669 | reg cfg_radio_en_high = 1'b0; |
---|
670 | |
---|
671 | reg cfg_logic_csb_low = 1'b0; |
---|
672 | reg cfg_logic_csb_high = 1'b0; |
---|
673 | reg cfg_logic_en_low = 1'b0; |
---|
674 | reg cfg_logic_en_high = 1'b0; |
---|
675 | |
---|
676 | always @ (posedge sys_clk) |
---|
677 | begin |
---|
678 | if (~scp_cyc_start) |
---|
679 | begin |
---|
680 | cfg_radio_csb_low <= 1'b0; |
---|
681 | cfg_radio_csb_high <= 1'b0; |
---|
682 | cfg_radio_en_low <= 1'b0; |
---|
683 | cfg_radio_en_high <= 1'b0; |
---|
684 | |
---|
685 | cfg_logic_csb_low <= 1'b0; |
---|
686 | cfg_logic_csb_high <= 1'b0; |
---|
687 | cfg_logic_en_low <= 1'b0; |
---|
688 | cfg_logic_en_high <= 1'b0; |
---|
689 | end |
---|
690 | |
---|
691 | else |
---|
692 | begin |
---|
693 | if (cfg_cyc_done) |
---|
694 | begin |
---|
695 | cfg_radio_csb_low <= 1'b0; |
---|
696 | cfg_radio_csb_high <= 1'b1; |
---|
697 | cfg_radio_en_low <= 1'b0; |
---|
698 | cfg_radio_en_high <= 1'b1; |
---|
699 | |
---|
700 | cfg_logic_csb_low <= 1'b0; |
---|
701 | cfg_logic_csb_high <= 1'b1; |
---|
702 | cfg_logic_en_low <= 1'b0; |
---|
703 | cfg_logic_en_high <= 1'b1; |
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704 | end |
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705 | else |
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706 | begin |
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707 | cfg_radio_csb_low <= `RADIO_CSB_LOW_DECODE; |
---|
708 | cfg_radio_csb_high <= `RADIO_CSB_HIGH_DECODE; |
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709 | cfg_radio_en_low <= `RADIO_EN_LOW_DECODE; |
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710 | cfg_radio_en_high <= `RADIO_EN_HIGH_DECODE; |
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711 | |
---|
712 | cfg_logic_csb_low <= `LOGIC_CSB_LOW_DECODE; |
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713 | cfg_logic_csb_high <= `LOGIC_CSB_HIGH_DECODE; |
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714 | cfg_logic_en_low <= `LOGIC_EN_LOW_DECODE; |
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715 | cfg_logic_en_high <= `LOGIC_EN_HIGH_DECODE; |
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716 | end |
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717 | |
---|
718 | end |
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719 | |
---|
720 | end |
---|
721 | |
---|
722 | |
---|
723 | |
---|
724 | always @ (posedge sys_clk) |
---|
725 | begin |
---|
726 | if (srl_shift) cfg_radio_dat_out <= srl_radio_q [0]; |
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727 | else cfg_radio_dat_out <= cfg_radio_dat_out; |
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728 | |
---|
729 | cfg_radio_csb_out <= cfg_radio_csb_out & ~cfg_radio_csb_low |
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730 | | ~cfg_radio_csb_out & cfg_radio_csb_high; |
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731 | cfg_radio_en_out <= cfg_radio_en_out & ~cfg_radio_en_low |
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732 | | ~cfg_radio_en_out & cfg_radio_en_high; |
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733 | cfg_radio_clk_out <= cfg_radio_clk_out & ~cfg_clk_low |
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734 | | ~cfg_radio_clk_out & cfg_clk_high; |
---|
735 | |
---|
736 | if (srl_shift) cfg_logic_dat_out <= srl_logic_q [0]; |
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737 | else cfg_logic_dat_out <= cfg_logic_dat_out; |
---|
738 | |
---|
739 | cfg_logic_csb_out <= cfg_logic_csb_out & ~cfg_logic_csb_low |
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740 | | ~cfg_logic_csb_out & cfg_logic_csb_high; |
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741 | cfg_logic_en_out <= cfg_logic_en_out & ~cfg_logic_en_low |
---|
742 | | ~cfg_logic_en_out & cfg_logic_en_high; |
---|
743 | cfg_logic_clk_out <= cfg_logic_clk_out & ~cfg_clk_low |
---|
744 | | ~cfg_logic_clk_out & cfg_clk_high; |
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745 | end |
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746 | |
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747 | endmodule |
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