[1166] | 1 | ################################################################### |
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| 2 | ## |
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| 3 | ## Name : eeprom |
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| 4 | ## Desc : Microprocessor Peripheral Description |
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| 5 | ## : Automatically generated by PsfUtility |
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| 6 | ## |
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| 7 | ################################################################### |
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| 8 | |
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| 9 | BEGIN eeprom |
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| 10 | |
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| 11 | ## Peripheral Options |
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| 12 | OPTION IPTYPE = PERIPHERAL |
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| 13 | OPTION IMP_NETLIST = TRUE |
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| 14 | OPTION HDL = MIXED |
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[1167] | 15 | OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE) |
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[1166] | 16 | OPTION IP_GROUP = MICROBLAZE:PPC:USER |
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| 17 | OPTION DESC = "EEPROM Controller based on Maxim OneWire Master core" |
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| 18 | OPTION USAGE_LEVEL = BASE_USER #Enable this core in base system builder |
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| 19 | |
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| 20 | IO_INTERFACE IO_IF = EEPROM, IO_TYPE = WARP_EEPROM_V1 |
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| 21 | |
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| 22 | ## Bus Interfaces |
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| 23 | BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46 |
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| 24 | |
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| 25 | ## Generics for VHDL or Parameters for Verilog |
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| 26 | PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT |
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| 27 | PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128) |
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| 28 | PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16) |
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| 29 | PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4) |
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| 30 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT |
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| 31 | PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1) |
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| 32 | PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT |
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| 33 | PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128) |
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| 34 | PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB |
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| 35 | PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1) |
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| 36 | PARAMETER C_FAMILY = virtex5, DT = STRING |
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| 37 | PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM0_HIGHADDR |
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| 38 | PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM0_BASEADDR |
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| 39 | |
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| 40 | ## Ports |
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| 41 | PORT DQ0 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ0_I, TRI_O = DQ0_O, TRI_T = DQ0_T |
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| 42 | PORT DQ0_T = "", DIR = O |
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| 43 | PORT DQ0_O = "", DIR = O |
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| 44 | PORT DQ0_I = "", DIR = I |
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| 45 | |
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| 46 | PORT DQ1 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ1_I, TRI_O = DQ1_O, TRI_T = DQ1_T |
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| 47 | PORT DQ1_T = "", DIR = O |
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| 48 | PORT DQ1_O = "", DIR = O |
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| 49 | PORT DQ1_I = "", DIR = I, INITIALVAL = VCC |
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| 50 | |
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| 51 | PORT DQ2 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ2_I, TRI_O = DQ2_O, TRI_T = DQ2_T |
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| 52 | PORT DQ2_T = "", DIR = O |
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| 53 | PORT DQ2_O = "", DIR = O |
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| 54 | PORT DQ2_I = "", DIR = I, INITIALVAL = VCC |
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| 55 | |
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| 56 | PORT DQ3 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ3_I, TRI_O = DQ3_O, TRI_T = DQ3_T |
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| 57 | PORT DQ3_T = "", DIR = O |
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| 58 | PORT DQ3_O = "", DIR = O |
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| 59 | PORT DQ3_I = "", DIR = I, INITIALVAL = VCC |
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| 60 | |
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| 61 | PORT DQ4 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ4_I, TRI_O = DQ4_O, TRI_T = DQ4_T |
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| 62 | PORT DQ4_T = "", DIR = O |
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| 63 | PORT DQ4_O = "", DIR = O |
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| 64 | PORT DQ4_I = "", DIR = I, INITIALVAL = VCC |
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| 65 | |
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| 66 | PORT DQ5 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ5_I, TRI_O = DQ5_O, TRI_T = DQ5_T |
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| 67 | PORT DQ5_T = "", DIR = O |
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| 68 | PORT DQ5_O = "", DIR = O |
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| 69 | PORT DQ5_I = "", DIR = I, INITIALVAL = VCC |
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| 70 | |
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| 71 | PORT DQ6 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ6_I, TRI_O = DQ6_O, TRI_T = DQ6_T |
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| 72 | PORT DQ6_T = "", DIR = O |
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| 73 | PORT DQ6_O = "", DIR = O |
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| 74 | PORT DQ6_I = "", DIR = I, INITIALVAL = VCC |
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| 75 | |
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| 76 | PORT DQ7 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ7_I, TRI_O = DQ7_O, TRI_T = DQ7_T |
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| 77 | PORT DQ7_T = "", DIR = O |
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| 78 | PORT DQ7_O = "", DIR = O |
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| 79 | PORT DQ7_I = "", DIR = I, INITIALVAL = VCC |
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| 80 | |
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| 81 | PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB |
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| 82 | PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB |
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| 83 | PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB |
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| 84 | PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB |
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| 85 | PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB |
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| 86 | PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB |
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| 87 | PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB |
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| 88 | PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB |
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| 89 | PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB |
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| 90 | PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB |
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| 91 | PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB |
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| 92 | PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB |
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| 93 | PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB |
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| 94 | PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB |
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| 95 | PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB |
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| 96 | PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB |
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| 97 | PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB |
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| 98 | PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB |
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| 99 | PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB |
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| 100 | PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB |
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| 101 | PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB |
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| 102 | PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB |
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| 103 | PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB |
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| 104 | PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB |
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| 105 | PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB |
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| 106 | PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB |
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| 107 | PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB |
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| 108 | PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB |
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| 109 | PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB |
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| 110 | PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB |
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| 111 | PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB |
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| 112 | PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB |
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| 113 | PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB |
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| 114 | PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB |
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| 115 | PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB |
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| 116 | PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB |
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| 117 | PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB |
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| 118 | PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB |
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| 119 | PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB |
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| 120 | PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB |
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| 121 | PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB |
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| 122 | PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB |
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| 123 | |
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| 124 | END |
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