[1166] | 1 | //-------------------------------------------------------------------------- |
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| 2 | // -- |
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| 3 | // OneWireMaster -- |
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| 4 | // A synthesizable 1-wire master peripheral -- |
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| 5 | // Copyright 1999-2005 Dallas Semiconductor Corporation -- |
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| 6 | // -- |
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| 7 | //-------------------------------------------------------------------------- |
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| 8 | // -- |
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| 9 | // Purpose: Provides timing and control of Dallas 1-wire bus -- |
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| 10 | // through a memory-mapped peripheral -- |
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| 11 | // File: OWM.v -- |
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| 12 | // Date: February 1, 2005 -- |
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| 13 | // Version: v2.100 -- |
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| 14 | // Authors: Rick Downs and Charles Hill, -- |
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| 15 | // Dallas Semiconductor Corporation -- |
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| 16 | // -- |
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| 17 | // Note: This source code is available for use without license. -- |
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| 18 | // Dallas Semiconductor is not responsible for the -- |
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| 19 | // functionality or utility of this product. -- |
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| 20 | // -- |
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| 21 | // Rev: Added Overdrive, Bit control, and strong pullup control -- |
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| 22 | // along with many other features described in the new spec -- |
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| 23 | // released version 2.0 9/5/01 - Greg Glennon -- |
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| 24 | // Significant changes to improve synthesis - English -- |
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| 25 | // Ported to Verilog - Sandelin -- |
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| 26 | //-------------------------------------------------------------------------- |
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| 27 | |
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| 28 | module OWM ( |
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| 29 | ADDRESS, ADS_bar, CLK, EN_bar, MR, RD_bar, WR_bar, /*DDIR, DOUT,*/ INTR, |
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| 30 | STPZ, DATA_IN, DATA_OUT, |
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| 31 | DQ0_T, DQ1_T, DQ2_T, DQ3_T, DQ4_T, DQ5_T, DQ6_T, DQ7_T, |
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| 32 | DQ0_O, DQ1_O, DQ2_O, DQ3_O, DQ4_O, DQ5_O, DQ6_O, DQ7_O, |
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| 33 | DQ0_I, DQ1_I, DQ2_I, DQ3_I, DQ4_I, DQ5_I, DQ6_I, DQ7_I); |
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| 34 | |
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| 35 | input [2:0] ADDRESS; // SFR address |
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| 36 | input ADS_bar; // address latch control (active low) |
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| 37 | input CLK; // system clock |
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| 38 | input EN_bar; // SFR access enable (active low) |
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| 39 | input MR; // master reset |
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| 40 | input RD_bar; // SFR read (active low) |
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| 41 | input WR_bar; // SFR write (active low) |
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| 42 | |
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| 43 | //output DDIR; |
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| 44 | //output [7:0] DOUT; |
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| 45 | output INTR; // one wire master interrupt |
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| 46 | output STPZ; // strong pullup (active low) |
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| 47 | |
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| 48 | input [7:0] DATA_IN; // input DATA bus |
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| 49 | output [7:0] DATA_OUT; // output DATA bus |
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| 50 | |
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| 51 | output DQ0_T; |
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| 52 | output DQ1_T; |
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| 53 | output DQ2_T; |
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| 54 | output DQ3_T; |
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| 55 | output DQ4_T; |
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| 56 | output DQ5_T; |
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| 57 | output DQ6_T; |
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| 58 | output DQ7_T; |
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| 59 | |
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| 60 | output DQ0_O; |
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| 61 | output DQ1_O; |
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| 62 | output DQ2_O; |
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| 63 | output DQ3_O; |
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| 64 | output DQ4_O; |
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| 65 | output DQ5_O; |
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| 66 | output DQ6_O; |
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| 67 | output DQ7_O; |
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| 68 | |
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| 69 | input DQ0_I; |
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| 70 | input DQ1_I; |
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| 71 | input DQ2_I; |
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| 72 | input DQ3_I; |
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| 73 | input DQ4_I; |
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| 74 | input DQ5_I; |
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| 75 | input DQ6_I; |
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| 76 | input DQ7_I; |
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| 77 | |
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| 78 | wire [2:0] dq_sel; |
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| 79 | |
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| 80 | wire [7:0] DIN; |
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| 81 | wire [7:0] DOUT; |
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| 82 | wire [7:0] rcvr_buffer; |
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| 83 | wire [7:0] xmit_buffer; |
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| 84 | wire [2:0] ADDRESS; |
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| 85 | wire clk_1us; |
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| 86 | |
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| 87 | one_wire_io xone_wire_io |
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| 88 | ( |
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| 89 | .CLK(CLK), |
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| 90 | .DDIR(DDIR), |
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| 91 | .DOUT(DOUT), |
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| 92 | .DQ_CONTROL(DQ_CONTROL), |
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| 93 | .MR(MR), |
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| 94 | .DIN(DIN), |
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| 95 | .DQ_IN(DQ_IN), |
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| 96 | .DATA_IN(DATA_IN), |
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| 97 | .DATA_OUT(DATA_OUT), |
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| 98 | .DQ0_T(DQ0_T), |
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| 99 | .DQ0_O(DQ0_O), |
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| 100 | .DQ0_I(DQ0_I), |
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| 101 | |
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| 102 | |
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| 103 | .DQ1_T(DQ1_T), |
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| 104 | .DQ1_O(DQ1_O), |
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| 105 | .DQ1_I(DQ1_I), |
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| 106 | |
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| 107 | |
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| 108 | .DQ2_T(DQ2_T), |
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| 109 | .DQ2_O(DQ2_O), |
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| 110 | .DQ2_I(DQ2_I), |
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| 111 | |
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| 112 | |
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| 113 | .DQ3_T(DQ3_T), |
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| 114 | .DQ3_O(DQ3_O), |
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| 115 | .DQ3_I(DQ3_I), |
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| 116 | |
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| 117 | |
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| 118 | .DQ4_T(DQ4_T), |
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| 119 | .DQ4_O(DQ4_O), |
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| 120 | .DQ4_I(DQ4_I), |
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| 121 | |
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| 122 | |
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| 123 | .DQ5_T(DQ5_T), |
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| 124 | .DQ5_O(DQ5_O), |
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| 125 | .DQ5_I(DQ5_I), |
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| 126 | |
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| 127 | |
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| 128 | .DQ6_T(DQ6_T), |
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| 129 | .DQ6_O(DQ6_O), |
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| 130 | .DQ6_I(DQ6_I), |
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| 131 | |
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| 132 | |
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| 133 | .DQ7_T(DQ7_T), |
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| 134 | .DQ7_O(DQ7_O), |
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| 135 | .DQ7_I(DQ7_I), |
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| 136 | |
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| 137 | |
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| 138 | .DQ_SEL(dq_sel) |
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| 139 | ); |
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| 140 | |
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| 141 | clk_prescaler xclk_prescaler |
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| 142 | ( |
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| 143 | .CLK(CLK), |
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| 144 | .CLK_EN(CLK_EN), |
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| 145 | .div_1(div_1), |
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| 146 | .div_2(div_2), |
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| 147 | .div_3(div_3), |
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| 148 | .MR(MR), |
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| 149 | .pre_0(pre_0), |
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| 150 | .pre_1(pre_1), |
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| 151 | .clk_1us(clk_1us) |
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| 152 | ); |
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| 153 | |
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| 154 | one_wire_interface xone_wire_interface |
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| 155 | ( |
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| 156 | .ADDRESS(ADDRESS), |
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| 157 | .ADS_bar(ADS_bar), |
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| 158 | .clear_interrupts(clear_interrupts), |
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| 159 | .DIN(DIN), |
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| 160 | .DQ_IN(DQ_IN), |
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| 161 | .EN_bar(EN_bar), |
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| 162 | .FSM_CLK(FSM_CLK), |
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| 163 | .MR(MR), |
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| 164 | .OneWireIO_eq_Load(OneWireIO_eq_Load), |
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| 165 | .pdr(pdr), |
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| 166 | .OW_LOW(OW_LOW), |
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| 167 | .OW_SHORT(OW_SHORT), |
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| 168 | .rbf(rbf), |
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| 169 | .rcvr_buffer(rcvr_buffer), |
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| 170 | .RD_bar(RD_bar), |
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| 171 | .reset_owr(reset_owr), |
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| 172 | .rsrf(rsrf), |
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| 173 | .temt(temt), |
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| 174 | .WR_bar(WR_bar), |
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| 175 | .BIT_CTL(BIT_CTL), |
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| 176 | .CLK_EN(CLK_EN), |
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| 177 | .clr_activate_intr(clr_activate_intr), |
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| 178 | .DDIR(DDIR), |
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| 179 | .div_1(div_1), |
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| 180 | .div_2(div_2), |
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| 181 | .div_3(div_3), |
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| 182 | .DOUT(DOUT), |
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| 183 | .EN_FOW(EN_FOW), |
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| 184 | .EOWL(EOWL), |
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| 185 | .EOWSH(EOWSH), |
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| 186 | .epd(epd), |
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| 187 | .erbf(erbf), |
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| 188 | .ersf(ersf), |
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| 189 | .etbe(etbe), |
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| 190 | .etmt(etmt), |
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| 191 | .FOW(FOW), |
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| 192 | .ias(ias), |
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| 193 | .LLM(LLM), |
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| 194 | .OD(OD), |
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| 195 | .owr(owr), |
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| 196 | .pd(pd), |
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| 197 | .PPM(PPM), |
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| 198 | .pre_0(pre_0), |
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| 199 | .pre_1(pre_1), |
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| 200 | .rbf_reset(rbf_reset), |
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| 201 | .sr_a(sr_a), |
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| 202 | .STP_SPLY(STP_SPLY), |
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| 203 | .STPEN(STPEN), |
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| 204 | .tbe(tbe), |
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| 205 | .xmit_buffer(xmit_buffer), |
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| 206 | .dq_sel(dq_sel) |
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| 207 | ); |
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| 208 | |
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| 209 | onewiremaster xonewiremaster( |
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| 210 | .BIT_CTL(BIT_CTL), |
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| 211 | .clk(CLK), |
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| 212 | .clk_1us_en(clk_1us), |
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| 213 | .clr_activate_intr(clr_activate_intr), |
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| 214 | .DQ_IN(DQ_IN), |
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| 215 | .EN_FOW(EN_FOW), |
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| 216 | .EOWL(EOWL), |
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| 217 | .EOWSH(EOWSH), |
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| 218 | .epd(epd), |
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| 219 | .erbf(erbf), |
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| 220 | .ersf(ersf), |
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| 221 | .etbe(etbe), |
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| 222 | .etmt(etmt), |
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| 223 | .FOW(FOW), |
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| 224 | .ias(ias), |
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| 225 | .LLM(LLM), |
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| 226 | .MR(MR), |
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| 227 | .OD(OD), |
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| 228 | .owr(owr), |
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| 229 | .pd(pd), |
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| 230 | .PPM(PPM), |
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| 231 | .rbf_reset(rbf_reset), |
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| 232 | .sr_a(sr_a), |
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| 233 | .STP_SPLY(STP_SPLY), |
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| 234 | .STPEN(STPEN), |
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| 235 | .tbe(tbe), |
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| 236 | .xmit_buffer(xmit_buffer), |
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| 237 | .clear_interrupts(clear_interrupts), |
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| 238 | .DQ_CONTROL(DQ_CONTROL), |
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| 239 | .FSM_CLK(FSM_CLK), |
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| 240 | .INTR(INTR), |
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| 241 | .OneWireIO_eq_Load(OneWireIO_eq_Load), |
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| 242 | .OW_LOW(OW_LOW), |
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| 243 | .OW_SHORT(OW_SHORT), |
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| 244 | .pdr(pdr), |
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| 245 | .rbf(rbf), |
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| 246 | .rcvr_buffer(rcvr_buffer), |
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| 247 | .reset_owr(reset_owr), |
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| 248 | .rsrf(rsrf), |
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| 249 | .STPZ(STPZ), |
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| 250 | .temt(temt) |
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| 251 | ); |
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| 252 | |
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| 253 | |
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| 254 | //synthesis attribute clock_signal of clk_1us IS no |
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| 255 | |
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| 256 | //synthesis attribute buffer_type of clk_1us IS none |
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| 257 | |
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| 258 | |
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| 259 | endmodule |
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