[1166] | 1 | //-------------------------------------------------------------------------- |
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| 2 | // -- |
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| 3 | // OneWireMaster -- |
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| 4 | // A synthesizable 1-wire master peripheral -- |
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| 5 | // Copyright 1999-2005 Dallas Semiconductor Corporation -- |
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| 6 | // -- |
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| 7 | //-------------------------------------------------------------------------- |
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| 8 | // -- |
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| 9 | // Purpose: Provides timing and control of Dallas 1-wire bus -- |
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| 10 | // through a memory-mapped peripheral -- |
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| 11 | // File: clk_prescaler.v -- |
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| 12 | // Date: February 1, 2005 -- |
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| 13 | // Version: v2.100 -- |
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| 14 | // Authors: Rick Downs and Charles Hill, -- |
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| 15 | // Dallas Semiconductor Corporation -- |
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| 16 | // -- |
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| 17 | // Note: This source code is available for use without license. -- |
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| 18 | // Dallas Semiconductor is not responsible for the -- |
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| 19 | // functionality or utility of this product. -- |
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| 20 | // -- |
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| 21 | // REV: Significant changes to improve synthesis - English -- |
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| 22 | // Ported to Verilog - Sandelin -- |
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| 23 | //-------------------------------------------------------------------------- |
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| 24 | |
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| 25 | module clk_prescaler( |
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| 26 | CLK, CLK_EN, div_1, div_2, div_3, MR, pre_0, pre_1, clk_1us); |
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| 27 | |
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| 28 | input CLK; |
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| 29 | input CLK_EN; // enables the divide chain |
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| 30 | input div_1; // divider select bit 1 |
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| 31 | input div_2; // divider select bit 2 |
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| 32 | input div_3; // divider select bit 3 |
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| 33 | input MR; |
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| 34 | input pre_0; // prescaler select bit 0 |
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| 35 | input pre_1; // prescaler select bit 1 |
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| 36 | |
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| 37 | output clk_1us; // OD, STD mode fsm clock |
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| 38 | |
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| 39 | wire CLK; |
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| 40 | wire MR; |
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| 41 | wire pre_0; |
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| 42 | wire pre_1; |
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| 43 | wire div_1; |
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| 44 | wire div_2; |
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| 45 | wire div_3; |
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| 46 | |
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| 47 | wire clk_prescaled; // prescaled clock output |
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| 48 | // reg clk_1us; // 1us timebase for 1-wire STD and OD trans |
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| 49 | wire clk_1us; // 1us timebase for 1-wire STD and OD trans |
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| 50 | reg clk_div; // divided clk for hdrive |
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| 51 | reg en_div; // enable use of divided clk for hdrive |
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| 52 | reg clk_prescaled_reg; |
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| 53 | reg [6:0] div_cnt; |
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| 54 | reg [2:0] ClkPrescale; |
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| 55 | |
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| 56 | parameter [2:0] s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, |
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| 57 | s5=3'b101, s6=3'b110; |
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| 58 | |
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| 59 | |
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| 60 | //-------------------------------------------------------------------------- |
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| 61 | // Clock Prescaler |
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| 62 | //-------------------------------------------------------------------------- |
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| 63 | wire rst_clk = MR || !CLK_EN; |
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| 64 | |
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| 65 | always @(posedge rst_clk or posedge CLK) |
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| 66 | if(rst_clk) |
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| 67 | ClkPrescale <= s0; |
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| 68 | else |
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| 69 | case(ClkPrescale) |
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| 70 | s0: ClkPrescale <= s1; |
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| 71 | |
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| 72 | s1: ClkPrescale <= s2; |
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| 73 | |
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| 74 | s2: if(pre_0 && !pre_1) |
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| 75 | ClkPrescale <= s0; |
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| 76 | else |
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| 77 | ClkPrescale <= s3; |
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| 78 | |
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| 79 | s3: ClkPrescale <= s4; |
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| 80 | |
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| 81 | s4: if(!pre_0 && pre_1) |
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| 82 | ClkPrescale <= s0; |
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| 83 | else |
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| 84 | ClkPrescale <= s5; |
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| 85 | |
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| 86 | s5: ClkPrescale <= s6; |
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| 87 | |
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| 88 | s6: ClkPrescale <= s0; |
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| 89 | |
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| 90 | default: ClkPrescale<=s0; |
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| 91 | endcase |
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| 92 | |
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| 93 | reg en_clk; |
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| 94 | |
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| 95 | // |
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| 96 | // Create prescaled clock |
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| 97 | // |
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| 98 | always @(posedge MR or posedge CLK) |
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| 99 | if (MR) |
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| 100 | clk_prescaled_reg<=1; |
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| 101 | else |
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| 102 | clk_prescaled_reg <= (!ClkPrescale[0] && !ClkPrescale[1] |
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| 103 | && !ClkPrescale[2]); |
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| 104 | |
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| 105 | //assign clk_prescaled = (!pre_0 && !pre_1 && CLK_EN)?CLK:clk_prescaled_reg; |
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| 106 | |
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| 107 | always @(posedge MR or negedge CLK) |
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| 108 | if (MR) |
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| 109 | en_clk <= 1'b1; |
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| 110 | else |
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| 111 | en_clk <= CLK_EN && ((!pre_0 && !pre_1) || (ClkPrescale[2:0] == 3'b000)); |
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| 112 | |
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| 113 | assign clk_prescaled = en_clk & CLK; |
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| 114 | |
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| 115 | //-------------------------------------------------------------------------- |
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| 116 | // Clock Divider |
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| 117 | // using clk_prescaled as its input, this divide-by-2 chain does the |
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| 118 | // other clock division |
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| 119 | //-------------------------------------------------------------------------- |
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| 120 | always @(posedge MR or posedge CLK) |
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| 121 | if (MR) |
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| 122 | div_cnt <= 7'h00; |
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| 123 | else if (en_clk) |
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| 124 | div_cnt <= div_cnt + 1; |
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| 125 | |
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| 126 | reg clk_1us_en; |
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| 127 | |
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| 128 | always @(posedge MR or negedge CLK) |
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| 129 | if (MR) |
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| 130 | clk_1us_en <= 1'b1; |
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| 131 | else |
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| 132 | case ({div_3, div_2, div_1}) |
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| 133 | 3'b000 : clk_1us_en <= CLK_EN; |
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| 134 | 3'b001 : clk_1us_en <= ~div_cnt[0]; |
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| 135 | 3'b010 : clk_1us_en <= (div_cnt[1:0] == 2'h1); |
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| 136 | 3'b011 : clk_1us_en <= (div_cnt[2:0] == 3'h3); |
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| 137 | 3'b100 : clk_1us_en <= (div_cnt[3:0] == 4'h7); |
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| 138 | 3'b101 : clk_1us_en <= (div_cnt[4:0] == 5'h0f); |
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| 139 | 3'b110 : clk_1us_en <= (div_cnt[5:0] == 6'h1f); |
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| 140 | 3'b111 : clk_1us_en <= (div_cnt[6:0] == 7'h3f); |
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| 141 | endcase |
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| 142 | |
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| 143 | reg clk_1us_en_d1; |
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| 144 | |
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| 145 | // always @(clk_1us_en or en_clk or CLK) |
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| 146 | // assign clk_1us_gen <= clk_1us_en && en_clk && CLK; |
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| 147 | |
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| 148 | //negedge CLK to match clk_1us_en procedure above |
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| 149 | always @(negedge CLK) |
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| 150 | if(!en_clk) |
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| 151 | clk_1us_en_d1 <= 1'b0; |
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| 152 | else |
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| 153 | clk_1us_en_d1 <= clk_1us_en; |
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| 154 | |
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| 155 | |
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| 156 | //Pulse generator - only stays high 1 CLK cycle |
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| 157 | assign clk_1us = (!clk_1us_en_d1 && clk_1us_en); |
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| 158 | |
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| 159 | endmodule // clk_prescaler |
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