[1166] | 1 | //-------------------------------------------------------------------------- |
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| 2 | // -- |
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| 3 | // OneWireMaster -- |
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| 4 | // A synthesizable 1-wire master peripheral -- |
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| 5 | // Copyright 1999-2005 Dallas Semiconductor Corporation -- |
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| 6 | // -- |
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| 7 | //-------------------------------------------------------------------------- |
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| 8 | // -- |
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| 9 | // Purpose: Provides timing and control of Dallas 1-wire bus -- |
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| 10 | // through a memory-mapped peripheral -- |
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| 11 | // File: one_wire_interface.v -- |
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| 12 | // Date: February 1, 2005 -- |
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| 13 | // Version: v2.100 -- |
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| 14 | // Authors: Rick Downs and Charles Hill, -- |
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| 15 | // Dallas Semiconductor Corporation -- |
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| 16 | // -- |
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| 17 | // Note: This source code is available for use without license. -- |
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| 18 | // Dallas Semiconductor is not responsible for the -- |
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| 19 | // functionality or utility of this product. -- |
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| 20 | // -- |
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| 21 | // REV: Added BIT_CTL to COMMAND reg - GAG -- |
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| 22 | // Added STPEN to COMMAND reg - GAG -- |
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| 23 | // Combined CLK_DIV register bits into one block - GAG -- |
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| 24 | // Added CLK_EN to CLK_DIV reg - GAG -- |
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| 25 | // Added CONTROL reg and moved appropriate bits into it - GAG -- |
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| 26 | // Added EN_FOW and changed dqz to FOW - GAG -- |
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| 27 | // Added STP_SPLY - GAG -- |
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| 28 | // Significant changes to improve synthesis - English -- |
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| 29 | // Ported to Verilog - Sandelin -- |
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| 30 | //-------------------------------------------------------------------------- |
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| 31 | |
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| 32 | module one_wire_interface ( |
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| 33 | ADDRESS, ADS_bar, clear_interrupts, DIN, DQ_IN, EN_bar, FSM_CLK, MR, |
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| 34 | OneWireIO_eq_Load, pdr, OW_LOW, OW_SHORT, rbf, |
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| 35 | rcvr_buffer, RD_bar, reset_owr, rsrf, temt, WR_bar, BIT_CTL, |
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| 36 | CLK_EN, clr_activate_intr, DDIR, div_1, div_2, div_3, DOUT, EN_FOW, EOWL, |
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| 37 | EOWSH, epd, erbf, ersf, etbe, etmt, FOW, ias, |
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| 38 | LLM, OD, owr, pd, PPM, pre_0, pre_1, rbf_reset, sr_a, STP_SPLY, STPEN, tbe, |
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| 39 | xmit_buffer,dq_sel); |
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| 40 | |
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| 41 | input [2:0] ADDRESS; |
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| 42 | input ADS_bar; |
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| 43 | input clear_interrupts; |
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| 44 | input [7:0] DIN; |
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| 45 | input DQ_IN; |
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| 46 | input EN_bar; |
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| 47 | input FSM_CLK; |
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| 48 | input MR; |
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| 49 | input OneWireIO_eq_Load; |
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| 50 | input pdr; |
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| 51 | input OW_LOW; // ow bus low interrupt |
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| 52 | input OW_SHORT; // ow bus shorted interrupt |
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| 53 | input rbf; // receive buffer full int |
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| 54 | input [7:0] rcvr_buffer; |
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| 55 | input RD_bar; |
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| 56 | input reset_owr; |
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| 57 | input rsrf; // receive shift reg full int |
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| 58 | input temt; |
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| 59 | input WR_bar; |
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| 60 | |
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| 61 | output BIT_CTL; // enable signle bit outputs |
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| 62 | output CLK_EN; // clock divider enable |
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| 63 | output clr_activate_intr; |
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| 64 | output DDIR; |
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| 65 | output div_1; // divider select bit 1 |
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| 66 | output div_2; // divider select bit 2 |
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| 67 | output div_3; // divider select bit 3 |
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| 68 | output [7:0] DOUT; |
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| 69 | output EN_FOW; // enable force OW functionality |
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| 70 | output EOWL; // enable one wire bus low interrupt |
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| 71 | output EOWSH; // enable one wire short interrupt |
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| 72 | output epd; // enable presence detect interrupt |
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| 73 | output erbf; // enable receive buffer full interrupt |
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| 74 | output ersf; // enable receive shift register full int. |
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| 75 | output etbe; // enable transmit buffer empty interrupt |
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| 76 | output etmt; // enable transmit shift outputister empty int. |
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| 77 | output FOW; // force OW value to opposite value |
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| 78 | output ias; // INTR active state |
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| 79 | output LLM; // long line mode enable |
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| 80 | output OD; // enable overdrive |
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| 81 | output owr; |
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| 82 | output pd; |
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| 83 | output PPM; // presence pulse masking enable |
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| 84 | output pre_0; // prescaler select bit 0 |
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| 85 | output pre_1; // prescaler select bit 1 |
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| 86 | output rbf_reset; // clear signal for rbf |
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| 87 | output sr_a; |
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| 88 | output STP_SPLY; // enable strong pull up supply mode |
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| 89 | output STPEN; // enable strong pull up output |
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| 90 | output tbe; |
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| 91 | output [7:0] xmit_buffer; |
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| 92 | output [2:0] dq_sel; |
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| 93 | reg [2:0] dq_sel; |
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| 94 | |
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| 95 | |
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| 96 | wire read_op; |
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| 97 | wire write_op; |
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| 98 | reg [2:0] sel_addr; // selected register address |
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| 99 | |
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| 100 | // command register |
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| 101 | reg sr_a; // search ROM accelerator command |
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| 102 | reg owr; // 1W reset command |
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| 103 | reg FOW; // Force OW value |
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| 104 | wire [7:0] CMD_REG = {4'b0, DQ_IN, FOW, sr_a, owr}; |
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| 105 | |
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| 106 | reg set_activate_intr; |
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| 107 | reg clr_activate_intr; |
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| 108 | reg xmit_buffer_full; |
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| 109 | |
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| 110 | reg [7:0] xmit_buffer; // transmit buffer |
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| 111 | |
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| 112 | // Control register |
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| 113 | reg OD; // enable overdrive |
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| 114 | reg BIT_CTL; // enable single bit transmitions |
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| 115 | reg STP_SPLY; // Strong Pullup supply mode enable |
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| 116 | reg STPEN; // enable strong pull up output |
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| 117 | reg EN_FOW; // enable force OW functionality |
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| 118 | reg PPM; // Presence Pulse masking enable |
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| 119 | reg LLM; // Long Line mode enable (stretch timing) |
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| 120 | wire [7:0] CONTRL_REG = {1'b0, OD, BIT_CTL, STP_SPLY, STPEN, EN_FOW, |
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| 121 | PPM, LLM}; |
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| 122 | |
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| 123 | // interrupt register |
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| 124 | wire OW_LOW; // OW low interrupt |
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| 125 | wire OW_SHORT; // OW shorted interrupt |
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| 126 | reg pd; // presence detect done flag |
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| 127 | wire pdr; // presence detect result |
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| 128 | reg tbe; // transmit buffer empty flag |
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| 129 | wire rbf; // receive buffer full flag |
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| 130 | wire [7:0] INT_REG = {OW_LOW, OW_SHORT, rsrf, rbf, temt, tbe, pdr, pd}; |
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| 131 | |
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| 132 | // interrupt enable register |
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| 133 | reg EOWL; // enable OW low interrupt |
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| 134 | reg EOWSH; // enable OW shorted interrupt |
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| 135 | reg epd; // enable presence detect interrupt |
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| 136 | reg ias; // INTR active state |
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| 137 | reg etbe; // enable transmit buffer empty interrupt |
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| 138 | reg etmt; // enable transmit shift register empty int. |
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| 139 | reg erbf; // enable receive buffer full interrupt |
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| 140 | reg ersf; // enable receive shift register full int. |
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| 141 | wire [7:0] INTEN_REG = {EOWL, EOWSH, ersf, erbf, etmt, etbe, ias, epd}; |
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| 142 | |
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| 143 | // clock divisor register |
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| 144 | reg pre_0; // prescaler select bit 0 |
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| 145 | reg pre_1; // prescaler select bit 1 |
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| 146 | reg div_1; // divider select bit 1 |
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| 147 | reg div_2; // divider select bit 2 |
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| 148 | reg div_3; // divider select bit 3 |
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| 149 | reg CLK_EN; // clock divider enable |
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| 150 | wire [7:0] CLKDV_REG = {CLK_EN, 2'b0, div_3, div_2, div_1, pre_1, pre_0}; |
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| 151 | |
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| 152 | |
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| 153 | |
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| 154 | //-------------------------------------------------------------------------- |
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| 155 | // read/write process |
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| 156 | //-------------------------------------------------------------------------- |
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| 157 | |
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| 158 | assign read_op = ~EN_bar && ~MR && ~RD_bar && WR_bar; |
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| 159 | wire read_op_n=~read_op; |
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| 160 | |
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| 161 | assign write_op = ~EN_bar && ~MR && ~WR_bar && RD_bar; |
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| 162 | wire write_op_n = ~write_op; |
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| 163 | |
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| 164 | always @(posedge MR or posedge WR_bar) |
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| 165 | if(MR) // removed reset interrupt reg when chip not enabled |
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| 166 | begin |
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| 167 | EOWL = 1'b0; |
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| 168 | EOWSH = 1'b0; |
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| 169 | ersf = 1'b0; |
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| 170 | erbf = 1'b0; |
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| 171 | etmt = 1'b0; |
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| 172 | etbe = 1'b0; |
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| 173 | ias = 1'b0; |
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| 174 | epd = 1'b0; |
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| 175 | xmit_buffer=0; |
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| 176 | end |
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| 177 | else |
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| 178 | if(!EN_bar && RD_bar) |
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| 179 | case(sel_addr) |
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| 180 | 3'b001: |
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| 181 | xmit_buffer = DIN; |
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| 182 | 3'b011: //removed ias to hard wire active low - GAG |
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| 183 | //added ias to remove hardwire - SKH |
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| 184 | begin |
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| 185 | EOWL = DIN[7]; |
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| 186 | EOWSH = DIN[6]; |
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| 187 | ersf = DIN[5]; |
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| 188 | erbf = DIN[4]; |
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| 189 | etmt = DIN[3]; |
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| 190 | etbe = DIN[2]; |
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| 191 | ias = DIN[1]; |
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| 192 | epd = DIN[0]; |
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| 193 | end |
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| 194 | endcase |
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| 195 | |
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| 196 | assign DDIR = read_op; |
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| 197 | |
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| 198 | // |
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| 199 | // Modified DOUT to always drive the current register value out |
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| 200 | // based on the address value |
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| 201 | // |
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| 202 | assign DOUT = |
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| 203 | (sel_addr == 3'b000)?{1'b0,dq_sel [2:0],DQ_IN,FOW,sr_a,owr}: |
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| 204 | (sel_addr == 3'b001)?rcvr_buffer: |
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| 205 | (sel_addr == 3'b010)?{OW_LOW,OW_SHORT,rsrf,rbf,temt,tbe,pdr,pd}: |
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| 206 | (sel_addr == 3'b011)?{EOWL,EOWSH,ersf,erbf,etmt,etbe,ias,epd}: |
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| 207 | (sel_addr == 3'b100)?{CLK_EN,2'b00,div_3,div_2,div_1,pre_1,pre_0}: |
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| 208 | (sel_addr == 3'b101)?{1'b0,OD,BIT_CTL,STP_SPLY,STPEN,EN_FOW,PPM,LLM}: |
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| 209 | 8'h00; |
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| 210 | |
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| 211 | |
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| 212 | // |
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| 213 | // Clock divisor register |
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| 214 | // |
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| 215 | // synopsys async_set_reset MR |
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| 216 | always @(posedge MR or posedge WR_bar) |
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| 217 | if(MR) |
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| 218 | begin |
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| 219 | pre_0 = 1'b0; |
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| 220 | pre_1 = 1'b0; |
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| 221 | div_1 = 1'b0; |
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| 222 | div_2 = 1'b0; |
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| 223 | div_3 = 1'b0; |
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| 224 | CLK_EN = 1'b0; |
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| 225 | end |
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| 226 | else |
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| 227 | if(!EN_bar && RD_bar) |
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| 228 | if(sel_addr == 3'b100) |
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| 229 | begin |
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| 230 | pre_0 = DIN[0]; |
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| 231 | pre_1 = DIN[1]; |
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| 232 | div_1 = DIN[2]; |
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| 233 | div_2 = DIN[3]; |
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| 234 | div_3 = DIN[4]; |
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| 235 | CLK_EN = DIN[7]; |
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| 236 | end |
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| 237 | |
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| 238 | |
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| 239 | wire CLR_OWR = MR || reset_owr; |
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| 240 | |
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| 241 | // |
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| 242 | // Command reg writes are handled in the next two sections |
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| 243 | // Bit 0 needs to be separate for the added clearing mechanism |
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| 244 | // |
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| 245 | always @(posedge CLR_OWR or posedge WR_bar) |
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| 246 | if(CLR_OWR) |
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| 247 | begin |
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| 248 | owr <= 1'b0; |
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| 249 | end |
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| 250 | else |
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| 251 | begin |
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| 252 | if(EN_bar == 0 && RD_bar == 1) |
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| 253 | if(sel_addr == 3'b000) |
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| 254 | owr <= DIN[0]; |
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| 255 | end |
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| 256 | // |
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| 257 | // Bits 1-7's write routine |
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| 258 | // |
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| 259 | always @(posedge MR or posedge WR_bar) |
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| 260 | if(MR) |
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| 261 | begin |
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| 262 | FOW <= 1'b0; |
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| 263 | sr_a <= 1'b0; |
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| 264 | dq_sel [2:0] <= 3'b000; |
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| 265 | end |
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| 266 | else |
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| 267 | begin |
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| 268 | if(EN_bar == 0 && RD_bar == 1) |
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| 269 | if(sel_addr == 3'b000) |
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| 270 | begin |
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| 271 | sr_a <= DIN[1]; |
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| 272 | FOW <= DIN[2]; |
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| 273 | dq_sel [2:0] <= DIN[6:4]; |
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| 274 | end |
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| 275 | end |
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| 276 | |
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| 277 | // |
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| 278 | // The Control reg writes are handled here |
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| 279 | // |
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| 280 | always @(posedge MR or posedge WR_bar) |
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| 281 | if(MR) |
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| 282 | begin |
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| 283 | OD <= 1'b0; |
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| 284 | BIT_CTL <= 1'b0; |
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| 285 | STP_SPLY<= 1'b0; |
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| 286 | STPEN <= 1'b0; |
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| 287 | EN_FOW <= 1'b0; |
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| 288 | PPM <= 1'b0; |
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| 289 | LLM <= 1'b0; |
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| 290 | end |
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| 291 | else |
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| 292 | begin |
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| 293 | if(EN_bar == 0 && RD_bar == 1) |
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| 294 | if(sel_addr == 3'b101) |
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| 295 | begin |
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| 296 | OD <= DIN[6]; |
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| 297 | BIT_CTL <= DIN[5]; |
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| 298 | STP_SPLY<= DIN[4]; |
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| 299 | STPEN <= DIN[3]; |
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| 300 | EN_FOW <= DIN[2]; |
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| 301 | PPM <= DIN[1]; |
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| 302 | LLM <= DIN[0]; |
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| 303 | end |
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| 304 | end |
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| 305 | |
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| 306 | |
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| 307 | //-------------------------------------------------------------------------- |
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| 308 | // Transparent address latch |
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| 309 | //-------------------------------------------------------------------------- |
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| 310 | |
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| 311 | always @(ADS_bar or ADDRESS or EN_bar) |
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| 312 | if(!ADS_bar && !EN_bar) |
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| 313 | sel_addr = ADDRESS; |
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| 314 | |
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| 315 | //-------------------------------------------------------------------------- |
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| 316 | // Interrupt flag register clearing (What is not handled in onewiremaster.v) |
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| 317 | //-------------------------------------------------------------------------- |
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| 318 | |
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| 319 | wire acint_reset = MR || (clear_interrupts); // synchronized |
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| 320 | // set_activate_intr - SDS |
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| 321 | |
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| 322 | always @(posedge acint_reset or posedge RD_bar) |
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| 323 | if(acint_reset) |
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| 324 | clr_activate_intr <= 1'b0; |
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| 325 | else |
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| 326 | if(EN_bar == 0 && WR_bar == 1) |
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| 327 | if(sel_addr == 3'b010) |
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| 328 | clr_activate_intr <= 1'b1; |
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| 329 | |
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| 330 | wire rbf_reset = (read_op && (sel_addr == 3'b001)); |
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| 331 | |
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| 332 | always @(posedge MR or posedge FSM_CLK) |
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| 333 | if (MR) |
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| 334 | pd <= 1'b0; |
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| 335 | else if (reset_owr) |
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| 336 | pd <= 1'b1; |
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| 337 | else if (clr_activate_intr) // This causes pd to wait for a clk to clear |
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| 338 | pd <= 1'b0; |
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| 339 | else |
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| 340 | pd <= pd; |
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| 341 | |
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| 342 | // |
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| 343 | // The following two blocks handle tbe |
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| 344 | // The lower is the psuedo asynch portion which is synched up |
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| 345 | // in the upper section. |
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| 346 | // |
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| 347 | always @(posedge FSM_CLK or posedge MR) |
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| 348 | if (MR) |
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| 349 | tbe <= 1'b1; |
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| 350 | else |
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| 351 | tbe <= ~xmit_buffer_full; |
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| 352 | |
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| 353 | always @(posedge MR or posedge WR_bar or posedge OneWireIO_eq_Load) |
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| 354 | if(MR) |
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| 355 | xmit_buffer_full <= 1'b0; |
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| 356 | else if (OneWireIO_eq_Load) |
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| 357 | xmit_buffer_full <= 1'b0; |
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| 358 | else |
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| 359 | if(EN_bar == 0 && RD_bar == 1) |
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| 360 | if(sel_addr == 3'b001) |
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| 361 | xmit_buffer_full <= 1'b1; |
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| 362 | |
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| 363 | endmodule // one_wire_interface |
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| 364 | |
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