[1166] | 1 | //-------------------------------------------------------------------------- |
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| 2 | // -- |
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| 3 | // OneWireMaster -- |
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| 4 | // A synthesizable 1-wire master peripheral -- |
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| 5 | // Copyright 1999-2005 Dallas Semiconductor Corporation -- |
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| 6 | // -- |
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| 7 | //-------------------------------------------------------------------------- |
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| 8 | // -- |
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| 9 | // Purpose: Provides timing and control of Dallas 1-wire bus -- |
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| 10 | // through a memory-mapped peripheral -- |
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| 11 | // File: OneWireMaster.v -- |
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| 12 | // Date: February 1, 2005 -- |
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| 13 | // Version: v2.100 -- |
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| 14 | // Authors: Rick Downs and Charles Hill, -- |
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| 15 | // Dallas Semiconductor Corporation -- |
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| 16 | // -- |
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| 17 | // Note: This source code is available for use without license. -- |
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| 18 | // Dallas Semiconductor is not responsible for the -- |
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| 19 | // functionality or utility of this product. -- |
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| 20 | // -- |
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| 21 | // REV: Updated 1-Wire timings to match App Note 126 - SKH -- |
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| 22 | // Added in Async MR of DQ_CONTROL - GAG -- |
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| 23 | // Changed WriteZero TimeSlotCnt to 60 instead of only 30 to -- |
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| 24 | // match OneWire Spec. - GAG -- |
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| 25 | // Added in bit control mode, left dqz for other function - GAG-- |
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| 26 | // Added strong pullup enable signal - GAG -- |
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| 27 | // Modified pd so it will not fire until the entire PD routine -- |
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| 28 | // has completed - GAG -- |
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| 29 | // Added OW_LOW interrupt and OW_SHORT interrupt - GAG -- |
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| 30 | // Added PPM and LLM for long line situations - GAG -- |
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| 31 | // Changed logic for rsrf and rbf int flags - GAG -- |
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| 32 | // Significant changes to improve synthesis - English -- |
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| 33 | // Ported to Verilog - Sandelin -- |
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| 34 | //-------------------------------------------------------------------------- |
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| 35 | |
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| 36 | module onewiremaster ( |
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| 37 | BIT_CTL, clk, clk_1us_en, clr_activate_intr, DQ_IN, EN_FOW, EOWL, |
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| 38 | EOWSH, epd, erbf, ersf, etbe, etmt, FOW, ias, LLM, MR, OD, |
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| 39 | owr, pd, PPM, rbf_reset, sr_a, STP_SPLY, STPEN, tbe, xmit_buffer, |
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| 40 | clear_interrupts, DQ_CONTROL, FSM_CLK, INTR, |
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| 41 | OneWireIO_eq_Load, OW_LOW, OW_SHORT, pdr, rbf, rcvr_buffer, reset_owr, |
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| 42 | rsrf, STPZ, temt); |
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| 43 | |
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| 44 | input BIT_CTL; // enable only single bit transmitions |
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| 45 | input clk; //Master clk; much faster than 1us |
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| 46 | input clk_1us_en; // 1us reference clock |
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| 47 | input clr_activate_intr; |
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| 48 | input DQ_IN; // OW data input |
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| 49 | input EN_FOW; // enable force OW functionality |
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| 50 | input EOWL; // enable One wire bus low interrupt |
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| 51 | input EOWSH; // enable One Wire bus short interrupt |
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| 52 | input epd; // enable presence detect interrupt |
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| 53 | input erbf; // enable receive buffer full interrupt |
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| 54 | input ersf; // enable receive shift register full int. |
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| 55 | input etbe; // enable transmit buffer empty interrupt |
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| 56 | input etmt; // enable transmit shift inputister empty int. |
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| 57 | input FOW; // Force OW value low |
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| 58 | input ias; // INTR active state |
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| 59 | input LLM; // long line mode enable |
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| 60 | input MR; // master reset |
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| 61 | input OD; // enable overdrive |
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| 62 | input owr; // one wire reset ??? |
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| 63 | input pd; // presence detect interrupt |
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| 64 | input PPM; // presence pulse masking enable |
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| 65 | input rbf_reset; // clear for receive buffer full interrupt |
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| 66 | input sr_a; // search rom accelorator enable |
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| 67 | input STP_SPLY; // enable strong pull up supply mode |
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| 68 | input STPEN; // enable strong pull up output |
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| 69 | input tbe; // transmit buffer empty interrupt |
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| 70 | input [7:0] xmit_buffer; // transmit buffer |
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| 71 | |
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| 72 | |
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| 73 | output clear_interrupts; |
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| 74 | output DQ_CONTROL; // OW pulldown control |
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| 75 | output FSM_CLK; // state machine clk |
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| 76 | output INTR; // One wire master interrupt output signal |
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| 77 | output OneWireIO_eq_Load; |
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| 78 | output OW_LOW; // One wire low interrupt |
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| 79 | output OW_SHORT; // One wire short interrupt |
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| 80 | output pdr; // presence detect result |
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| 81 | output rbf; // receive buffer full int |
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| 82 | output [7:0] rcvr_buffer; // receive register |
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| 83 | output reset_owr; // |
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| 84 | output rsrf; // receive shift reg full interrupt |
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| 85 | output STPZ; // Strong pullup control (active low) |
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| 86 | output temt; // transmit shift reg empty interrupt |
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| 87 | |
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| 88 | // |
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| 89 | // Define the states |
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| 90 | // |
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| 91 | parameter [2:0] Idle = 3'b000, // Idle |
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| 92 | CheckOWR = 3'b001, // Check for shorted OW |
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| 93 | Reset_Low = 3'b010, // Start reset |
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| 94 | PD_Wait = 3'b011, // release line for 1T |
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| 95 | PD_Sample = 3'b100, // sample line after slowest 1T over |
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| 96 | Reset_High = 3'b101, // recover OW line level |
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| 97 | PD_Force = 3'b110, // mask the presence pulse |
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| 98 | PD_Release = 3'b111; // recover OW line level |
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| 99 | |
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| 100 | parameter [4:0] IdleS= 5'b00000, // Idle state |
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| 101 | Load= 5'b00001, // Load byte |
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| 102 | CheckOW= 5'b00010, // Check for shorted line |
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| 103 | DQLOW= 5'b00011, // Start of timeslot |
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| 104 | WriteZero= 5'b00100, // Write a zero to the 1-wire |
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| 105 | WriteOne= 5'b00101, // Write a one to the 1-wire |
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| 106 | ReadBit= 5'b00110, // Search Rom Accelerator read bit |
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| 107 | FirstPassSR=5'b00111, // Used by SRA |
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| 108 | WriteBitSR= 5'b01000, // Decide what bit value to write in SRA |
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| 109 | WriteBit= 5'b01001, // Writes the chosen bit in SRA |
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| 110 | WaitTS= 5'b01010, // Wait for end of time slot |
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| 111 | IndexInc= 5'b01011, // Increments bit index |
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| 112 | UpdateBuff= 5'b01100, // Updates states of rbf |
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| 113 | ODWriteZero=5'b01101, // Write a zero @ OD speed to OW |
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| 114 | ODWriteOne= 5'b01110, // Write a one @ OD speed to OW |
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| 115 | ClrLowDone= 5'b01111; // disable stpupz before pulldown |
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| 116 | |
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| 117 | |
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| 118 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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| 119 | // micro-second count for bit transitions and sample |
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| 120 | parameter [6:0] // Standard speed |
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| 121 | bit_ts_writeone_high = 7'b0000110, // release-1 @6 us |
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| 122 | bit_ts_writeone_high_ll = 7'b0001000, // rel-1-LLM @8 us |
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| 123 | bit_ts_sample = 7'b0001111, // sample @15 us |
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| 124 | bit_ts_sample_ll = 7'b0011000, // sample/llm @24 us |
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| 125 | bit_ts_writezero_high = 7'b0111100, // release-0 @60 us |
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| 126 | bit_ts_end = 7'b1000110, // end @70 us |
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| 127 | bit_ts_end_ll = 7'b1010000, // end @80 us |
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| 128 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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| 129 | // Overdrive speed |
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| 130 | // note that due to the state machine architecture, the |
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| 131 | // writeone_high_od and sample_od must be 1 and 2 us. |
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| 132 | // writezero_high_od and end_od are adjustable, so long |
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| 133 | // as writezero_high_od does not exceed a particular |
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| 134 | // 1-Wire device max low time. |
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| 135 | bit_ts_writeone_high_od = 7'b0000001, // release-1 @1 us |
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| 136 | bit_ts_sample_od = 7'b0000010, // sample @2 us |
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| 137 | bit_ts_writezero_high_od = 7'b0001000, // release-0 @8 us |
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| 138 | bit_ts_end_od = 7'b0001001; // end @10 us |
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| 139 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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| 140 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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| 141 | // micro-second count for reset transitions |
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| 142 | parameter [10:0] // Standard speed |
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| 143 | reset_ts_release = 11'b01001011000, // release @600 us |
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| 144 | reset_ts_no_stpz = 11'b01001100010, // stpz=1 @610 us |
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| 145 | reset_ts_ppm = 11'b01001101100, // pp-mask @620 us |
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| 146 | reset_ts_sample = 11'b01010011110, // sample @670 us |
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| 147 | reset_ts_llsample= 11'b01010101101, // sample @685 us |
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| 148 | reset_ts_ppm_end = 11'b01010110010, // ppm-end @690 us |
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| 149 | reset_ts_stpz = 11'b01110110110, // stpz @950 us |
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| 150 | reset_ts_recover = 11'b01111000000, // recover @960 us |
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| 151 | reset_ts_end = 11'b10000111000, // end @1080 us |
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| 152 | // Overdrive speed |
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| 153 | reset_ts_release_od = 11'b00001000110, // release @70 us |
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| 154 | reset_ts_no_stpz_od = 11'b00001001011, // stpz=1 @75 us |
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| 155 | reset_ts_sample_od = 11'b00001001111, // sample @79 us |
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| 156 | reset_ts_stpz_od = 11'b00001101001, // stpz @105 us |
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| 157 | reset_ts_recover_od = 11'b00001110011, // recover @115 us |
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| 158 | reset_ts_end_od = 11'b00010000000; // end @128 us |
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| 159 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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| 160 | |
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| 161 | |
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| 162 | wire owr; // 1W reset command |
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| 163 | wire sr_a; // search ROM accelerator command |
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| 164 | |
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| 165 | // interrupt register |
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| 166 | wire pd; // presence detect done flag |
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| 167 | reg pdr; // presence detect result |
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| 168 | wire tbe; // transmit buffer empty flag |
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| 169 | reg temt; // transmit shift register empty flag |
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| 170 | wire temt_ext; // temt extended flag |
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| 171 | reg rbf; // receive buffer full flag |
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| 172 | reg rsrf; // receive shift register full flag |
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| 173 | reg OW_SHORT; // OW line shorted interrupt |
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| 174 | reg OW_LOW; // OW line low interrupt |
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| 175 | reg INTR; |
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| 176 | |
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| 177 | //wire rsrf_reset; // clear signal for rsrf |
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| 178 | reg set_rbf; // set signal for rbf |
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| 179 | |
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| 180 | // interrupt enable register |
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| 181 | wire epd; // enable presence detect interrupt |
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| 182 | wire ias; // INTR active state |
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| 183 | wire etbe; // enable transmit buffer empty interrupt |
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| 184 | wire etmt; // enable transmit shift register empty int. |
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| 185 | wire erbf; // enable receive buffer full interrupt |
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| 186 | wire ersf; // enable receive shift register full int. |
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| 187 | wire EOWSH; // enable ow shorted interrupt |
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| 188 | wire EOWL; // enable ow low interrupt |
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| 189 | |
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| 190 | wire clr_activate_intr; |
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| 191 | reg reset_owr; |
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| 192 | |
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| 193 | reg activate_intr; |
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| 194 | reg dly_clr_activate_intr; |
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| 195 | reg clear_interrupts; |
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| 196 | |
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| 197 | reg SET_RSHRT; // set ow_short prior to ow reset |
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| 198 | reg SET_IOSHRT; // set ow_short prior to tx a bit |
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| 199 | |
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| 200 | wire [7:0] xmit_buffer; // transmit buffer |
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| 201 | reg [7:0] xmit_shiftreg; // transmit shift register |
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| 202 | |
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| 203 | reg [7:0] rcvr_buffer; // receive buffer |
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| 204 | reg [7:0] rcvr_shiftreg; // receive shift register |
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| 205 | |
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| 206 | reg last_rcvr_bit; // active on index = 7 to begin shift to rbe |
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| 207 | reg byte_done; |
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| 208 | reg byte_done_flag, bdext1; // signals to stretch byte_done |
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| 209 | |
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| 210 | reg First; // for Search ROM accelerator |
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| 211 | reg BitRead1; |
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| 212 | reg BitRead2; |
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| 213 | reg BitWrite; |
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| 214 | |
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| 215 | reg [2:0] OneWireReset; |
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| 216 | reg [4:0] OneWireIO; |
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| 217 | |
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| 218 | reg [10:0] count; |
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| 219 | //reg [4:0] smCnt; |
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| 220 | reg [3:0] index; |
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| 221 | reg [6:0] TimeSlotCnt; |
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| 222 | |
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| 223 | reg PD_READ; |
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| 224 | reg LOW_DONE; |
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| 225 | reg DQ_CONTROL_F; |
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| 226 | wire DQ_CONTROL; |
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| 227 | wire STPZ; |
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| 228 | reg DQ_IN_HIGH; |
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| 229 | reg OD_DQH; |
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| 230 | reg rbf_set; |
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| 231 | reg rsrf_reset; |
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| 232 | |
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| 233 | reg ROW; |
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| 234 | |
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| 235 | // wire FSM_CLK = clk_1us; |
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| 236 | wire FSM_CLK = clk; |
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| 237 | |
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| 238 | // |
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| 239 | // 1 wire control |
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| 240 | // |
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| 241 | assign DQ_CONTROL = MR ? 1'b1 : DQ_CONTROL_F; //GAG added in asynch RESET |
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| 242 | |
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| 243 | always @(posedge clk) //GAG added in ODWriteZero |
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| 244 | begin |
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| 245 | if(clk_1us_en) |
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| 246 | begin |
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| 247 | DQ_CONTROL_F <= |
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| 248 | (EN_FOW == 1) && (FOW == 1)?0: |
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| 249 | OneWireReset == Reset_Low?0: |
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| 250 | OneWireReset == PD_Wait?1: |
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| 251 | OneWireReset == PD_Force?0: |
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| 252 | OneWireIO == DQLOW?0: |
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| 253 | OneWireIO == WriteZero?0: |
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| 254 | OneWireIO == ODWriteZero?0: |
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| 255 | OneWireIO == WriteBit?0: |
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| 256 | 1; |
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| 257 | end |
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| 258 | end |
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| 259 | |
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| 260 | wire OneWireIO_eq_Load = OneWireIO == Load; |
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| 261 | |
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| 262 | // |
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| 263 | // Strong Pullup control section - GAG |
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| 264 | // not pulling line low, not checking for pres detect, and |
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| 265 | // OW has recovered from read |
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| 266 | // SPLY is only for enabling STP when a slave requires high current |
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| 267 | // and STP_SPLY is enabled |
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| 268 | // |
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| 269 | wire SPLY = (STP_SPLY && (OneWireReset == Idle) && (OneWireIO == IdleS)); |
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| 270 | assign STPZ = !(STPEN && DQ_CONTROL && DQ_IN_HIGH |
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| 271 | && (PD_READ || LOW_DONE || SPLY)); |
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| 272 | |
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| 273 | always @(posedge MR or posedge FSM_CLK) |
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| 274 | begin |
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| 275 | if (MR) |
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| 276 | begin |
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| 277 | DQ_IN_HIGH <= 0; |
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| 278 | OD_DQH <=0; |
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| 279 | end |
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| 280 | else if(clk_1us_en) |
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| 281 | begin |
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| 282 | if (OD) |
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| 283 | if(DQ_IN && !DQ_IN_HIGH && !OD_DQH) |
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| 284 | begin |
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| 285 | DQ_IN_HIGH <= 1; |
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| 286 | OD_DQH <=1; |
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| 287 | end |
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| 288 | else if(OD_DQH && DQ_IN) |
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| 289 | DQ_IN_HIGH <= 0; |
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| 290 | else |
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| 291 | begin |
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| 292 | OD_DQH <=0; |
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| 293 | DQ_IN_HIGH <= 0; |
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| 294 | end |
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| 295 | else |
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| 296 | begin |
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| 297 | if(DQ_IN && !DQ_IN_HIGH) |
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| 298 | DQ_IN_HIGH <= 1; |
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| 299 | else if (DQ_IN && DQ_IN_HIGH) |
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| 300 | DQ_IN_HIGH <= DQ_IN_HIGH; |
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| 301 | else |
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| 302 | DQ_IN_HIGH <= 0; |
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| 303 | end |
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| 304 | end |
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| 305 | end |
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| 306 | |
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| 307 | // |
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| 308 | // Update receive buffer and the rsrf and rbf int flags |
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| 309 | // |
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| 310 | always @(posedge MR or posedge rbf_reset or posedge rbf_set) |
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| 311 | if (MR) |
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| 312 | rbf <= 0; |
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| 313 | else if (rbf_reset) //note that rbf resets at the beginning of the RX buff read |
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| 314 | rbf <= 0; |
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| 315 | else |
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| 316 | rbf <= 1; |
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| 317 | |
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| 318 | always @(posedge MR or posedge FSM_CLK) |
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| 319 | if (MR) |
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| 320 | rsrf <= 1'b0; |
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| 321 | else if(clk_1us_en) |
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| 322 | begin |
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| 323 | if (last_rcvr_bit || BIT_CTL) |
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| 324 | begin |
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| 325 | if (OneWireIO == IndexInc) |
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| 326 | rsrf <= 1'b1; |
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| 327 | else if (rsrf_reset) |
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| 328 | rsrf <= 1'b0; |
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| 329 | end |
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| 330 | else if (rsrf_reset || (OneWireIO == DQLOW)) |
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| 331 | rsrf <= 1'b0; |
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| 332 | end |
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| 333 | |
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| 334 | always @(posedge FSM_CLK or posedge MR) |
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| 335 | if (MR) |
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| 336 | begin |
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| 337 | rcvr_buffer <= 0; |
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| 338 | rbf_set <= 0; |
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| 339 | end |
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| 340 | else if(clk_1us_en) |
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| 341 | if (rsrf && !rbf) |
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| 342 | begin |
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| 343 | rcvr_buffer <= rcvr_shiftreg; |
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| 344 | rbf_set <= 1'b1; |
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| 345 | rsrf_reset <= 1'b1; |
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| 346 | end |
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| 347 | else |
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| 348 | begin |
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| 349 | rbf_set <= 1'b0; |
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| 350 | if (!rsrf) |
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| 351 | rsrf_reset <= 1'b0; |
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| 352 | end |
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| 353 | |
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| 354 | // |
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| 355 | // Update OW shorted interrupt |
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| 356 | // |
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| 357 | always @(posedge MR or posedge FSM_CLK) |
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| 358 | begin |
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| 359 | if(MR) |
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| 360 | OW_SHORT <= 1'b0; |
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| 361 | else if(clk_1us_en) |
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| 362 | begin |
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| 363 | if (SET_RSHRT || SET_IOSHRT) |
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| 364 | OW_SHORT <= 1'b1; |
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| 365 | else if (clr_activate_intr) |
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| 366 | OW_SHORT <= 1'b0; |
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| 367 | else |
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| 368 | OW_SHORT <= OW_SHORT; |
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| 369 | end |
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| 370 | end |
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| 371 | // |
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| 372 | // Update OW bus low interrupt |
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| 373 | // |
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| 374 | always @(posedge MR or posedge FSM_CLK) |
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| 375 | begin |
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| 376 | if (MR) |
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| 377 | OW_LOW <= 0; |
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| 378 | else if(clk_1us_en) |
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| 379 | begin |
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| 380 | if (!DQ_IN && (OneWireReset == Idle) && (OneWireIO == IdleS)) |
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| 381 | OW_LOW <= 1; |
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| 382 | else if (clr_activate_intr) |
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| 383 | OW_LOW <= 0; |
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| 384 | else |
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| 385 | OW_LOW <= OW_LOW; |
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| 386 | end |
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| 387 | end |
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| 388 | |
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| 389 | /////////////////////////////////////////////////////////////// |
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| 390 | // The following section handles the interrupt itself |
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| 391 | /////////////////////////////////////////////////////////////// |
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| 392 | |
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| 393 | // |
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| 394 | // Create clear interrupts |
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| 395 | // |
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| 396 | always @(posedge MR or posedge FSM_CLK) |
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| 397 | if (MR) |
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| 398 | begin |
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| 399 | //dly_clr_activate_intr <= 1'b0; |
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| 400 | clear_interrupts <= 1'b0; |
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| 401 | end // if (MR) |
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| 402 | else if(clk_1us_en) |
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| 403 | begin |
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| 404 | //dly_clr_activate_intr<=clr_activate_intr; |
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| 405 | clear_interrupts<=clr_activate_intr; |
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| 406 | //clear_interrupts <= dly_clr_activate_intr ; |
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| 407 | end |
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| 408 | |
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| 409 | wire acint_reset = MR || clr_activate_intr; |
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| 410 | |
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| 411 | // |
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| 412 | // Check for active interrupt |
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| 413 | // |
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| 414 | always @(posedge acint_reset or posedge FSM_CLK) |
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| 415 | if(acint_reset) |
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| 416 | activate_intr <= 1'b0; |
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| 417 | else if(clk_1us_en) |
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| 418 | case(1) |
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| 419 | pd && epd: |
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| 420 | activate_intr <= 1'b1; |
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| 421 | tbe && etbe && !temt: |
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| 422 | activate_intr <= 1'b1; |
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| 423 | temt_ext && etmt: |
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| 424 | activate_intr <= 1'b1; |
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| 425 | rbf && erbf: |
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| 426 | activate_intr <= 1'b1; |
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| 427 | rsrf && ersf: |
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| 428 | activate_intr <= 1'b1; |
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| 429 | OW_LOW && EOWL: |
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| 430 | activate_intr <= 1'b1; |
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| 431 | OW_SHORT && EOWSH: |
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| 432 | activate_intr <= 1'b1; |
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| 433 | endcase // case(1) |
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| 434 | |
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| 435 | // |
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| 436 | // Create INTR signal by checking for active interrupt and active |
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| 437 | // state of INTR |
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| 438 | // |
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| 439 | always @(activate_intr or ias) |
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| 440 | case({activate_intr,ias}) |
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| 441 | 2'b11: |
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| 442 | INTR <= 1'b1; |
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| 443 | 2'b01: |
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| 444 | INTR <= 1'b0; |
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| 445 | 2'b10: |
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| 446 | INTR <= 1'b1; // shughes - 8-16-04 - was 1'b0 |
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| 447 | default: |
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| 448 | INTR <= 1'b0; // shughes - 8-16-04 - was 1'b1 |
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| 449 | endcase // case({activate_intr,ias}) |
---|
| 450 | |
---|
| 451 | |
---|
| 452 | |
---|
| 453 | //-------------------------------------------------------------------------- |
---|
| 454 | // |
---|
| 455 | // OneWireReset |
---|
| 456 | // |
---|
| 457 | // this state machine performs the 1-wire reset and presence detect |
---|
| 458 | // - Added OD for overdrive speed presence detect |
---|
| 459 | // - Added PD_LOW bit for strong pullup control |
---|
| 460 | // |
---|
| 461 | // Idle : OW high - waiting to issue a PD |
---|
| 462 | // CheckOWR : OW high - checks for shorted OW line |
---|
| 463 | // Reset_Low : OW low - held down for GT8 OW osc periods |
---|
| 464 | // PD_Wait : OW high - released and waits for 1T |
---|
| 465 | // PD_Sample : OW high - checks to see if a slave is out there pulling |
---|
| 466 | // OW low for 4T |
---|
| 467 | // Reset_High : OW high - slave, if any, release OW and host lets it recover |
---|
| 468 | //-------------------------------------------------------------------------- |
---|
| 469 | |
---|
| 470 | always @(posedge FSM_CLK or posedge MR) |
---|
| 471 | if(MR) begin |
---|
| 472 | pdr <= 1'b1; // Added default state to conform to spec - SDS |
---|
| 473 | OneWireReset <= Idle; |
---|
| 474 | //smCnt <= 0; // added to init simulations |
---|
| 475 | count <= 0; |
---|
| 476 | PD_READ <= 0; // Added PD_READ - GAG |
---|
| 477 | reset_owr <= 0; |
---|
| 478 | SET_RSHRT <= 0; // |
---|
| 479 | ROW <= 0; |
---|
| 480 | end |
---|
| 481 | else if(clk_1us_en) |
---|
| 482 | begin |
---|
| 483 | if(!owr) |
---|
| 484 | begin |
---|
| 485 | count <= 0; |
---|
| 486 | ROW <= 0; |
---|
| 487 | reset_owr <= 0; |
---|
| 488 | OneWireReset <= Idle; |
---|
| 489 | end |
---|
| 490 | else |
---|
| 491 | case(OneWireReset) |
---|
| 492 | Idle: begin |
---|
| 493 | if (ROW) |
---|
| 494 | reset_owr <= 1; |
---|
| 495 | else |
---|
| 496 | begin |
---|
| 497 | count <= 0; |
---|
| 498 | SET_RSHRT <=0; |
---|
| 499 | reset_owr <= 0; |
---|
| 500 | OneWireReset <= CheckOWR; |
---|
| 501 | end |
---|
| 502 | end |
---|
| 503 | |
---|
| 504 | CheckOWR: begin |
---|
| 505 | OneWireReset <= Reset_Low; |
---|
| 506 | if(!DQ_IN) |
---|
| 507 | SET_RSHRT <= 1; |
---|
| 508 | end |
---|
| 509 | |
---|
| 510 | Reset_Low: begin |
---|
| 511 | count <= count + 1; |
---|
| 512 | PD_READ <= 0; // Added PD_READ - GAG |
---|
| 513 | if(OD) // Added OD - GAG |
---|
| 514 | begin |
---|
| 515 | // tRSTL - OD |
---|
| 516 | if(count == reset_ts_release_od) |
---|
| 517 | begin |
---|
| 518 | OneWireReset <= PD_Wait; |
---|
| 519 | PD_READ <= 1; |
---|
| 520 | end |
---|
| 521 | end |
---|
| 522 | // tRSTL - STD |
---|
| 523 | else if(count == reset_ts_release) |
---|
| 524 | begin |
---|
| 525 | OneWireReset <= PD_Wait; |
---|
| 526 | PD_READ <= 1; |
---|
| 527 | end |
---|
| 528 | end |
---|
| 529 | |
---|
| 530 | PD_Wait: begin |
---|
| 531 | SET_RSHRT <= 0; |
---|
| 532 | count <= count + 1; |
---|
| 533 | if(!DQ_IN & DQ_CONTROL_F) begin |
---|
| 534 | OneWireReset <= PD_Sample; |
---|
| 535 | //smCnt <= 0; |
---|
| 536 | end |
---|
| 537 | else if(OD) |
---|
| 538 | begin |
---|
| 539 | // (tRSTL + pull-up time) - OD |
---|
| 540 | if(count==reset_ts_no_stpz_od) |
---|
| 541 | // disables stp_sply |
---|
| 542 | PD_READ <= 0; // Be sure to turn off 4 MPD mode |
---|
| 543 | // tMSP - OD |
---|
| 544 | else if(count == reset_ts_sample_od) |
---|
| 545 | begin |
---|
| 546 | OneWireReset <= PD_Sample; |
---|
| 547 | //smCnt <= 0; |
---|
| 548 | end |
---|
| 549 | end |
---|
| 550 | // (tRSTL + pull-up time) - STD |
---|
| 551 | else if(count == reset_ts_no_stpz) |
---|
| 552 | // disables stp_sply |
---|
| 553 | PD_READ <= 0; // Be sure to turn off 4 MPD mode |
---|
| 554 | // tPPM1 - STD |
---|
| 555 | else if((count == reset_ts_ppm) && PPM) |
---|
| 556 | OneWireReset <= PD_Force; |
---|
| 557 | // tMSP - STD |
---|
| 558 | else if(count == reset_ts_llsample && !LLM) |
---|
| 559 | begin |
---|
| 560 | OneWireReset <= PD_Sample; |
---|
| 561 | //smCnt <= 0; |
---|
| 562 | end |
---|
| 563 | else if(count == reset_ts_sample && LLM) |
---|
| 564 | begin |
---|
| 565 | OneWireReset <= PD_Sample; |
---|
| 566 | //smCnt <= 0; |
---|
| 567 | end |
---|
| 568 | end |
---|
| 569 | |
---|
| 570 | PD_Sample: begin |
---|
| 571 | PD_READ <= 0; |
---|
| 572 | count <= count + 1; |
---|
| 573 | //smCnt <= smCnt + 1; |
---|
| 574 | //if (OD) // Added OD - GAG |
---|
| 575 | // begin |
---|
| 576 | // if(smCnt == 3-1) |
---|
| 577 | // begin |
---|
| 578 | pdr <= DQ_IN; |
---|
| 579 | OneWireReset <= Reset_High; |
---|
| 580 | // end |
---|
| 581 | // end |
---|
| 582 | //else |
---|
| 583 | // if(smCnt == 30-1) |
---|
| 584 | // begin |
---|
| 585 | // pdr <= DQ_IN; |
---|
| 586 | // OneWireReset <= Reset_High; |
---|
| 587 | // end |
---|
| 588 | end |
---|
| 589 | |
---|
| 590 | Reset_High: begin |
---|
| 591 | count <= count + 1; |
---|
| 592 | if (OD) // Added OD - GAG |
---|
| 593 | begin |
---|
| 594 | if (count == reset_ts_stpz_od) |
---|
| 595 | begin |
---|
| 596 | if (DQ_IN) |
---|
| 597 | PD_READ <= 1; |
---|
| 598 | end |
---|
| 599 | else if (count == reset_ts_recover_od) |
---|
| 600 | begin |
---|
| 601 | PD_READ <= 0; |
---|
| 602 | end |
---|
| 603 | else if (count == reset_ts_end_od) |
---|
| 604 | begin |
---|
| 605 | PD_READ <= 0; |
---|
| 606 | OneWireReset <= Idle; |
---|
| 607 | ROW <= 1; |
---|
| 608 | end |
---|
| 609 | end |
---|
| 610 | else |
---|
| 611 | begin |
---|
| 612 | if(count == reset_ts_stpz) |
---|
| 613 | begin |
---|
| 614 | if (DQ_IN) |
---|
| 615 | PD_READ <= 1; |
---|
| 616 | end |
---|
| 617 | else if (count == reset_ts_recover) |
---|
| 618 | begin |
---|
| 619 | PD_READ <= 0; |
---|
| 620 | end |
---|
| 621 | else if (count == reset_ts_end) |
---|
| 622 | begin |
---|
| 623 | PD_READ <= 0; |
---|
| 624 | OneWireReset <= Idle; |
---|
| 625 | ROW <= 1; |
---|
| 626 | end |
---|
| 627 | end |
---|
| 628 | end |
---|
| 629 | |
---|
| 630 | PD_Force: begin |
---|
| 631 | count <= count + 1; |
---|
| 632 | // tPPM2 |
---|
| 633 | if (count == reset_ts_ppm_end) |
---|
| 634 | begin |
---|
| 635 | OneWireReset <= PD_Release; |
---|
| 636 | end |
---|
| 637 | end |
---|
| 638 | |
---|
| 639 | PD_Release: begin |
---|
| 640 | count <= count + 1; |
---|
| 641 | pdr <= 0; //force valid result |
---|
| 642 | if(count == reset_ts_stpz) |
---|
| 643 | begin |
---|
| 644 | if (DQ_IN) |
---|
| 645 | PD_READ <= 1; |
---|
| 646 | end |
---|
| 647 | else if (count == reset_ts_recover) |
---|
| 648 | begin |
---|
| 649 | PD_READ <= 0; |
---|
| 650 | end |
---|
| 651 | else if (count == reset_ts_end) |
---|
| 652 | begin |
---|
| 653 | PD_READ <= 0; |
---|
| 654 | OneWireReset <= Idle; |
---|
| 655 | ROW <= 1; |
---|
| 656 | end |
---|
| 657 | end |
---|
| 658 | |
---|
| 659 | endcase |
---|
| 660 | end |
---|
| 661 | |
---|
| 662 | //-------------------------------------------------------------------------- |
---|
| 663 | // |
---|
| 664 | // OneWireIO |
---|
| 665 | // |
---|
| 666 | // this state machine performs the 1-wire writing and reading |
---|
| 667 | // - Added ODWriteZero and ODWriteOne for overdrive timing |
---|
| 668 | // |
---|
| 669 | // IdleS : Waiting for transmit byte to be loaded |
---|
| 670 | // ClrLowDone : Disables strong pullup before pulldown turns on |
---|
| 671 | // Load : Loads byte to shift reg |
---|
| 672 | // CheckOW : Checks for OW short |
---|
| 673 | // DQLOW : Starts time slot with OW = 0 |
---|
| 674 | // ODWriteZero : Completes write of 0 bit / read bit in OD speed |
---|
| 675 | // ODWriteOne : Completes write of 1 bit / read bit in OD speed |
---|
| 676 | // WriteZero : Completes write of 0 bit / read bit in standard speed |
---|
| 677 | // WriteOne : Completes write of 1 bit / read bit in standard speed |
---|
| 678 | // ReadBit : AutoSearchRom : Reads the first bit value |
---|
| 679 | // FirstPassSR : AutoSearchRom : Decides to do another read or the write |
---|
| 680 | // WriteBitSR : AutoSearchRom : Determines the bit to write |
---|
| 681 | // WriteBit : AutoSearchRom : Writes the bit |
---|
| 682 | // WatiTS : Allows OW to recover for the remainder of the time slot |
---|
| 683 | // IndexInc : Increment the index to send out next bit (in byte) |
---|
| 684 | // UpdateBuff : Allows other signals to update following finished byte/bit |
---|
| 685 | //-------------------------------------------------------------------------- |
---|
| 686 | |
---|
| 687 | // The following 2 registers are to stretch the temt signal to catch the |
---|
| 688 | // temt interrupt source - SDS |
---|
| 689 | |
---|
| 690 | always @(posedge MR or posedge FSM_CLK) |
---|
| 691 | if(MR) |
---|
| 692 | bdext1 <= 1'b0; |
---|
| 693 | else if(clk_1us_en) |
---|
| 694 | bdext1 <= byte_done; |
---|
| 695 | |
---|
| 696 | always @(posedge MR or posedge FSM_CLK) |
---|
| 697 | if(MR) |
---|
| 698 | byte_done_flag <= 1'b0; |
---|
| 699 | else if(clk_1us_en) |
---|
| 700 | byte_done_flag <= bdext1; |
---|
| 701 | |
---|
| 702 | assign temt_ext = temt && byte_done_flag; |
---|
| 703 | |
---|
| 704 | // The index variable has been decoded explicitly in this state machine |
---|
| 705 | // so that the code would compile on the Cypress warp compiler - SDS |
---|
| 706 | always @(posedge FSM_CLK or posedge MR) |
---|
| 707 | if(MR) begin |
---|
| 708 | index <= 0; |
---|
| 709 | TimeSlotCnt <= 0; |
---|
| 710 | temt <= 1'b1; |
---|
| 711 | last_rcvr_bit <= 1'b0; |
---|
| 712 | rcvr_shiftreg <= 0; |
---|
| 713 | OneWireIO <= IdleS; |
---|
| 714 | BitRead1<=0; |
---|
| 715 | BitRead2<=0; |
---|
| 716 | BitWrite<=0; |
---|
| 717 | First <= 1'b0; |
---|
| 718 | byte_done <= 1'b0; |
---|
| 719 | xmit_shiftreg<=0; |
---|
| 720 | LOW_DONE <= 0; |
---|
| 721 | SET_IOSHRT <= 0; |
---|
| 722 | end |
---|
| 723 | else if(clk_1us_en) |
---|
| 724 | case(OneWireIO) |
---|
| 725 | |
---|
| 726 | // IdleS state clears variables and waits for something to be |
---|
| 727 | // deposited in the transmit buffer. When something is there, |
---|
| 728 | // the next state is Load. |
---|
| 729 | IdleS: |
---|
| 730 | begin |
---|
| 731 | byte_done <= 1'b0; |
---|
| 732 | index <= 0; |
---|
| 733 | last_rcvr_bit <= 1'b0; |
---|
| 734 | First <= 1'b0; |
---|
| 735 | TimeSlotCnt <= 0; |
---|
| 736 | LOW_DONE <= 0; |
---|
| 737 | SET_IOSHRT <= 0; |
---|
| 738 | temt <= 1'b1; |
---|
| 739 | if(!tbe) |
---|
| 740 | begin |
---|
| 741 | if(STPEN) |
---|
| 742 | OneWireIO <= ClrLowDone; |
---|
| 743 | else |
---|
| 744 | OneWireIO <= Load; |
---|
| 745 | end |
---|
| 746 | else |
---|
| 747 | OneWireIO <= IdleS; |
---|
| 748 | end |
---|
| 749 | |
---|
| 750 | // New state added to be sure the strong pullup will be disabled |
---|
| 751 | // before the OW pulldown turns on |
---|
| 752 | ClrLowDone: |
---|
| 753 | begin |
---|
| 754 | LOW_DONE <= 0; |
---|
| 755 | if (!LOW_DONE) |
---|
| 756 | OneWireIO <= Load; |
---|
| 757 | end |
---|
| 758 | |
---|
| 759 | // Load transfers the transmit buffer to the transmit shift register, |
---|
| 760 | // then clears the transmit shift register empty interrupt. The next |
---|
| 761 | // state is then DQLOW. |
---|
| 762 | Load: |
---|
| 763 | begin |
---|
| 764 | xmit_shiftreg <= xmit_buffer; |
---|
| 765 | rcvr_shiftreg <= 0; |
---|
| 766 | temt <= 1'b0; |
---|
| 767 | LOW_DONE <= 0; |
---|
| 768 | OneWireIO <= CheckOW; |
---|
| 769 | end |
---|
| 770 | |
---|
| 771 | // Checks OW value before sending out every bit to see if line |
---|
| 772 | // was forced low by some other means at an incorrect time |
---|
| 773 | CheckOW: |
---|
| 774 | begin |
---|
| 775 | OneWireIO <= DQLOW; |
---|
| 776 | //TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 777 | if (!DQ_IN) |
---|
| 778 | SET_IOSHRT <= 1; |
---|
| 779 | end |
---|
| 780 | |
---|
| 781 | // DQLOW pulls the DQ line low for 1us, beginning a timeslot. |
---|
| 782 | // If sr_a is 0, it is a normal write/read operation. If sr_a |
---|
| 783 | // is a 1, then you must go into Search ROM accelerator mode. |
---|
| 784 | // If OD is 1, the part is in overdrive and must perform |
---|
| 785 | // ODWrites instead of normal Writes while OD is 0. |
---|
| 786 | DQLOW: |
---|
| 787 | begin |
---|
| 788 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 789 | LOW_DONE <= 0; |
---|
| 790 | if (OD) |
---|
| 791 | begin |
---|
| 792 | //if(TimeSlotCnt==bit_ts_writeone_high_od) |
---|
| 793 | //begin |
---|
| 794 | if(!sr_a) |
---|
| 795 | begin |
---|
| 796 | case(index) |
---|
| 797 | 0: |
---|
| 798 | if(!xmit_shiftreg[0]) |
---|
| 799 | OneWireIO <= ODWriteZero; |
---|
| 800 | else |
---|
| 801 | OneWireIO <= ODWriteOne; |
---|
| 802 | 1: |
---|
| 803 | if(!xmit_shiftreg[1]) |
---|
| 804 | OneWireIO <= ODWriteZero; |
---|
| 805 | else |
---|
| 806 | OneWireIO <= ODWriteOne; |
---|
| 807 | 2: |
---|
| 808 | if(!xmit_shiftreg[2]) |
---|
| 809 | OneWireIO <= ODWriteZero; |
---|
| 810 | else |
---|
| 811 | OneWireIO <= ODWriteOne; |
---|
| 812 | 3: |
---|
| 813 | if(!xmit_shiftreg[3]) |
---|
| 814 | OneWireIO <= ODWriteZero; |
---|
| 815 | else |
---|
| 816 | OneWireIO <= ODWriteOne; |
---|
| 817 | 4: |
---|
| 818 | if(!xmit_shiftreg[4]) |
---|
| 819 | OneWireIO <= ODWriteZero; |
---|
| 820 | else |
---|
| 821 | OneWireIO <= ODWriteOne; |
---|
| 822 | 5: |
---|
| 823 | if(!xmit_shiftreg[5]) |
---|
| 824 | OneWireIO <= ODWriteZero; |
---|
| 825 | else |
---|
| 826 | OneWireIO <= ODWriteOne; |
---|
| 827 | 6: |
---|
| 828 | if(!xmit_shiftreg[6]) |
---|
| 829 | OneWireIO <= ODWriteZero; |
---|
| 830 | else |
---|
| 831 | OneWireIO <= ODWriteOne; |
---|
| 832 | 7: |
---|
| 833 | if(!xmit_shiftreg[7]) |
---|
| 834 | OneWireIO <= ODWriteZero; |
---|
| 835 | else |
---|
| 836 | OneWireIO <= ODWriteOne; |
---|
| 837 | endcase // case(index) |
---|
| 838 | end |
---|
| 839 | else // Search Rom Accelerator mode |
---|
| 840 | OneWireIO <= ReadBit; |
---|
| 841 | end |
---|
| 842 | //end |
---|
| 843 | else if(((TimeSlotCnt==bit_ts_writeone_high) && !LLM) || |
---|
| 844 | ((TimeSlotCnt==bit_ts_writeone_high_ll) && LLM)) |
---|
| 845 | begin |
---|
| 846 | if(!sr_a) // Normal write |
---|
| 847 | begin |
---|
| 848 | case(index) |
---|
| 849 | 0: |
---|
| 850 | if(!xmit_shiftreg[0]) |
---|
| 851 | OneWireIO <= WriteZero; |
---|
| 852 | else |
---|
| 853 | OneWireIO <= WriteOne; |
---|
| 854 | 1: |
---|
| 855 | if(!xmit_shiftreg[1]) |
---|
| 856 | OneWireIO <= WriteZero; |
---|
| 857 | else |
---|
| 858 | OneWireIO <= WriteOne; |
---|
| 859 | 2: |
---|
| 860 | if(!xmit_shiftreg[2]) |
---|
| 861 | OneWireIO <= WriteZero; |
---|
| 862 | else |
---|
| 863 | OneWireIO <= WriteOne; |
---|
| 864 | 3: |
---|
| 865 | if(!xmit_shiftreg[3]) |
---|
| 866 | OneWireIO <= WriteZero; |
---|
| 867 | else |
---|
| 868 | OneWireIO <= WriteOne; |
---|
| 869 | 4: |
---|
| 870 | if(!xmit_shiftreg[4]) |
---|
| 871 | OneWireIO <= WriteZero; |
---|
| 872 | else |
---|
| 873 | OneWireIO <= WriteOne; |
---|
| 874 | 5: |
---|
| 875 | if(!xmit_shiftreg[5]) |
---|
| 876 | OneWireIO <= WriteZero; |
---|
| 877 | else |
---|
| 878 | OneWireIO <= WriteOne; |
---|
| 879 | 6: |
---|
| 880 | if(!xmit_shiftreg[6]) |
---|
| 881 | OneWireIO <= WriteZero; |
---|
| 882 | else |
---|
| 883 | OneWireIO <= WriteOne; |
---|
| 884 | 7: |
---|
| 885 | if(!xmit_shiftreg[7]) |
---|
| 886 | OneWireIO <= WriteZero; |
---|
| 887 | else |
---|
| 888 | OneWireIO <= WriteOne; |
---|
| 889 | endcase // case(index) |
---|
| 890 | end |
---|
| 891 | else // Search Rom Accelerator mode |
---|
| 892 | OneWireIO <= ReadBit; |
---|
| 893 | end |
---|
| 894 | end |
---|
| 895 | |
---|
| 896 | // WriteZero and WriteOne are identical, except for what they do to |
---|
| 897 | // DQ (assigned in concurrent assignments). They both read DQ after |
---|
| 898 | // 15us, then move on to wait for the end of the timeslot, unless |
---|
| 899 | // running in Long Line mode which extends the sample time out to 22 |
---|
| 900 | WriteZero: |
---|
| 901 | begin |
---|
| 902 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 903 | if(((TimeSlotCnt==bit_ts_sample) && !sr_a && !LLM) || |
---|
| 904 | ((TimeSlotCnt==bit_ts_sample_ll) && !sr_a && LLM)) |
---|
| 905 | case(index) |
---|
| 906 | 0: |
---|
| 907 | rcvr_shiftreg[0] <= DQ_IN; |
---|
| 908 | 1: |
---|
| 909 | rcvr_shiftreg[1] <= DQ_IN; |
---|
| 910 | 2: |
---|
| 911 | rcvr_shiftreg[2] <= DQ_IN; |
---|
| 912 | 3: |
---|
| 913 | rcvr_shiftreg[3] <= DQ_IN; |
---|
| 914 | 4: |
---|
| 915 | rcvr_shiftreg[4] <= DQ_IN; |
---|
| 916 | 5: |
---|
| 917 | rcvr_shiftreg[5] <= DQ_IN; |
---|
| 918 | 6: |
---|
| 919 | rcvr_shiftreg[6] <= DQ_IN; |
---|
| 920 | 7: |
---|
| 921 | rcvr_shiftreg[7] <= DQ_IN; |
---|
| 922 | endcase |
---|
| 923 | if(TimeSlotCnt == bit_ts_writezero_high) //62 7_25_01 |
---|
| 924 | OneWireIO <= WaitTS; |
---|
| 925 | if(DQ_IN) |
---|
| 926 | LOW_DONE <= 1; |
---|
| 927 | end |
---|
| 928 | |
---|
| 929 | WriteOne: |
---|
| 930 | begin |
---|
| 931 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 932 | if(((TimeSlotCnt==bit_ts_sample) && !sr_a && !LLM) || |
---|
| 933 | ((TimeSlotCnt==bit_ts_sample_ll) && !sr_a && LLM)) |
---|
| 934 | case(index) |
---|
| 935 | 0: |
---|
| 936 | rcvr_shiftreg[0] <= DQ_IN; |
---|
| 937 | 1: |
---|
| 938 | rcvr_shiftreg[1] <= DQ_IN; |
---|
| 939 | 2: |
---|
| 940 | rcvr_shiftreg[2] <= DQ_IN; |
---|
| 941 | 3: |
---|
| 942 | rcvr_shiftreg[3] <= DQ_IN; |
---|
| 943 | 4: |
---|
| 944 | rcvr_shiftreg[4] <= DQ_IN; |
---|
| 945 | 5: |
---|
| 946 | rcvr_shiftreg[5] <= DQ_IN; |
---|
| 947 | 6: |
---|
| 948 | rcvr_shiftreg[6] <= DQ_IN; |
---|
| 949 | 7: |
---|
| 950 | rcvr_shiftreg[7] <= DQ_IN; |
---|
| 951 | endcase |
---|
| 952 | if(TimeSlotCnt == bit_ts_writezero_high) //62 7_25_01 |
---|
| 953 | OneWireIO <= WaitTS; |
---|
| 954 | if(DQ_IN) |
---|
| 955 | LOW_DONE <= 1; |
---|
| 956 | end |
---|
| 957 | |
---|
| 958 | // ADDED ODWRITE states here GAG |
---|
| 959 | // ODWriteZero and ODWriteOne are identical, except for what they |
---|
| 960 | // do to DQ (assigned in concurrent assignments). They both read |
---|
| 961 | // DQ after 3us, then move on to wait for the end of the timeslot. |
---|
| 962 | ODWriteZero: |
---|
| 963 | begin |
---|
| 964 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 965 | if((TimeSlotCnt == bit_ts_sample_od) && !sr_a) |
---|
| 966 | case(index) |
---|
| 967 | 0: |
---|
| 968 | rcvr_shiftreg[0] <= DQ_IN; |
---|
| 969 | 1: |
---|
| 970 | rcvr_shiftreg[1] <= DQ_IN; |
---|
| 971 | 2: |
---|
| 972 | rcvr_shiftreg[2] <= DQ_IN; |
---|
| 973 | 3: |
---|
| 974 | rcvr_shiftreg[3] <= DQ_IN; |
---|
| 975 | 4: |
---|
| 976 | rcvr_shiftreg[4] <= DQ_IN; |
---|
| 977 | 5: |
---|
| 978 | rcvr_shiftreg[5] <= DQ_IN; |
---|
| 979 | 6: |
---|
| 980 | rcvr_shiftreg[6] <= DQ_IN; |
---|
| 981 | 7: |
---|
| 982 | rcvr_shiftreg[7] <= DQ_IN; |
---|
| 983 | endcase |
---|
| 984 | if(TimeSlotCnt == bit_ts_writezero_high_od) |
---|
| 985 | OneWireIO <= WaitTS; |
---|
| 986 | if(DQ_IN) |
---|
| 987 | LOW_DONE <= 1; |
---|
| 988 | end |
---|
| 989 | |
---|
| 990 | ODWriteOne: |
---|
| 991 | begin |
---|
| 992 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 993 | if((TimeSlotCnt == bit_ts_sample_od) && !sr_a) |
---|
| 994 | case(index) |
---|
| 995 | 0: |
---|
| 996 | rcvr_shiftreg[0] <= DQ_IN; |
---|
| 997 | 1: |
---|
| 998 | rcvr_shiftreg[1] <= DQ_IN; |
---|
| 999 | 2: |
---|
| 1000 | rcvr_shiftreg[2] <= DQ_IN; |
---|
| 1001 | 3: |
---|
| 1002 | rcvr_shiftreg[3] <= DQ_IN; |
---|
| 1003 | 4: |
---|
| 1004 | rcvr_shiftreg[4] <= DQ_IN; |
---|
| 1005 | 5: |
---|
| 1006 | rcvr_shiftreg[5] <= DQ_IN; |
---|
| 1007 | 6: |
---|
| 1008 | rcvr_shiftreg[6] <= DQ_IN; |
---|
| 1009 | 7: |
---|
| 1010 | rcvr_shiftreg[7] <= DQ_IN; |
---|
| 1011 | endcase |
---|
| 1012 | if(TimeSlotCnt == bit_ts_writezero_high_od) |
---|
| 1013 | OneWireIO <= WaitTS; |
---|
| 1014 | if(DQ_IN) |
---|
| 1015 | LOW_DONE <= 1; |
---|
| 1016 | end |
---|
| 1017 | |
---|
| 1018 | // ReadBit used by the SRA to do the required bit reads |
---|
| 1019 | ReadBit: |
---|
| 1020 | begin |
---|
| 1021 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 1022 | if(DQ_IN) |
---|
| 1023 | LOW_DONE <= 1; |
---|
| 1024 | if(OD) |
---|
| 1025 | begin |
---|
| 1026 | if(TimeSlotCnt == bit_ts_sample_od) |
---|
| 1027 | if(!First) |
---|
| 1028 | BitRead1 <= DQ_IN; |
---|
| 1029 | else |
---|
| 1030 | BitRead2 <= DQ_IN; |
---|
| 1031 | if(TimeSlotCnt == bit_ts_writezero_high_od) //7 7_25_01 |
---|
| 1032 | OneWireIO <= FirstPassSR; |
---|
| 1033 | end |
---|
| 1034 | else |
---|
| 1035 | begin |
---|
| 1036 | if(((TimeSlotCnt == bit_ts_sample)&&!LLM) || ((TimeSlotCnt == bit_ts_sample_ll)&&LLM)) |
---|
| 1037 | if(!First) |
---|
| 1038 | BitRead1 <= DQ_IN; |
---|
| 1039 | else |
---|
| 1040 | BitRead2 <= DQ_IN; |
---|
| 1041 | if(TimeSlotCnt == bit_ts_writezero_high) |
---|
| 1042 | OneWireIO <= FirstPassSR; |
---|
| 1043 | end |
---|
| 1044 | end |
---|
| 1045 | |
---|
| 1046 | // FirstPassSR decides whether to do another read or to do the |
---|
| 1047 | // bit write. |
---|
| 1048 | FirstPassSR: |
---|
| 1049 | begin |
---|
| 1050 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 1051 | LOW_DONE <= 0; |
---|
| 1052 | if(OD) |
---|
| 1053 | begin |
---|
| 1054 | if(TimeSlotCnt == bit_ts_end_od) |
---|
| 1055 | begin |
---|
| 1056 | TimeSlotCnt <= 0; |
---|
| 1057 | if(!First) |
---|
| 1058 | begin |
---|
| 1059 | First <= 1'b1; |
---|
| 1060 | OneWireIO <= DQLOW; |
---|
| 1061 | end |
---|
| 1062 | else |
---|
| 1063 | begin |
---|
| 1064 | OneWireIO <= WriteBitSR; |
---|
| 1065 | end |
---|
| 1066 | end |
---|
| 1067 | end |
---|
| 1068 | else |
---|
| 1069 | begin |
---|
| 1070 | if(((TimeSlotCnt==bit_ts_end) && !LLM) || ((TimeSlotCnt==bit_ts_end_ll) && LLM)) |
---|
| 1071 | begin |
---|
| 1072 | TimeSlotCnt <= 0; |
---|
| 1073 | if(!First) |
---|
| 1074 | begin |
---|
| 1075 | First <= 1'b1; |
---|
| 1076 | OneWireIO <= DQLOW; |
---|
| 1077 | end |
---|
| 1078 | else |
---|
| 1079 | begin |
---|
| 1080 | OneWireIO <= WriteBitSR; |
---|
| 1081 | end // else: !if(!First) |
---|
| 1082 | end |
---|
| 1083 | end |
---|
| 1084 | end |
---|
| 1085 | |
---|
| 1086 | // WriteBitSR will now determine the bit necessary to write |
---|
| 1087 | // for the Search ROM to proceed. |
---|
| 1088 | WriteBitSR: |
---|
| 1089 | begin |
---|
| 1090 | case({BitRead1,BitRead2}) |
---|
| 1091 | 2'b00: begin |
---|
| 1092 | case(index) |
---|
| 1093 | 0: begin |
---|
| 1094 | BitWrite <= xmit_shiftreg[1]; |
---|
| 1095 | rcvr_shiftreg[0] <= 1'b1; |
---|
| 1096 | end |
---|
| 1097 | 1: begin |
---|
| 1098 | BitWrite <= xmit_shiftreg[2]; |
---|
| 1099 | rcvr_shiftreg[1] <= 1'b1; |
---|
| 1100 | end |
---|
| 1101 | 2: begin |
---|
| 1102 | BitWrite <= xmit_shiftreg[3]; |
---|
| 1103 | rcvr_shiftreg[2] <= 1'b1; |
---|
| 1104 | end |
---|
| 1105 | 3: begin |
---|
| 1106 | BitWrite <= xmit_shiftreg[4]; |
---|
| 1107 | rcvr_shiftreg[3] <= 1'b1; |
---|
| 1108 | end |
---|
| 1109 | 4: begin |
---|
| 1110 | BitWrite <= xmit_shiftreg[5]; |
---|
| 1111 | rcvr_shiftreg[4] <= 1'b1; |
---|
| 1112 | end |
---|
| 1113 | 5: begin |
---|
| 1114 | BitWrite <= xmit_shiftreg[6]; |
---|
| 1115 | rcvr_shiftreg[5] <= 1'b1; |
---|
| 1116 | end |
---|
| 1117 | 6: begin |
---|
| 1118 | BitWrite <= xmit_shiftreg[7]; |
---|
| 1119 | rcvr_shiftreg[6] <= 1'b1; |
---|
| 1120 | end |
---|
| 1121 | 7: begin |
---|
| 1122 | BitWrite <= xmit_shiftreg[0]; |
---|
| 1123 | rcvr_shiftreg[7] <= 1'b1; |
---|
| 1124 | end |
---|
| 1125 | endcase |
---|
| 1126 | end |
---|
| 1127 | 2'b01: begin |
---|
| 1128 | BitWrite <= 1'b0; |
---|
| 1129 | case(index) |
---|
| 1130 | 0: |
---|
| 1131 | rcvr_shiftreg[0] <= 1'b0; |
---|
| 1132 | 1: |
---|
| 1133 | rcvr_shiftreg[1] <= 1'b0; |
---|
| 1134 | 2: |
---|
| 1135 | rcvr_shiftreg[2] <= 1'b0; |
---|
| 1136 | 3: |
---|
| 1137 | rcvr_shiftreg[3] <= 1'b0; |
---|
| 1138 | 4: |
---|
| 1139 | rcvr_shiftreg[4] <= 1'b0; |
---|
| 1140 | 5: |
---|
| 1141 | rcvr_shiftreg[5] <= 1'b0; |
---|
| 1142 | 6: |
---|
| 1143 | rcvr_shiftreg[6] <= 1'b0; |
---|
| 1144 | 7: |
---|
| 1145 | rcvr_shiftreg[7] <= 1'b0; |
---|
| 1146 | endcase |
---|
| 1147 | end |
---|
| 1148 | 2'b10: begin |
---|
| 1149 | BitWrite <= 1'b1; |
---|
| 1150 | case(index) |
---|
| 1151 | 0: |
---|
| 1152 | rcvr_shiftreg[0] <= 1'b0; |
---|
| 1153 | 1: |
---|
| 1154 | rcvr_shiftreg[1] <= 1'b0; |
---|
| 1155 | 2: |
---|
| 1156 | rcvr_shiftreg[2] <= 1'b0; |
---|
| 1157 | 3: |
---|
| 1158 | rcvr_shiftreg[3] <= 1'b0; |
---|
| 1159 | 4: |
---|
| 1160 | rcvr_shiftreg[4] <= 1'b0; |
---|
| 1161 | 5: |
---|
| 1162 | rcvr_shiftreg[5] <= 1'b0; |
---|
| 1163 | 6: |
---|
| 1164 | rcvr_shiftreg[6] <= 1'b0; |
---|
| 1165 | 7: |
---|
| 1166 | rcvr_shiftreg[7] <= 1'b0; |
---|
| 1167 | endcase |
---|
| 1168 | end |
---|
| 1169 | 2'b11: begin |
---|
| 1170 | BitWrite <= 1'b1; |
---|
| 1171 | case(index) |
---|
| 1172 | 0: begin |
---|
| 1173 | rcvr_shiftreg[0] <= 1'b1; |
---|
| 1174 | rcvr_shiftreg[1] <= 1'b1; |
---|
| 1175 | end |
---|
| 1176 | 1: begin |
---|
| 1177 | rcvr_shiftreg[1] <= 1'b1; |
---|
| 1178 | rcvr_shiftreg[2] <= 1'b1; |
---|
| 1179 | end |
---|
| 1180 | 2: begin |
---|
| 1181 | rcvr_shiftreg[2] <= 1'b1; |
---|
| 1182 | rcvr_shiftreg[3] <= 1'b1; |
---|
| 1183 | end |
---|
| 1184 | 3: begin |
---|
| 1185 | rcvr_shiftreg[3] <= 1'b1; |
---|
| 1186 | rcvr_shiftreg[4] <= 1'b1; |
---|
| 1187 | end |
---|
| 1188 | 4: begin |
---|
| 1189 | rcvr_shiftreg[4] <= 1'b1; |
---|
| 1190 | rcvr_shiftreg[5] <= 1'b1; |
---|
| 1191 | end |
---|
| 1192 | 5: begin |
---|
| 1193 | rcvr_shiftreg[5] <= 1'b1; |
---|
| 1194 | rcvr_shiftreg[6] <= 1'b1; |
---|
| 1195 | end |
---|
| 1196 | 6: begin |
---|
| 1197 | rcvr_shiftreg[6] <= 1'b1; |
---|
| 1198 | rcvr_shiftreg[7] <= 1'b1; |
---|
| 1199 | end |
---|
| 1200 | 7: begin |
---|
| 1201 | rcvr_shiftreg[7] <= 1'b1; |
---|
| 1202 | rcvr_shiftreg[0] <= 1'b1; |
---|
| 1203 | end |
---|
| 1204 | endcase |
---|
| 1205 | end |
---|
| 1206 | endcase // case({BitRead1,BitRead2}) |
---|
| 1207 | OneWireIO <= WriteBit; |
---|
| 1208 | end |
---|
| 1209 | |
---|
| 1210 | // WriteBit actually writes the chosen bit to the One Wire bus. |
---|
| 1211 | WriteBit: |
---|
| 1212 | begin |
---|
| 1213 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 1214 | case(index) |
---|
| 1215 | 0: |
---|
| 1216 | rcvr_shiftreg[1] <= BitWrite; |
---|
| 1217 | 1: |
---|
| 1218 | rcvr_shiftreg[2] <= BitWrite; |
---|
| 1219 | 2: |
---|
| 1220 | rcvr_shiftreg[3] <= BitWrite; |
---|
| 1221 | 3: |
---|
| 1222 | rcvr_shiftreg[4] <= BitWrite; |
---|
| 1223 | 4: |
---|
| 1224 | rcvr_shiftreg[5] <= BitWrite; |
---|
| 1225 | 5: |
---|
| 1226 | rcvr_shiftreg[6] <= BitWrite; |
---|
| 1227 | 6: |
---|
| 1228 | rcvr_shiftreg[7] <= BitWrite; |
---|
| 1229 | 7: |
---|
| 1230 | rcvr_shiftreg[0] <= BitWrite; |
---|
| 1231 | endcase |
---|
| 1232 | if(!BitWrite) |
---|
| 1233 | begin |
---|
| 1234 | if(OD) |
---|
| 1235 | OneWireIO <= ODWriteZero; |
---|
| 1236 | else |
---|
| 1237 | OneWireIO <= WriteZero; |
---|
| 1238 | end |
---|
| 1239 | else |
---|
| 1240 | begin |
---|
| 1241 | if(OD && (TimeSlotCnt == bit_ts_writeone_high_od)) |
---|
| 1242 | OneWireIO <= ODWriteOne; |
---|
| 1243 | else if (!LLM && (TimeSlotCnt == bit_ts_writeone_high)) //5 7_25_01 |
---|
| 1244 | OneWireIO <= WriteOne; |
---|
| 1245 | else if (LLM && (TimeSlotCnt == bit_ts_writeone_high_ll)) |
---|
| 1246 | OneWireIO <= WriteOne; |
---|
| 1247 | end |
---|
| 1248 | end |
---|
| 1249 | |
---|
| 1250 | // WaitTS waits until the timeslot is completed, 80us. When done with |
---|
| 1251 | // that timeslot, the index will be incremented. |
---|
| 1252 | WaitTS: |
---|
| 1253 | begin |
---|
| 1254 | SET_IOSHRT <= 0; |
---|
| 1255 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
| 1256 | if(OD) |
---|
| 1257 | begin |
---|
| 1258 | if(TimeSlotCnt == bit_ts_end_od) //11 7_25_01 |
---|
| 1259 | OneWireIO <= IndexInc; |
---|
| 1260 | end |
---|
| 1261 | else |
---|
| 1262 | if(((TimeSlotCnt == bit_ts_end) && !LLM) || ((TimeSlotCnt==bit_ts_end_ll) && LLM)) |
---|
| 1263 | OneWireIO <= IndexInc; |
---|
| 1264 | if(DQ_IN) |
---|
| 1265 | LOW_DONE <= 1; |
---|
| 1266 | end |
---|
| 1267 | |
---|
| 1268 | // IndexInc incs the index by 1 if normal write, by 2 if in SRA |
---|
| 1269 | IndexInc: |
---|
| 1270 | begin |
---|
| 1271 | if(!sr_a) |
---|
| 1272 | index <= index + 1; |
---|
| 1273 | else |
---|
| 1274 | begin |
---|
| 1275 | index <= index + 2; |
---|
| 1276 | First <= 1'b0; |
---|
| 1277 | end |
---|
| 1278 | |
---|
| 1279 | if(BIT_CTL || (index == 8-1 && !sr_a) || (index == 8-2 && sr_a) ) |
---|
| 1280 | begin // Added BIT_CTL - GAG |
---|
| 1281 | byte_done <= 1'b1; |
---|
| 1282 | OneWireIO <= UpdateBuff; |
---|
| 1283 | end |
---|
| 1284 | else |
---|
| 1285 | begin |
---|
| 1286 | if((index == 7-1) && !sr_a) |
---|
| 1287 | last_rcvr_bit <= 1'b1; |
---|
| 1288 | else |
---|
| 1289 | if((index == 6-2) && sr_a) |
---|
| 1290 | last_rcvr_bit <= 1'b1; |
---|
| 1291 | OneWireIO <= DQLOW; |
---|
| 1292 | TimeSlotCnt <= 0; |
---|
| 1293 | end |
---|
| 1294 | |
---|
| 1295 | LOW_DONE <= 0; |
---|
| 1296 | end |
---|
| 1297 | |
---|
| 1298 | UpdateBuff: |
---|
| 1299 | begin |
---|
| 1300 | OneWireIO <= IdleS; |
---|
| 1301 | if(DQ_IN && STP_SPLY) |
---|
| 1302 | LOW_DONE <= 1; |
---|
| 1303 | end |
---|
| 1304 | endcase |
---|
| 1305 | endmodule |
---|