[1166] | 1 | //---------------------------------------------------------------------------- |
---|
| 2 | // user_logic.vhd - module |
---|
| 3 | //---------------------------------------------------------------------------- |
---|
| 4 | // |
---|
| 5 | // *************************************************************************** |
---|
| 6 | // ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. ** |
---|
| 7 | // ** ** |
---|
| 8 | // ** Xilinx, Inc. ** |
---|
| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
---|
| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
---|
| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
---|
| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
---|
| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
---|
| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
---|
| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
---|
| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
---|
| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
---|
| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
---|
| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
---|
| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
---|
| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
---|
| 22 | // ** ** |
---|
| 23 | // *************************************************************************** |
---|
| 24 | // |
---|
| 25 | //---------------------------------------------------------------------------- |
---|
| 26 | // Filename: user_logic.vhd |
---|
| 27 | // Version: 1.04.a |
---|
| 28 | // Description: User logic module. |
---|
| 29 | // Date: Tue Jun 24 12:44:50 2008 (by Create and Import Peripheral Wizard) |
---|
| 30 | // Verilog Standard: Verilog-2001 |
---|
| 31 | //---------------------------------------------------------------------------- |
---|
| 32 | // Naming Conventions: |
---|
| 33 | // active low signals: "*_n" |
---|
| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
---|
| 35 | // reset signals: "rst", "rst_n" |
---|
| 36 | // generics: "C_*" |
---|
| 37 | // user defined types: "*_TYPE" |
---|
| 38 | // state machine next state: "*_ns" |
---|
| 39 | // state machine current state: "*_cs" |
---|
| 40 | // combinatorial signals: "*_com" |
---|
| 41 | // pipelined or register delay signals: "*_d#" |
---|
| 42 | // counter signals: "*cnt*" |
---|
| 43 | // clock enable signals: "*_ce" |
---|
| 44 | // internal version of output port: "*_i" |
---|
| 45 | // device pins: "*_pin" |
---|
| 46 | // ports: "- Names begin with Uppercase" |
---|
| 47 | // processes: "*_PROCESS" |
---|
| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
---|
| 49 | //---------------------------------------------------------------------------- |
---|
| 50 | |
---|
| 51 | module user_logic |
---|
| 52 | ( |
---|
| 53 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
---|
| 54 | //Eight EEPROM one-wire I/O ports (I/O/T control tri-state buffer in higher module) |
---|
| 55 | |
---|
| 56 | DQ0_T, |
---|
| 57 | DQ0_O, |
---|
| 58 | DQ0_I, |
---|
| 59 | |
---|
| 60 | DQ1_T, |
---|
| 61 | DQ1_O, |
---|
| 62 | DQ1_I, |
---|
| 63 | |
---|
| 64 | DQ2_T, |
---|
| 65 | DQ2_O, |
---|
| 66 | DQ2_I, |
---|
| 67 | |
---|
| 68 | DQ3_T, |
---|
| 69 | DQ3_O, |
---|
| 70 | DQ3_I, |
---|
| 71 | |
---|
| 72 | DQ4_T, |
---|
| 73 | DQ4_O, |
---|
| 74 | DQ4_I, |
---|
| 75 | |
---|
| 76 | DQ5_T, |
---|
| 77 | DQ5_O, |
---|
| 78 | DQ5_I, |
---|
| 79 | |
---|
| 80 | DQ6_T, |
---|
| 81 | DQ6_O, |
---|
| 82 | DQ6_I, |
---|
| 83 | |
---|
| 84 | DQ7_T, |
---|
| 85 | DQ7_O, |
---|
| 86 | DQ7_I, |
---|
| 87 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
---|
| 88 | |
---|
| 89 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
---|
| 90 | // -- Bus protocol ports, do not add to or delete |
---|
| 91 | Bus2IP_Clk, // Bus to IP clock |
---|
| 92 | Bus2IP_Reset, // Bus to IP reset |
---|
| 93 | Bus2IP_Addr, // Bus to IP address bus |
---|
| 94 | Bus2IP_CS, // Bus to IP chip select for user logic memory selection |
---|
| 95 | Bus2IP_RNW, // Bus to IP read/not write |
---|
| 96 | Bus2IP_Data, // Bus to IP data bus |
---|
| 97 | Bus2IP_BE, // Bus to IP byte enables |
---|
| 98 | IP2Bus_Data, // IP to Bus data bus |
---|
| 99 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
---|
| 100 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
---|
| 101 | IP2Bus_Error // IP to Bus error response |
---|
| 102 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
---|
| 103 | ); // user_logic |
---|
| 104 | |
---|
| 105 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
---|
| 106 | // --USER parameters added here |
---|
| 107 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
---|
| 108 | |
---|
| 109 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
---|
| 110 | // -- Bus protocol parameters, do not add to or delete |
---|
| 111 | parameter C_SLV_AWIDTH = 32; |
---|
| 112 | parameter C_SLV_DWIDTH = 32; |
---|
| 113 | parameter C_NUM_MEM = 1; |
---|
| 114 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
---|
| 115 | |
---|
| 116 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
---|
| 117 | output DQ0_T; |
---|
| 118 | output DQ1_T; |
---|
| 119 | output DQ2_T; |
---|
| 120 | output DQ3_T; |
---|
| 121 | output DQ4_T; |
---|
| 122 | output DQ5_T; |
---|
| 123 | output DQ6_T; |
---|
| 124 | output DQ7_T; |
---|
| 125 | |
---|
| 126 | output DQ0_O; |
---|
| 127 | output DQ1_O; |
---|
| 128 | output DQ2_O; |
---|
| 129 | output DQ3_O; |
---|
| 130 | output DQ4_O; |
---|
| 131 | output DQ5_O; |
---|
| 132 | output DQ6_O; |
---|
| 133 | output DQ7_O; |
---|
| 134 | |
---|
| 135 | input DQ0_I; |
---|
| 136 | input DQ1_I; |
---|
| 137 | input DQ2_I; |
---|
| 138 | input DQ3_I; |
---|
| 139 | input DQ4_I; |
---|
| 140 | input DQ5_I; |
---|
| 141 | input DQ6_I; |
---|
| 142 | input DQ7_I; |
---|
| 143 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
---|
| 144 | |
---|
| 145 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
---|
| 146 | // -- Bus protocol ports, do not add to or delete |
---|
| 147 | input Bus2IP_Clk; |
---|
| 148 | input Bus2IP_Reset; |
---|
| 149 | input [0 : C_SLV_AWIDTH-1] Bus2IP_Addr; |
---|
| 150 | input [0 : C_NUM_MEM-1] Bus2IP_CS; |
---|
| 151 | input Bus2IP_RNW; |
---|
| 152 | input [0 : C_SLV_DWIDTH-1] Bus2IP_Data; |
---|
| 153 | input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE; |
---|
| 154 | output [0 : C_SLV_DWIDTH-1] IP2Bus_Data; |
---|
| 155 | output IP2Bus_RdAck; |
---|
| 156 | output IP2Bus_WrAck; |
---|
| 157 | output IP2Bus_Error; |
---|
| 158 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
---|
| 159 | |
---|
| 160 | //---------------------------------------------------------------------------- |
---|
| 161 | // Implementation |
---|
| 162 | //---------------------------------------------------------------------------- |
---|
| 163 | |
---|
| 164 | // --USER logic implementation added here |
---|
| 165 | wire [ 7:0] OWM_rd_data; |
---|
| 166 | wire [31:0] OWM_wt_data; |
---|
| 167 | wire [31:0] OWM_addr; |
---|
| 168 | |
---|
| 169 | assign OWM_wt_data = Bus2IP_Data; |
---|
| 170 | assign OWM_addr = Bus2IP_Addr; |
---|
| 171 | |
---|
| 172 | reg [ 2:0] OWM_rdwt_cycle; |
---|
| 173 | reg OWM_wt_n; |
---|
| 174 | reg OWM_rd_n; |
---|
| 175 | reg OWM_rdwt_ack; |
---|
| 176 | reg OWM_toutsup; |
---|
| 177 | |
---|
| 178 | always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset) |
---|
| 179 | begin |
---|
| 180 | |
---|
| 181 | if (Bus2IP_Reset) |
---|
| 182 | begin |
---|
| 183 | |
---|
| 184 | OWM_rdwt_cycle <= 3'b000; |
---|
| 185 | OWM_wt_n <= 1'b1; |
---|
| 186 | OWM_rd_n <= 1'b1; |
---|
| 187 | OWM_rdwt_ack <= 1'b0; |
---|
| 188 | OWM_toutsup <= 1'b0; |
---|
| 189 | |
---|
| 190 | end |
---|
| 191 | |
---|
| 192 | else |
---|
| 193 | begin |
---|
| 194 | |
---|
| 195 | if ( ~Bus2IP_CS) OWM_rdwt_cycle <= 3'b000; |
---|
| 196 | else if (OWM_rdwt_cycle == 3'b111) OWM_rdwt_cycle <= 3'b111; |
---|
| 197 | else OWM_rdwt_cycle <= OWM_rdwt_cycle + 1; |
---|
| 198 | |
---|
| 199 | OWM_wt_n <= ~( Bus2IP_CS & ~Bus2IP_RNW & (OWM_rdwt_cycle == 1) |
---|
| 200 | | Bus2IP_CS & ~Bus2IP_RNW & (OWM_rdwt_cycle == 2) |
---|
| 201 | ); |
---|
| 202 | |
---|
| 203 | OWM_rd_n <= ~( Bus2IP_CS & Bus2IP_RNW & (OWM_rdwt_cycle == 1) |
---|
| 204 | | Bus2IP_CS & Bus2IP_RNW & (OWM_rdwt_cycle == 2) |
---|
| 205 | | Bus2IP_CS & Bus2IP_RNW & (OWM_rdwt_cycle == 3) |
---|
| 206 | | Bus2IP_CS & Bus2IP_RNW & (OWM_rdwt_cycle == 4) |
---|
| 207 | ); |
---|
| 208 | |
---|
| 209 | OWM_rdwt_ack <= Bus2IP_CS & (OWM_rdwt_cycle == 4); |
---|
| 210 | |
---|
| 211 | OWM_toutsup <= ~OWM_toutsup & Bus2IP_CS & (OWM_rdwt_cycle == 0) |
---|
| 212 | | OWM_toutsup & Bus2IP_CS & ~OWM_rdwt_ack; |
---|
| 213 | |
---|
| 214 | end |
---|
| 215 | |
---|
| 216 | end |
---|
| 217 | |
---|
| 218 | // ********** Instantiate the OWM core here... ***************************************** |
---|
| 219 | |
---|
| 220 | wire clk_1us_out; |
---|
| 221 | |
---|
| 222 | //Register the reset signal here |
---|
| 223 | reg Bus2IP_Reset_d1; |
---|
| 224 | always @(posedge Bus2IP_Clk) |
---|
| 225 | begin |
---|
| 226 | Bus2IP_Reset_d1 <= Bus2IP_Reset; |
---|
| 227 | end |
---|
| 228 | |
---|
| 229 | OWM owm_instance |
---|
| 230 | ( |
---|
[1167] | 231 | .ADDRESS(OWM_addr[4:2]), |
---|
[1166] | 232 | .ADS_bar(1'b0), |
---|
| 233 | .CLK(Bus2IP_Clk), |
---|
| 234 | .EN_bar(1'b0), |
---|
| 235 | .MR(Bus2IP_Reset_d1), |
---|
| 236 | .RD_bar(OWM_rd_n), |
---|
| 237 | .WR_bar(OWM_wt_n), |
---|
| 238 | .INTR(), |
---|
| 239 | .STPZ(), |
---|
| 240 | .DATA_IN(OWM_wt_data[7:0]), |
---|
| 241 | .DATA_OUT(OWM_rd_data), |
---|
| 242 | .DQ0_T(DQ0_T), |
---|
| 243 | .DQ0_O(DQ0_O), |
---|
| 244 | .DQ0_I(DQ0_I), |
---|
| 245 | |
---|
| 246 | .DQ1_T(DQ1_T), |
---|
| 247 | .DQ1_O(DQ1_O), |
---|
| 248 | .DQ1_I(DQ1_I), |
---|
| 249 | |
---|
| 250 | .DQ2_T(DQ2_T), |
---|
| 251 | .DQ2_O(DQ2_O), |
---|
| 252 | .DQ2_I(DQ2_I), |
---|
| 253 | |
---|
| 254 | .DQ3_T(DQ3_T), |
---|
| 255 | .DQ3_O(DQ3_O), |
---|
| 256 | .DQ3_I(DQ3_I), |
---|
| 257 | |
---|
| 258 | .DQ4_T(DQ4_T), |
---|
| 259 | .DQ4_O(DQ4_O), |
---|
| 260 | .DQ4_I(DQ4_I), |
---|
| 261 | |
---|
| 262 | .DQ5_T(DQ5_T), |
---|
| 263 | .DQ5_O(DQ5_O), |
---|
| 264 | .DQ5_I(DQ5_I), |
---|
| 265 | |
---|
| 266 | .DQ6_T(DQ6_T), |
---|
| 267 | .DQ6_O(DQ6_O), |
---|
| 268 | .DQ6_I(DQ6_I), |
---|
| 269 | |
---|
| 270 | .DQ7_T(DQ7_T), |
---|
| 271 | .DQ7_O(DQ7_O), |
---|
| 272 | .DQ7_I(DQ7_I) |
---|
| 273 | ); |
---|
| 274 | |
---|
| 275 | // Now connect signals to the OWM peripheral using the following mapping |
---|
| 276 | // (instantiate the OWM core)... |
---|
| 277 | // |
---|
| 278 | // INTR -> IP2Bus_IntrEvent |
---|
| 279 | // DATA_IN -> OWM_wt_data [7:0] |
---|
| 280 | // DATA_OUT -> OWM_rd_data [7:0] |
---|
| 281 | // A -> OWM_addr [2:0] |
---|
| 282 | // ADS -> 1'b0; |
---|
| 283 | // RD -> OWM_rd_n |
---|
| 284 | // WR -> OWM_wt_n |
---|
| 285 | // EN -> 1'b0; |
---|
| 286 | // MR -> Bus2IP_Reset |
---|
| 287 | // CLK -> Bus2IP_Clk |
---|
| 288 | // |
---|
| 289 | // ************************************************************************************* |
---|
| 290 | |
---|
| 291 | /* |
---|
| 292 | reg [31:0] debug; |
---|
| 293 | |
---|
| 294 | always @ (posedge OWM_wt_n or posedge Bus2IP_Reset) |
---|
| 295 | begin |
---|
| 296 | |
---|
| 297 | if (Bus2IP_Reset) |
---|
| 298 | begin |
---|
| 299 | debug <= 32'h00000000; |
---|
| 300 | end |
---|
| 301 | |
---|
| 302 | else |
---|
| 303 | begin |
---|
| 304 | debug <= {Bus2IP_CS,Bus2IP_RNW,OWM_rd_n,13'h0000,OWM_addr [7:0],OWM_wt_data [7:0]} |
---|
| 305 | end |
---|
| 306 | |
---|
| 307 | end |
---|
| 308 | */ |
---|
| 309 | |
---|
| 310 | |
---|
| 311 | assign IP2Bus_Data = {32{OWM_rdwt_ack}} & {24'h000000, OWM_rd_data}; |
---|
| 312 | // assign IP2Bus_Data = {32{OWM_rdwt_ack}} & {16'hFEDC,IP2Bus_Ack,OWM_rdwt_cycle,Bus2IP_Reset,Bus2IP_CS,OWM_wt_n,OWM_rd_n,OWM_rd_data}; |
---|
| 313 | assign IP2Bus_RdAck = OWM_rdwt_ack & Bus2IP_CS & Bus2IP_RNW; |
---|
| 314 | assign IP2Bus_WrAck = OWM_rdwt_ack & Bus2IP_CS & ~Bus2IP_RNW; |
---|
| 315 | |
---|
| 316 | assign IP2Bus_Error = 1'b0; |
---|
| 317 | |
---|
| 318 | //synthesis attribute clock_signal of OWM_wt_n IS no |
---|
| 319 | //synthesis attribute buffer_type of OWM_wt_n IS none |
---|
| 320 | endmodule |
---|