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eeprom.vhd

Last change on this file was 1167, checked in by murphpo, 15 years ago

File size: 26.8 KB

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1	------------------------------------------------------------------------------
2	-- eeprom.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: eeprom.vhd
36	-- Version: 1.04.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Tue Jun 24 12:44:50 2008 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v2_00_a;
66	use proc_common_v2_00_a.proc_common_pkg.all;
67	use proc_common_v2_00_a.ipif_pkg.all;
68
69	library plbv46_slave_single_v1_00_a;
70	use plbv46_slave_single_v1_00_a.plbv46_slave_single;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
77	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
78	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
79	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
80	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
81	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
82	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
83	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
84	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
85	-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
86	-- C_FAMILY -- Xilinx FPGA family
87	-- C_MEM0_BASEADDR -- User memory space 0 base address
88	-- C_MEM0_HIGHADDR -- User memory space 0 high address
89	--
90	-- Definition of Ports:
91	-- SPLB_Clk -- PLB main bus clock
92	-- SPLB_Rst -- PLB main bus reset
93	-- PLB_ABus -- PLB address bus
94	-- PLB_UABus -- PLB upper address bus
95	-- PLB_PAValid -- PLB primary address valid indicator
96	-- PLB_SAValid -- PLB secondary address valid indicator
97	-- PLB_rdPrim -- PLB secondary to primary read request indicator
98	-- PLB_wrPrim -- PLB secondary to primary write request indicator
99	-- PLB_masterID -- PLB current master identifier
100	-- PLB_abort -- PLB abort request indicator
101	-- PLB_busLock -- PLB bus lock
102	-- PLB_RNW -- PLB read/not write
103	-- PLB_BE -- PLB byte enables
104	-- PLB_MSize -- PLB master data bus size
105	-- PLB_size -- PLB transfer size
106	-- PLB_type -- PLB transfer type
107	-- PLB_lockErr -- PLB lock error indicator
108	-- PLB_wrDBus -- PLB write data bus
109	-- PLB_wrBurst -- PLB burst write transfer indicator
110	-- PLB_rdBurst -- PLB burst read transfer indicator
111	-- PLB_wrPendReq -- PLB write pending bus request indicator
112	-- PLB_rdPendReq -- PLB read pending bus request indicator
113	-- PLB_wrPendPri -- PLB write pending request priority
114	-- PLB_rdPendPri -- PLB read pending request priority
115	-- PLB_reqPri -- PLB current request priority
116	-- PLB_TAttribute -- PLB transfer attribute
117	-- Sl_addrAck -- Slave address acknowledge
118	-- Sl_SSize -- Slave data bus size
119	-- Sl_wait -- Slave wait indicator
120	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
121	-- Sl_wrDAck -- Slave write data acknowledge
122	-- Sl_wrComp -- Slave write transfer complete indicator
123	-- Sl_wrBTerm -- Slave terminate write burst transfer
124	-- Sl_rdDBus -- Slave read data bus
125	-- Sl_rdWdAddr -- Slave read word address
126	-- Sl_rdDAck -- Slave read data acknowledge
127	-- Sl_rdComp -- Slave read transfer complete indicator
128	-- Sl_rdBTerm -- Slave terminate read burst transfer
129	-- Sl_MBusy -- Slave busy indicator
130	-- Sl_MWrErr -- Slave write error indicator
131	-- Sl_MRdErr -- Slave read error indicator
132	-- Sl_MIRQ -- Slave interrupt indicator
133	------------------------------------------------------------------------------
134
135	entity eeprom is
136	generic
137	(
138	-- ADD USER GENERICS BELOW THIS LINE ---------------
139	--USER generics added here
140	-- ADD USER GENERICS ABOVE THIS LINE ---------------
141
142	-- DO NOT EDIT BELOW THIS LINE ---------------------
143	-- Bus protocol parameters, do not add to or delete
144	C_SPLB_AWIDTH : integer := 32;
145	C_SPLB_DWIDTH : integer := 128;
146	C_SPLB_NUM_MASTERS : integer := 8;
147	C_SPLB_MID_WIDTH : integer := 3;
148	C_SPLB_NATIVE_DWIDTH : integer := 32;
149	C_SPLB_P2P : integer := 0;
150	C_SPLB_SUPPORT_BURSTS : integer := 0;
151	C_SPLB_SMALLEST_MASTER : integer := 32;
152	C_SPLB_CLK_PERIOD_PS : integer := 10000;
153	C_INCLUDE_DPHASE_TIMER : integer := 0;
154	C_FAMILY : string := "virtex5";
155	C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
156	C_MEM0_HIGHADDR : std_logic_vector := X"00000000"
157	-- DO NOT EDIT ABOVE THIS LINE ---------------------
158	);
159	port
160	(
161	-- ADD USER PORTS BELOW THIS LINE ------------------
162	DQ0_T : out std_logic;
163	DQ0_O : out std_logic;
164	DQ0_I : in std_logic;
165
166	DQ1_T : out std_logic;
167	DQ1_O : out std_logic;
168	DQ1_I : in std_logic;
169
170	DQ2_T : out std_logic;
171	DQ2_O : out std_logic;
172	DQ2_I : in std_logic;
173
174	DQ3_T : out std_logic;
175	DQ3_O : out std_logic;
176	DQ3_I : in std_logic;
177
178	DQ4_T : out std_logic;
179	DQ4_O : out std_logic;
180	DQ4_I : in std_logic;
181
182	DQ5_T : out std_logic;
183	DQ5_O : out std_logic;
184	DQ5_I : in std_logic;
185
186	DQ6_T : out std_logic;
187	DQ6_O : out std_logic;
188	DQ6_I : in std_logic;
189
190	DQ7_T : out std_logic;
191	DQ7_O : out std_logic;
192	DQ7_I : in std_logic;
193	-- ADD USER PORTS ABOVE THIS LINE ------------------
194
195	-- DO NOT EDIT BELOW THIS LINE ---------------------
196	-- Bus protocol ports, do not add to or delete
197	SPLB_Clk : in std_logic;
198	SPLB_Rst : in std_logic;
199	PLB_ABus : in std_logic_vector(0 to 31);
200	PLB_UABus : in std_logic_vector(0 to 31);
201	PLB_PAValid : in std_logic;
202	PLB_SAValid : in std_logic;
203	PLB_rdPrim : in std_logic;
204	PLB_wrPrim : in std_logic;
205	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
206	PLB_abort : in std_logic;
207	PLB_busLock : in std_logic;
208	PLB_RNW : in std_logic;
209	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
210	PLB_MSize : in std_logic_vector(0 to 1);
211	PLB_size : in std_logic_vector(0 to 3);
212	PLB_type : in std_logic_vector(0 to 2);
213	PLB_lockErr : in std_logic;
214	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
215	PLB_wrBurst : in std_logic;
216	PLB_rdBurst : in std_logic;
217	PLB_wrPendReq : in std_logic;
218	PLB_rdPendReq : in std_logic;
219	PLB_wrPendPri : in std_logic_vector(0 to 1);
220	PLB_rdPendPri : in std_logic_vector(0 to 1);
221	PLB_reqPri : in std_logic_vector(0 to 1);
222	PLB_TAttribute : in std_logic_vector(0 to 15);
223	Sl_addrAck : out std_logic;
224	Sl_SSize : out std_logic_vector(0 to 1);
225	Sl_wait : out std_logic;
226	Sl_rearbitrate : out std_logic;
227	Sl_wrDAck : out std_logic;
228	Sl_wrComp : out std_logic;
229	Sl_wrBTerm : out std_logic;
230	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
231	Sl_rdWdAddr : out std_logic_vector(0 to 3);
232	Sl_rdDAck : out std_logic;
233	Sl_rdComp : out std_logic;
234	Sl_rdBTerm : out std_logic;
235	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
236	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
237	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
238	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
239	-- DO NOT EDIT ABOVE THIS LINE ---------------------
240	);
241
242	attribute SIGIS : string;
243	attribute SIGIS of SPLB_Clk : signal is "CLK";
244	attribute SIGIS of SPLB_Rst : signal is "RST";
245
246	end entity eeprom;
247
248	------------------------------------------------------------------------------
249	-- Architecture section
250	------------------------------------------------------------------------------
251
252	architecture IMP of eeprom is
253
254	------------------------------------------
255	-- Array of base/high address pairs for each address range
256	------------------------------------------
257	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
258
259	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
260	(
261	ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address
262	ZERO_ADDR_PAD & C_MEM0_HIGHADDR -- user logic memory space 0 high address
263	);
264
265	------------------------------------------
266	-- Array of desired number of chip enables for each address range
267	------------------------------------------
268	constant USER_NUM_MEM : integer := 1;
269
270	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
271	(
272	0 => 1 -- number of ce for user logic memory space 0 (always 1 chip enable)
273	);
274
275	------------------------------------------
276	-- Ratio of bus clock to core clock (for use in dual clock systems)
277	-- 1 = ratio is 1:1
278	-- 2 = ratio is 2:1
279	------------------------------------------
280	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
281
282	------------------------------------------
283	-- Width of the slave data bus (32 only)
284	------------------------------------------
285	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
286
287	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
288
289	------------------------------------------
290	-- Width of the slave address bus (32 only)
291	------------------------------------------
292	constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
293
294	------------------------------------------
295	-- Index for CS/CE
296	------------------------------------------
297	constant USER_MEM0_CS_INDEX : integer := 0;
298
299	constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
300
301	------------------------------------------
302	-- IP Interconnect (IPIC) signal declarations
303	------------------------------------------
304	signal ipif_Bus2IP_Clk : std_logic;
305	signal ipif_Bus2IP_Reset : std_logic;
306	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
307	signal ipif_IP2Bus_WrAck : std_logic;
308	signal ipif_IP2Bus_RdAck : std_logic;
309	signal ipif_IP2Bus_Error : std_logic;
310	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
311	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
312	signal ipif_Bus2IP_RNW : std_logic;
313	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
314	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
315	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
316	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
317	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
318	signal user_IP2Bus_RdAck : std_logic;
319	signal user_IP2Bus_WrAck : std_logic;
320	signal user_IP2Bus_Error : std_logic;
321
322	------------------------------------------
323	-- Component declaration for verilog user logic
324	------------------------------------------
325	component user_logic is
326	generic
327	(
328	-- ADD USER GENERICS BELOW THIS LINE ---------------
329	--USER generics added here
330	-- ADD USER GENERICS ABOVE THIS LINE ---------------
331
332	-- DO NOT EDIT BELOW THIS LINE ---------------------
333	-- Bus protocol parameters, do not add to or delete
334	C_SLV_AWIDTH : integer := 32;
335	C_SLV_DWIDTH : integer := 32;
336	C_NUM_MEM : integer := 1
337	-- DO NOT EDIT ABOVE THIS LINE ---------------------
338	);
339	port
340	(
341	-- ADD USER PORTS BELOW THIS LINE ------------------
342	DQ0_T : out std_logic;
343	DQ0_O : out std_logic;
344	DQ0_I : in std_logic;
345
346	DQ1_T : out std_logic;
347	DQ1_O : out std_logic;
348	DQ1_I : in std_logic;
349
350	DQ2_T : out std_logic;
351	DQ2_O : out std_logic;
352	DQ2_I : in std_logic;
353
354	DQ3_T : out std_logic;
355	DQ3_O : out std_logic;
356	DQ3_I : in std_logic;
357
358	DQ4_T : out std_logic;
359	DQ4_O : out std_logic;
360	DQ4_I : in std_logic;
361
362	DQ5_T : out std_logic;
363	DQ5_O : out std_logic;
364	DQ5_I : in std_logic;
365
366	DQ6_T : out std_logic;
367	DQ6_O : out std_logic;
368	DQ6_I : in std_logic;
369
370	DQ7_T : out std_logic;
371	DQ7_O : out std_logic;
372	DQ7_I : in std_logic;
373	-- ADD USER PORTS ABOVE THIS LINE ------------------
374
375	-- DO NOT EDIT BELOW THIS LINE ---------------------
376	-- Bus protocol ports, do not add to or delete
377	Bus2IP_Clk : in std_logic;
378	Bus2IP_Reset : in std_logic;
379	Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1);
380	Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1);
381	Bus2IP_RNW : in std_logic;
382	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
383	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
384	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
385	IP2Bus_RdAck : out std_logic;
386	IP2Bus_WrAck : out std_logic;
387	IP2Bus_Error : out std_logic
388	-- DO NOT EDIT ABOVE THIS LINE ---------------------
389	);
390	end component user_logic;
391
392	begin
393
394	------------------------------------------
395	-- instantiate plbv46_slave_single
396	------------------------------------------
397	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
398	generic map
399	(
400	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
401	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
402	C_SPLB_P2P => C_SPLB_P2P,
403	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
404	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
405	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
406	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
407	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
408	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
409	C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
410	C_FAMILY => C_FAMILY
411	)
412	port map
413	(
414	SPLB_Clk => SPLB_Clk,
415	SPLB_Rst => SPLB_Rst,
416	PLB_ABus => PLB_ABus,
417	PLB_UABus => PLB_UABus,
418	PLB_PAValid => PLB_PAValid,
419	PLB_SAValid => PLB_SAValid,
420	PLB_rdPrim => PLB_rdPrim,
421	PLB_wrPrim => PLB_wrPrim,
422	PLB_masterID => PLB_masterID,
423	PLB_abort => PLB_abort,
424	PLB_busLock => PLB_busLock,
425	PLB_RNW => PLB_RNW,
426	PLB_BE => PLB_BE,
427	PLB_MSize => PLB_MSize,
428	PLB_size => PLB_size,
429	PLB_type => PLB_type,
430	PLB_lockErr => PLB_lockErr,
431	PLB_wrDBus => PLB_wrDBus,
432	PLB_wrBurst => PLB_wrBurst,
433	PLB_rdBurst => PLB_rdBurst,
434	PLB_wrPendReq => PLB_wrPendReq,
435	PLB_rdPendReq => PLB_rdPendReq,
436	PLB_wrPendPri => PLB_wrPendPri,
437	PLB_rdPendPri => PLB_rdPendPri,
438	PLB_reqPri => PLB_reqPri,
439	PLB_TAttribute => PLB_TAttribute,
440	Sl_addrAck => Sl_addrAck,
441	Sl_SSize => Sl_SSize,
442	Sl_wait => Sl_wait,
443	Sl_rearbitrate => Sl_rearbitrate,
444	Sl_wrDAck => Sl_wrDAck,
445	Sl_wrComp => Sl_wrComp,
446	Sl_wrBTerm => Sl_wrBTerm,
447	Sl_rdDBus => Sl_rdDBus,
448	Sl_rdWdAddr => Sl_rdWdAddr,
449	Sl_rdDAck => Sl_rdDAck,
450	Sl_rdComp => Sl_rdComp,
451	Sl_rdBTerm => Sl_rdBTerm,
452	Sl_MBusy => Sl_MBusy,
453	Sl_MWrErr => Sl_MWrErr,
454	Sl_MRdErr => Sl_MRdErr,
455	Sl_MIRQ => Sl_MIRQ,
456	Bus2IP_Clk => ipif_Bus2IP_Clk,
457	Bus2IP_Reset => ipif_Bus2IP_Reset,
458	IP2Bus_Data => ipif_IP2Bus_Data,
459	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
460	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
461	IP2Bus_Error => ipif_IP2Bus_Error,
462	Bus2IP_Addr => ipif_Bus2IP_Addr,
463	Bus2IP_Data => ipif_Bus2IP_Data,
464	Bus2IP_RNW => ipif_Bus2IP_RNW,
465	Bus2IP_BE => ipif_Bus2IP_BE,
466	Bus2IP_CS => ipif_Bus2IP_CS,
467	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
468	Bus2IP_WrCE => ipif_Bus2IP_WrCE
469	);
470
471	------------------------------------------
472	-- instantiate User Logic
473	------------------------------------------
474	USER_LOGIC_I : component user_logic
475	generic map
476	(
477	-- MAP USER GENERICS BELOW THIS LINE ---------------
478	--USER generics mapped here
479	-- MAP USER GENERICS ABOVE THIS LINE ---------------
480
481	C_SLV_AWIDTH => USER_SLV_AWIDTH,
482	C_SLV_DWIDTH => USER_SLV_DWIDTH,
483	C_NUM_MEM => USER_NUM_MEM
484	)
485	port map
486	(
487	-- MAP USER PORTS BELOW THIS LINE ------------------
488	DQ0_T => DQ0_T,
489	DQ0_O => DQ0_O,
490	DQ0_I => DQ0_I,
491
492	DQ1_T => DQ1_T,
493	DQ1_O => DQ1_O,
494	DQ1_I => DQ1_I,
495
496	DQ2_T => DQ2_T,
497	DQ2_O => DQ2_O,
498	DQ2_I => DQ2_I,
499
500	DQ3_T => DQ3_T,
501	DQ3_O => DQ3_O,
502	DQ3_I => DQ3_I,
503
504	DQ4_T => DQ4_T,
505	DQ4_O => DQ4_O,
506	DQ4_I => DQ4_I,
507
508	DQ5_T => DQ5_T,
509	DQ5_O => DQ5_O,
510	DQ5_I => DQ5_I,
511
512	DQ6_T => DQ6_T,
513	DQ6_O => DQ6_O,
514	DQ6_I => DQ6_I,
515
516	DQ7_T => DQ7_T,
517	DQ7_O => DQ7_O,
518	DQ7_I => DQ7_I,
519	-- MAP USER PORTS ABOVE THIS LINE ------------------
520
521	Bus2IP_Clk => ipif_Bus2IP_Clk,
522	Bus2IP_Reset => ipif_Bus2IP_Reset,
523	Bus2IP_Addr => ipif_Bus2IP_Addr,
524	Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
525	Bus2IP_RNW => ipif_Bus2IP_RNW,
526	Bus2IP_Data => ipif_Bus2IP_Data,
527	Bus2IP_BE => ipif_Bus2IP_BE,
528	IP2Bus_Data => user_IP2Bus_Data,
529	IP2Bus_RdAck => user_IP2Bus_RdAck,
530	IP2Bus_WrAck => user_IP2Bus_WrAck,
531	IP2Bus_Error => user_IP2Bus_Error
532	);
533
534	------------------------------------------
535	-- connect internal signals
536	------------------------------------------
537	ipif_IP2Bus_Data <= user_IP2Bus_Data;
538	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
539	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
540	ipif_IP2Bus_Error <= user_IP2Bus_Error;
541
542	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/eeprom_v1_07_a/hdl/vhdl/eeprom.vhd

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