source: PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_a/hdl/verilog/fmc_bb_4da_bridge.v

module fmc_bb_4da_bridge
(
    //Ref clk for IDELAYCTRL
    input clk200,
    
    //Input sampling clocks - User design must provide these clock signals
    
    // sys_samp_clk_Tx requirements:
    //  -Synchronous to and valid for capturing user_RFx_TXD ports
    //  -Frequency must match AD9963 input data rate configuration (DAC clock / interpolation rate)
    input sys_samp_clk,

    // sys_samp_clk_Tx_90 must be 90 degree phase shift of sys_samp_clk_Tx (used to generate TXCLK output)
    input sys_samp_clk_90,

    input [0:11] user_DAC_A,
    input [0:11] user_DAC_B,
    input [0:11] user_DAC_C,
    input [0:11] user_DAC_D,
    
    output [0:13] DAC_AB_DB,
    output [0:13] DAC_CD_DB,
    output DAC_AB_CLK,
    output DAC_CD_CLK
);

parameter C_FAMILY = "virtex6";
parameter INCLUDE_IDELAYCTRL = 1;

parameter DAC_AB_CLK_ODELAY_TAPS = 31;
parameter DAC_CD_CLK_ODELAY_TAPS = 31;

generate
if(INCLUDE_IDELAYCTRL==1) begin
IDELAYCTRL IDELAYCTRL_inst (
      .RDY(),       // 1-bit Ready output
      .REFCLK(clk200), // 1-bit Reference clock input
      .RST(1'b0)        // 1-bit Reset input
   );
end
endgenerate

/* DAC Clocks are delayed here to give enough separation from clock and data transitions
   Signal flow is: (OPADs inferred by tools, when user ties DAC_ ports to top-level ports)
   CLK: sys_samp_clk -> ODDR -> DAC_X_CLK_unDelayed -> ODELAY -> DAC_X_CLK PAD
   Data: user_DAC_X -> ODDR -> DAC_X_DB PADs
*/
ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
    .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
    .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) OBUFDDR_DACCLK_AB (
    .Q(DAC_AB_CLK),   // 1-bit DDR output
    .C(sys_samp_clk_90),   // 1-bit clock input
    .CE(1'b1), // 1-bit clock enable input
    .D1(1'b1), // 1-bit data input (positive edge)
    .D2(1'b0), // 1-bit data input (negative edge)
    .R(1'b0),   // 1-bit reset
    .S(1'b0)    // 1-bit set
);

ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
    .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
    .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) OBUFDDR_DACCLK_CD (
    .Q(DAC_CD_CLK),   // 1-bit DDR output
    .C(sys_samp_clk_90),   // 1-bit clock input
    .CE(1'b1), // 1-bit clock enable input
    .D1(1'b1), // 1-bit data input (positive edge)
    .D2(1'b0), // 1-bit data input (negative edge)
    .R(1'b0),   // 1-bit reset
    .S(1'b0)    // 1-bit set
);

//Instantiate all the DDR registers for DAC DB outputs
// User-supplied 12-bit values become 12MSB of 14-bit outputs
// 2 LSB tied to zero (NC on AD9116)
genvar ii;
generate
    for(ii=0; ii<12; ii=ii+1) begin: DDR_REGS_RFA_RFB
        ODDR #(
            .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
            .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
            .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
        ) ODDR_DAC_AB_DB (
            .Q(DAC_AB_DB[ii]),   // 1-bit DDR output
            .C(sys_samp_clk),   // 1-bit clock input
            .CE(1'b1), // 1-bit clock enable input
            .D1(user_DAC_A[ii]), // 1-bit data input (positive edge)
            .D2(user_DAC_B[ii]), // 1-bit data input (negative edge)
            .R(1'b0),   // 1-bit reset
            .S(1'b0)    // 1-bit set
        );
        ODDR #(
            .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
            .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
            .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
        ) ODDR_DAC_CD_DB (
            .Q(DAC_CD_DB[ii]),   // 1-bit DDR output
            .C(sys_samp_clk),   // 1-bit clock input
            .CE(1'b1), // 1-bit clock enable input
            .D1(user_DAC_C[ii]), // 1-bit data input (positive edge)
            .D2(user_DAC_D[ii]), // 1-bit data input (negative edge)
            .R(1'b0),   // 1-bit reset
            .S(1'b0)    // 1-bit set
        );
        end
endgenerate

//Just in case a 4DA board gets built with the AD9117 (14-bit DACs) in the future, ensure the 2MBS are tied low
// Actual users for the AD9117 should modify this core to have 14-bit user ports (future feature, maybe)
assign DAC_AB_DB[12:13] = 2'b0;
assign DAC_CD_DB[12:13] = 2'b0;

endmodule