source: PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_b/hdl/verilog/fmc_bb_4da_bridge.v

module fmc_bb_4da_bridge
(
    //Input sampling clocks - User design must provide these clock signals
    
    // sys_samp_clk_Tx requirements:
    //  -Synchronous to and valid for capturing user_DAC_x ports
    input sys_samp_clk,

    // sys_samp_clk_Tx_90 must be 90 degree phase shift of sys_samp_clk (used to generate DAC clock outputs)
    input sys_samp_clk_90,

    input [0:USER_DAC_A_BITS-1] user_DAC_A,
    input [0:USER_DAC_B_BITS-1] user_DAC_B,
    input [0:USER_DAC_C_BITS-1] user_DAC_C,
    input [0:USER_DAC_D_BITS-1] user_DAC_D,
    
    output [0:13] DAC_AB_DB,
    output [0:13] DAC_CD_DB,
    output DAC_AB_CLK,
    output DAC_CD_CLK,
    
    output DAC_AB_PINMD,
    output DAC_AB_CLKMD,
    output DAC_AB_FORMAT,
    output DAC_AB_PWDN,

    output DAC_CD_PINMD,
    output DAC_CD_CLKMD,
    output DAC_CD_FORMAT,
    output DAC_CD_PWDN
);

parameter USER_DAC_A_BITS = 12;
parameter USER_DAC_B_BITS = 12;
parameter USER_DAC_C_BITS = 12;
parameter USER_DAC_D_BITS = 12;

parameter C_FAMILY = "virtex6";

//Tie the control signals to sensible defaults
// With these values the DACs will always be running with 2's complement input data
assign DAC_AB_PINMD = 1'b1;
assign DAC_AB_CLKMD = 1'b0;
assign DAC_AB_FORMAT = 1'b1;
assign DAC_AB_PWDN = 1'b0;

assign DAC_CD_PINMD = 1'b1;
assign DAC_CD_CLKMD = 1'b0;
assign DAC_CD_FORMAT = 1'b1;
assign DAC_CD_PWDN = 1'b0;

//Output the DAC clocks using ODDRs, to minimize skew between clock and data outputs
ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
    .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
    .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) OBUFDDR_DACCLK_AB (
    .Q(DAC_AB_CLK),   // 1-bit DDR output
    .C(sys_samp_clk_90),   // 1-bit clock input
    .CE(1'b1), // 1-bit clock enable input
    .D1(1'b1), // 1-bit data input (positive edge)
    .D2(1'b0), // 1-bit data input (negative edge)
    .R(1'b0),   // 1-bit reset
    .S(1'b0)    // 1-bit set
);

ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
    .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
    .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) OBUFDDR_DACCLK_CD (
    .Q(DAC_CD_CLK),   // 1-bit DDR output
    .C(sys_samp_clk_90),   // 1-bit clock input
    .CE(1'b1), // 1-bit clock enable input
    .D1(1'b1), // 1-bit data input (positive edge)
    .D2(1'b0), // 1-bit data input (negative edge)
    .R(1'b0),   // 1-bit reset
    .S(1'b0)    // 1-bit set
);

//Create intermediate nets to tie unused bits to zero
// Params USER_DAC_x_BITS must be <= 16
wire [0:17] user_DAC_A_pad;
wire [0:17] user_DAC_B_pad;
wire [0:17] user_DAC_C_pad;
wire [0:17] user_DAC_D_pad;

assign user_DAC_A_pad[0:USER_DAC_A_BITS-1] = user_DAC_A;
assign user_DAC_A_pad[USER_DAC_A_BITS:17] = 0;

assign user_DAC_B_pad[0:USER_DAC_B_BITS-1] = user_DAC_B;
assign user_DAC_B_pad[USER_DAC_B_BITS:17] = 0;

assign user_DAC_C_pad[0:USER_DAC_C_BITS-1] = user_DAC_C;
assign user_DAC_C_pad[USER_DAC_C_BITS:17] = 0;

assign user_DAC_D_pad[0:USER_DAC_D_BITS-1] = user_DAC_D;
assign user_DAC_D_pad[USER_DAC_D_BITS:17] = 0;

//Instantiate all the DDR registers for DAC DB outputs
// User-supplied values become MSB of 14-bit outputs
// Unused LSB tied to zero
// 14-bit outputs are used in case FMC-BB-4DA has AD9117
genvar ii;
generate
    for(ii=0; ii<14; ii=ii+1) begin: DDR_REGS_RFA_RFB
        ODDR #(
            .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
            .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
            .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
        ) ODDR_DAC_AB_DB (
            .Q(DAC_AB_DB[ii]),   // 1-bit DDR output
            .C(sys_samp_clk),   // 1-bit clock input
            .CE(1'b1), // 1-bit clock enable input
            .D1(user_DAC_A_pad[ii]), // 1-bit data input (positive edge)
            .D2(user_DAC_B_pad[ii]), // 1-bit data input (negative edge)
            .R(1'b0),   // 1-bit reset
            .S(1'b0)    // 1-bit set
        );
        ODDR #(
            .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
            .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
            .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
        ) ODDR_DAC_CD_DB (
            .Q(DAC_CD_DB[ii]),   // 1-bit DDR output
            .C(sys_samp_clk),   // 1-bit clock input
            .CE(1'b1), // 1-bit clock enable input
            .D1(user_DAC_C_pad[ii]), // 1-bit data input (positive edge)
            .D2(user_DAC_D_pad[ii]), // 1-bit data input (negative edge)
            .R(1'b0),   // 1-bit reset
            .S(1'b0)    // 1-bit set
        );
        end
endgenerate

endmodule