1 | |
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2 | ################################################################### |
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3 | # Copyright (c) 2006 Rice University |
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4 | # All Rights Reserved |
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5 | # This code is covered by the Rice-WARP license |
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6 | # See http://warp.rice.edu/license/ for details |
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7 | ################################################################### |
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8 | |
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9 | BEGIN radio_bridge |
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10 | |
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11 | ## Peripheral Options |
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12 | OPTION IPTYPE = PERIPHERAL |
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13 | OPTION IMP_NETLIST = TRUE |
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14 | OPTION HDL = VERILOG |
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15 | OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE) |
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16 | OPTION USAGE_LEVEL = BASE_USER |
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17 | OPTION DESC = WARP Radio Board Bridge Core |
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18 | OPTION LONG_DESC = "Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards." |
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19 | OPTION IP_GROUP = USER |
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20 | OPTION RUN_NGCBUILD = FALSE |
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21 | OPTION STYLE = HDL |
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22 | |
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23 | IO_INTERFACE IO_IF = ext_radio_board_ports, IO_TYPE = WARP_RADIOBRIDGE_V1 |
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24 | IO_INTERFACE IO_IF = user_ports, IO_TYPE = WARP_RADIOBRIDGE_V1 |
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25 | |
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26 | BUS_INTERFACE BUS = RC2RB_RAD, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = TARGET |
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27 | |
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28 | PARAMETER C_FAMILY = virtex2p, DT = STRING |
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29 | |
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30 | ## Ports |
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31 | #################################################################################### |
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32 | ## User Ports |
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33 | ## The user must connect sources/sinks to these ports in XPS in order to use |
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34 | ## the radio board. The rest of the board's connections are made automatically |
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35 | #################################################################################### |
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36 | PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IF = user_ports, IO_IS = userADCI |
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37 | PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IF = user_ports, IO_IS = userADCQ |
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38 | |
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39 | PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IF = user_ports, IO_IS = userDACI |
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40 | PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IF = user_ports, IO_IS = userDACQ |
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41 | |
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42 | PORT user_RxRF_gain = "", DIR = I, VEC = [0:1], IO_IF = user_ports, IO_IS = userRxRFG |
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43 | PORT user_RxBB_gain = "", DIR = I, VEC = [0:4], IO_IF = user_ports, IO_IS = userRxBBG |
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44 | |
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45 | |
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46 | |
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47 | PORT user_TxModelStart = "", DIR = O, IO_IF = user_ports, IO_IS = user_txMdlStart |
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48 | |
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49 | PORT user_RSSI_ADC_clk = "", DIR = I, IO_IF = user_ports, IO_IS = user_RSSICLK |
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50 | |
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51 | PORT user_RSSI_ADC_D = "", DIR = O, VEC = [0:9], IO_IF = user_ports, IO_IS = user_RSSID |
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52 | |
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53 | PORT user_EEPROM_IO_T = "", DIR = I, IO_IF = user_ports, IO_IS = user_eepromIOT |
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54 | PORT user_EEPROM_IO_O = "", DIR = I , IO_IF = user_ports, IO_IS = user_eepromIOO |
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55 | PORT user_EEPROM_IO_I = "", DIR = O , IO_IF = user_ports, IO_IS = user_eepromIOI |
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56 | |
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57 | PORT user_SHDN_external = "", DIR = I, IO_IF = user_ports, IO_IS = user_SHDNext |
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58 | PORT user_RxEn_external = "", DIR = I, IO_IF = user_ports, IO_IS = user_RXENext |
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59 | PORT user_TxEn_external = "", DIR = I, IO_IF = user_ports, IO_IS = user_TXENext |
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60 | PORT user_RxHP_external = "", DIR = I, IO_IF = user_ports, IO_IS = user_RXHPext |
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61 | |
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62 | #This clock must match the sampling clock at the Radio Board |
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63 | # Users must assign it to the proper net in XPS (no way to know here what that net will be called) |
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64 | PORT converter_clock_in = "", DIR = I, SIGIS = CLK, CLK_FREQ = 40000000, IO_IF = user_ports, ASSIGNMENT = REQUIRE, IO_IS = user_converterClk |
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65 | #################################################################################### |
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66 | |
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67 | #### |
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68 | # Radio Bridge <-> Radio Board ports |
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69 | #### |
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70 | PORT converter_clock_out = "", DIR = O, SIGIS = CLK, IO_IF = ext_radio_board_ports, IO_IS = convClkOut |
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71 | |
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72 | PORT radio_RSSI_ADC_clk = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_rssi_adc_clk |
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73 | |
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74 | PORT radio_DAC_I = "", DIR = O, VEC = [15:0], IO_IS = radioDACI, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports, IO_IS = radioDACI |
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75 | PORT radio_DAC_Q = "", DIR = O, VEC = [15:0], IO_IS = radioDACQ, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports, IO_IS = radioDACQ |
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76 | |
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77 | PORT radio_ADC_I = "", DIR = I, VEC = [13:0], IO_IS = radioADCI, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports, IO_IS = radioADCI |
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78 | PORT radio_ADC_Q = "", DIR = I, VEC = [13:0], IO_IS = radioADCQ, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports, IO_IS = radioADCQ |
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79 | |
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80 | PORT radio_B = "", DIR = O, VEC = [6:0], IO_IS = radioGain, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports |
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81 | |
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82 | PORT radio_ANTSW = "", DIR = O, VEC = [1:0], IO_IS = b2r_ANTSW, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports |
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83 | PORT radio_LED = "", DIR = O, VEC = [2:0], IO_IS = b2r_LED, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports |
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84 | PORT radio_DIPSW = "", DIR = I, VEC = [3:0], IO_IS = b2r_DIPSW, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports |
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85 | PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [9:0], IO_IS = b2r_RSSI_ADC_D, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports |
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86 | |
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87 | PORT radio_EEPROM_IO = "", DIR = IO, THREE_STATE = FALSE, IOB_STATE = BUF, IO_IF = ext_radio_board_ports, IO_IS = radio_eepromIO |
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88 | |
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89 | PORT radio_spi_clk = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_SCLK |
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90 | PORT radio_spi_data = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_SDO |
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91 | PORT radio_spi_cs = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_SCS |
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92 | PORT radio_SHDN = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_SHDN |
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93 | PORT radio_TxEn = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_TXEN |
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94 | PORT radio_RxEn = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RXEN |
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95 | PORT radio_RxHP = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RXHP |
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96 | PORT radio_24PA = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_24PA |
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97 | PORT radio_5PA = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_5PA |
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98 | PORT radio_RX_ADC_DCS = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCDCS |
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99 | PORT radio_RX_ADC_DFS = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCDFS |
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100 | PORT radio_RX_ADC_PWDNA = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCPWDNA |
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101 | PORT radio_RX_ADC_PWDNB = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCPWDNB |
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102 | PORT radio_RSSI_ADC_CLAMP = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RSSIADCCLAMP |
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103 | PORT radio_RSSI_ADC_HIZ = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RSSIADCHIZ |
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104 | PORT radio_RSSI_ADC_SLEEP = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RSSIADCSLEEP |
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105 | PORT radio_LD = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_LD |
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106 | PORT radio_RX_ADC_OTRA = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCOTRA |
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107 | PORT radio_RX_ADC_OTRB = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCOTRB |
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108 | PORT radio_RSSI_ADC_OTR = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_RSSIOTR |
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109 | PORT radio_DAC_PLL_LOCK = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_DACLOCK |
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110 | PORT radio_DAC_RESET = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_DACRESET |
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111 | PORT dac_spi_data = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = rc_dac_sdo |
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112 | PORT dac_spi_cs = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = rc_dac_scs |
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113 | PORT dac_spi_clk = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = rc_dac_sclk |
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114 | |
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115 | ### |
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116 | # Radio Controller <-> Radio Bridge ports |
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117 | ### |
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118 | PORT controller_logic_clk = "controller_logic_clk", DIR = I, BUS = RC2RB_RAD |
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119 | PORT controller_spi_clk = "controller_spi_clk", DIR = I, BUS = RC2RB_RAD |
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120 | PORT controller_spi_data = "controller_spi_data", DIR = I, BUS = RC2RB_RAD |
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121 | |
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122 | PORT controller_radio_cs = "controller_radio_cs", DIR = I, BUS = RC2RB_RAD |
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123 | PORT controller_dac_cs = "controller_dac_cs", DIR = I, BUS = RC2RB_RAD |
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124 | PORT controller_SHDN = "controller_SHDN", DIR = I, BUS = RC2RB_RAD |
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125 | PORT controller_TxEn = "controller_TxEn", DIR = I, BUS = RC2RB_RAD |
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126 | PORT controller_RxEn = "controller_RxEn", DIR = I, BUS = RC2RB_RAD |
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127 | PORT controller_RxHP = "controller_RxHP", DIR = I, BUS = RC2RB_RAD |
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128 | PORT controller_24PA = "controller_24PA", DIR = I, BUS = RC2RB_RAD |
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129 | PORT controller_5PA = "controller_5PA", DIR = I, BUS = RC2RB_RAD |
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130 | PORT controller_ANTSW = "controller_ANTSW", DIR = I, VEC = [0:1], BUS = RC2RB_RAD |
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131 | PORT controller_LED = "controller_LED", DIR = I, VEC = [0:2], BUS = RC2RB_RAD |
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132 | PORT controller_RX_ADC_DCS = "controller_RX_ADC_DCS", DIR = I, BUS = RC2RB_RAD |
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133 | PORT controller_RX_ADC_DFS = "controller_RX_ADC_DFS", DIR = I, BUS = RC2RB_RAD |
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134 | PORT controller_RX_ADC_OTRA = "controller_RX_ADC_OTRA", DIR = O, BUS = RC2RB_RAD |
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135 | PORT controller_RX_ADC_OTRB = "controller_RX_ADC_OTRB", DIR = O, BUS = RC2RB_RAD |
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136 | PORT controller_RX_ADC_PWDNA = "controller_RX_ADC_PWDNA", DIR = I, BUS = RC2RB_RAD |
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137 | PORT controller_RX_ADC_PWDNB = "controller_RX_ADC_PWDNB", DIR = I, BUS = RC2RB_RAD |
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138 | PORT controller_DIPSW = "controller_DIPSW", DIR = O, VEC = [0:3], BUS = RC2RB_RAD |
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139 | PORT controller_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = I, BUS = RC2RB_RAD |
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140 | PORT controller_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = I, BUS = RC2RB_RAD |
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141 | PORT controller_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = O, BUS = RC2RB_RAD |
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142 | PORT controller_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = I, BUS = RC2RB_RAD |
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143 | PORT controller_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = O, VEC = [0:9], BUS = RC2RB_RAD |
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144 | PORT controller_LD = "controller_LD", DIR = O, BUS = RC2RB_RAD |
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145 | PORT controller_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = O, BUS = RC2RB_RAD |
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146 | PORT controller_DAC_RESET = "controller_DAC_RESET", DIR = I, BUS = RC2RB_RAD |
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147 | PORT controller_SHDN_external = "controller_SHDN_external", DIR = O, BUS = RC2RB_RAD |
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148 | PORT controller_TxEn_external = "controller_TxEn_external", DIR = O, BUS = RC2RB_RAD |
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149 | PORT controller_RxEn_external = "controller_RxEn_external", DIR = O, BUS = RC2RB_RAD |
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150 | PORT controller_RxHP_external = "controller_RxHP_external", DIR = O, BUS = RC2RB_RAD |
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151 | PORT controller_TxStart = "controller_TxStart", DIR = I, BUS = RC2RB_RAD |
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152 | PORT user_Tx_gain = "controller_Tx_gain", DIR = I, VEC = [0:5], BUS = RC2RB_RAD |
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153 | END |
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