1 | ////////////////////////////////////////////////////////// |
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2 | // Copyright (c) 2006 Rice University // |
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3 | // All Rights Reserved // |
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4 | // This code is covered by the Rice-WARP license // |
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5 | // See http://warp.rice.edu/license/ for details // |
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6 | ////////////////////////////////////////////////////////// |
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7 | |
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8 | module radio_bridge |
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9 | ( |
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10 | converter_clock_in, |
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11 | converter_clock_out, |
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12 | |
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13 | user_RSSI_ADC_clk, |
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14 | radio_RSSI_ADC_clk, |
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15 | |
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16 | user_RSSI_ADC_D, |
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17 | |
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18 | user_EEPROM_IO_T, |
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19 | user_EEPROM_IO_O, |
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20 | user_EEPROM_IO_I, |
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21 | |
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22 | user_TxModelStart, |
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23 | |
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24 | radio_EEPROM_IO, |
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25 | |
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26 | radio_DAC_I, |
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27 | radio_DAC_Q, |
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28 | |
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29 | radio_ADC_I, |
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30 | radio_ADC_Q, |
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31 | |
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32 | user_DAC_I, |
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33 | user_DAC_Q, |
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34 | |
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35 | user_ADC_I, |
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36 | user_ADC_Q, |
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37 | |
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38 | radio_B, |
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39 | user_Tx_gain, |
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40 | user_RxBB_gain, |
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41 | user_RxRF_gain, |
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42 | |
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43 | user_SHDN_external, |
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44 | user_RxEn_external, |
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45 | user_TxEn_external, |
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46 | user_RxHP_external, |
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47 | |
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48 | controller_logic_clk, |
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49 | controller_spi_clk, |
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50 | controller_spi_data, |
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51 | controller_radio_cs, |
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52 | controller_dac_cs, |
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53 | controller_SHDN, |
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54 | controller_TxEn, |
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55 | controller_RxEn, |
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56 | controller_RxHP, |
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57 | controller_24PA, |
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58 | controller_5PA, |
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59 | controller_ANTSW, |
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60 | controller_LED, |
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61 | controller_RX_ADC_DCS, |
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62 | controller_RX_ADC_DFS, |
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63 | controller_RX_ADC_PWDNA, |
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64 | controller_RX_ADC_PWDNB, |
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65 | controller_DIPSW, |
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66 | controller_RSSI_ADC_CLAMP, |
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67 | controller_RSSI_ADC_HIZ, |
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68 | controller_RSSI_ADC_SLEEP, |
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69 | controller_RSSI_ADC_D, |
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70 | controller_TxStart, |
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71 | |
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72 | controller_LD, |
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73 | controller_RX_ADC_OTRA, |
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74 | controller_RX_ADC_OTRB, |
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75 | controller_RSSI_ADC_OTR, |
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76 | controller_DAC_PLL_LOCK, |
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77 | controller_DAC_RESET, |
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78 | |
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79 | controller_SHDN_external, |
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80 | controller_RxEn_external, |
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81 | controller_TxEn_external, |
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82 | controller_RxHP_external, |
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83 | |
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84 | dac_spi_data, |
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85 | dac_spi_cs, |
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86 | dac_spi_clk, |
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87 | |
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88 | radio_spi_clk, |
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89 | radio_spi_data, |
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90 | radio_spi_cs, |
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91 | |
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92 | radio_SHDN, |
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93 | radio_TxEn, |
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94 | radio_RxEn, |
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95 | radio_RxHP, |
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96 | radio_24PA, |
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97 | radio_5PA, |
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98 | radio_ANTSW, |
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99 | radio_LED, |
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100 | radio_RX_ADC_DCS, |
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101 | radio_RX_ADC_DFS, |
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102 | radio_RX_ADC_PWDNA, |
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103 | radio_RX_ADC_PWDNB, |
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104 | radio_DIPSW, |
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105 | radio_RSSI_ADC_CLAMP, |
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106 | radio_RSSI_ADC_HIZ, |
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107 | radio_RSSI_ADC_SLEEP, |
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108 | radio_RSSI_ADC_D, |
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109 | |
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110 | radio_LD, |
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111 | radio_RX_ADC_OTRA, |
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112 | radio_RX_ADC_OTRB, |
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113 | radio_RSSI_ADC_OTR, |
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114 | radio_DAC_PLL_LOCK, |
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115 | radio_DAC_RESET |
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116 | ); |
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117 | |
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118 | parameter C_FAMILY = "virtex2p"; |
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119 | |
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120 | /**********************/ |
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121 | /* Clock & Data Ports */ |
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122 | /**********************/ |
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123 | input converter_clock_in; |
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124 | output converter_clock_out; |
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125 | |
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126 | input user_RSSI_ADC_clk; |
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127 | output radio_RSSI_ADC_clk; |
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128 | output [0:9] user_RSSI_ADC_D; |
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129 | |
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130 | input user_EEPROM_IO_T; |
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131 | input user_EEPROM_IO_O; |
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132 | output user_EEPROM_IO_I; |
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133 | |
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134 | output user_TxModelStart; |
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135 | |
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136 | output [0:15] radio_DAC_I; |
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137 | output [0:15] radio_DAC_Q; |
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138 | |
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139 | input [0:13] radio_ADC_I; |
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140 | input [0:13] radio_ADC_Q; |
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141 | |
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142 | input [0:15] user_DAC_I; |
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143 | input [0:15] user_DAC_Q; |
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144 | |
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145 | output [0:13] user_ADC_I; |
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146 | output [0:13] user_ADC_Q; |
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147 | |
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148 | input [0:1] user_RxRF_gain; |
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149 | input [0:4] user_RxBB_gain; |
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150 | |
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151 | input [0:5] user_Tx_gain; |
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152 | |
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153 | /* radio_B is a 7-bit bus */ |
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154 | /* In Rx mode, radio_B[0:1] = RF gain, radio_B[2:6] = baseband gain */ |
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155 | /* In Tx mode, radio_B[1:6] = gain, radio_B[0] is unused */ |
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156 | output [0:6] radio_B; |
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157 | |
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158 | input user_SHDN_external; |
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159 | input user_RxEn_external; |
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160 | input user_TxEn_external; |
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161 | input user_RxHP_external; |
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162 | |
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163 | /*******************************************/ |
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164 | /* Radio Controller <-> Radio Bridge Ports */ |
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165 | /*******************************************/ |
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166 | input controller_logic_clk; |
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167 | input controller_spi_clk; |
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168 | input controller_spi_data; |
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169 | input controller_radio_cs; |
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170 | input controller_dac_cs; |
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171 | |
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172 | input controller_SHDN; |
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173 | input controller_TxEn; |
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174 | input controller_RxEn; |
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175 | input controller_RxHP; |
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176 | input controller_24PA; |
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177 | input controller_5PA; |
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178 | input [0:1] controller_ANTSW; |
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179 | input [0:2] controller_LED; |
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180 | input controller_RX_ADC_DCS; |
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181 | input controller_RX_ADC_DFS; |
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182 | input controller_RX_ADC_PWDNA; |
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183 | input controller_RX_ADC_PWDNB; |
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184 | input controller_RSSI_ADC_CLAMP; |
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185 | input controller_RSSI_ADC_HIZ; |
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186 | input controller_RSSI_ADC_SLEEP; |
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187 | input controller_DAC_RESET; |
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188 | input controller_TxStart; |
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189 | |
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190 | output [0:3] controller_DIPSW; |
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191 | output [0:9] controller_RSSI_ADC_D; |
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192 | output controller_LD; |
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193 | output controller_RX_ADC_OTRA; |
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194 | output controller_RX_ADC_OTRB; |
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195 | output controller_RSSI_ADC_OTR; |
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196 | output controller_DAC_PLL_LOCK; |
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197 | |
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198 | output controller_SHDN_external; |
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199 | output controller_RxEn_external; |
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200 | output controller_TxEn_external; |
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201 | output controller_RxHP_external; |
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202 | |
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203 | /**************************************/ |
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204 | /* Radio Bridge <-> Radio Board Ports */ |
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205 | /**************************************/ |
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206 | output dac_spi_data; |
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207 | output dac_spi_cs; |
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208 | output dac_spi_clk; |
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209 | |
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210 | output radio_spi_clk; |
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211 | output radio_spi_data; |
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212 | output radio_spi_cs; |
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213 | |
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214 | output radio_SHDN; |
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215 | output radio_TxEn; |
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216 | output radio_RxEn; |
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217 | output radio_RxHP; |
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218 | output radio_24PA; |
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219 | output radio_5PA; |
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220 | output [0:1] radio_ANTSW; |
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221 | output [0:2] radio_LED; |
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222 | output radio_RX_ADC_DCS; |
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223 | output radio_RX_ADC_DFS; |
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224 | output radio_RX_ADC_PWDNA; |
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225 | output radio_RX_ADC_PWDNB; |
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226 | output radio_RSSI_ADC_CLAMP; |
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227 | output radio_RSSI_ADC_HIZ; |
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228 | output radio_RSSI_ADC_SLEEP; |
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229 | output radio_DAC_RESET; |
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230 | |
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231 | input [0:9] radio_RSSI_ADC_D; |
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232 | input radio_LD; |
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233 | input radio_RX_ADC_OTRA; |
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234 | input radio_RX_ADC_OTRB; |
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235 | input radio_RSSI_ADC_OTR; |
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236 | input radio_DAC_PLL_LOCK; |
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237 | input [0:3] radio_DIPSW; |
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238 | |
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239 | inout radio_EEPROM_IO; |
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240 | |
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241 | //All the I/O will be registered using IOB registers |
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242 | reg radio_RSSI_ADC_clk; |
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243 | //reg [0:9] user_RSSI_ADC_D; |
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244 | reg [0:15] radio_DAC_I; |
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245 | reg [0:15] radio_DAC_Q; |
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246 | |
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247 | reg [0:13] user_ADC_I; |
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248 | reg [0:13] user_ADC_Q; |
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249 | |
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250 | reg [0:13] radio_ADC_I_nReg; |
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251 | reg [0:13] radio_ADC_Q_nReg; |
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252 | |
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253 | reg [0:6] radio_B; |
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254 | reg [0:3] controller_DIPSW; |
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255 | //reg [0:9] controller_RSSI_ADC_D; |
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256 | reg controller_LD; |
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257 | reg controller_RX_ADC_OTRA; |
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258 | reg controller_RX_ADC_OTRB; |
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259 | reg controller_RSSI_ADC_OTR; |
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260 | reg controller_DAC_PLL_LOCK; |
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261 | reg dac_spi_data; |
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262 | reg dac_spi_cs; |
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263 | reg dac_spi_clk; |
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264 | reg radio_spi_clk; |
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265 | reg radio_spi_data; |
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266 | reg radio_spi_cs; |
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267 | reg radio_SHDN; |
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268 | reg radio_TxEn; |
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269 | reg radio_RxEn; |
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270 | reg radio_RxHP; |
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271 | reg radio_24PA; |
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272 | reg radio_5PA; |
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273 | reg [0:1] radio_ANTSW; |
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274 | reg [0:2] radio_LED; |
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275 | reg radio_RX_ADC_DCS; |
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276 | reg radio_RX_ADC_DFS; |
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277 | reg radio_RX_ADC_PWDNA; |
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278 | reg radio_RX_ADC_PWDNB; |
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279 | reg radio_RSSI_ADC_CLAMP; |
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280 | reg radio_RSSI_ADC_HIZ; |
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281 | reg radio_RSSI_ADC_SLEEP; |
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282 | reg radio_DAC_RESET; |
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283 | |
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284 | //Drive the clock out to the ADC/DACs |
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285 | //synthesis attribute IOB of converter_clock_out IS true; |
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286 | OFDDRRSE OFDDRRSE_inst ( |
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287 | .Q(converter_clock_out), // Data output (connect directly to top-level port) |
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288 | .C0(converter_clock_in), // 0 degree clock input |
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289 | .C1(~converter_clock_in), // 180 degree clock input |
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290 | .CE(1'b1), // Clock enable input |
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291 | .D0(1'b1), // Posedge data input |
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292 | .D1(1'b0), // Negedge data input |
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293 | .R(1'b0), // Synchronous reset input |
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294 | .S(1'b0) // Synchronous preset input |
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295 | ); |
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296 | |
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297 | //Pass the Tx start signal through to the user port |
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298 | // This is an internal signal, so it won't be registered here |
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299 | assign user_TxModelStart = controller_TxStart; |
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300 | |
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301 | // Pass user_external signals to the controller |
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302 | assign controller_SHDN_external = user_SHDN_external; |
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303 | assign controller_RxEn_external = user_RxEn_external; |
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304 | assign controller_TxEn_external = user_TxEn_external; |
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305 | assign controller_RxHP_external = user_RxHP_external; |
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306 | |
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307 | |
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308 | //Make the gain mux default to the Tx settings, unless Rx is active |
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309 | //The Tx gain needs to be zero when TxEn is raised |
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310 | //The radio controller outputs zero for TxGain by default |
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311 | wire [0:6] radio_B_preReg; |
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312 | //assign radio_B_preReg = radio_RxEn ? {user_RxRF_gain, user_RxBB_gain} : {1'b0, user_Tx_gain}; |
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313 | assign radio_B_preReg = controller_RxEn ? {user_RxRF_gain, user_RxBB_gain} : {1'b0, user_Tx_gain}; |
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314 | |
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315 | |
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316 | /********************************************/ |
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317 | /* Instantiate the IOBUF for EEPROM Devices */ |
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318 | /********************************************/ |
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319 | IOBUF #( |
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320 | .DRIVE(8), |
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321 | .SLEW("SLOW") |
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322 | ) xIOBUF ( |
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323 | .T(user_EEPROM_IO_T), |
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324 | .I(user_EEPROM_IO_O), |
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325 | .O(user_EEPROM_IO_I), |
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326 | .IO(radio_EEPROM_IO) |
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327 | ); |
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328 | |
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329 | //Capture the incoming ADC signals on the negative |
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330 | // edge of the converter clock |
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331 | //synthesis attribute IOB of radio_ADC_I_nReg IS true; |
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332 | //synthesis attribute IOB of radio_ADC_Q_nReg IS true; |
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333 | always @( negedge converter_clock_in ) |
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334 | begin |
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335 | radio_ADC_I_nReg <= radio_ADC_I; |
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336 | radio_ADC_Q_nReg <= radio_ADC_Q; |
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337 | end |
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338 | |
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339 | |
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340 | always @( posedge converter_clock_in ) |
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341 | begin |
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342 | /*******************************************/ |
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343 | /* PHY Cores <-> Radio Board */ |
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344 | /*******************************************/ |
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345 | radio_B <= radio_B_preReg; |
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346 | |
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347 | radio_RSSI_ADC_clk <= user_RSSI_ADC_clk; |
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348 | |
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349 | user_ADC_I <= radio_ADC_I_nReg; |
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350 | user_ADC_Q <= radio_ADC_Q_nReg; |
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351 | |
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352 | radio_DAC_I <= user_DAC_I; |
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353 | radio_DAC_Q <= user_DAC_Q; |
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354 | end |
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355 | |
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356 | |
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357 | //Use the clock provied by the radio_controller to register its I/O |
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358 | // This will be a copy of the PLB clock for the controller's bus |
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359 | // It may be different than the converter clock (probably faster, but usually still synchronous) |
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360 | always @( posedge controller_logic_clk ) |
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361 | begin |
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362 | /*******************************************/ |
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363 | /* Radio Controller -> Radio Board Drivers */ |
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364 | /*******************************************/ |
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365 | dac_spi_clk <= controller_spi_clk; |
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366 | dac_spi_data <= controller_spi_data; |
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367 | dac_spi_cs <= controller_dac_cs; |
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368 | radio_spi_clk <= controller_spi_clk; |
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369 | radio_spi_data <= controller_spi_data; |
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370 | radio_spi_cs <= controller_radio_cs; |
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371 | radio_SHDN <= controller_SHDN; |
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372 | radio_TxEn <= controller_TxEn; |
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373 | radio_RxEn <= controller_RxEn; |
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374 | radio_RxHP <= controller_RxHP; |
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375 | radio_24PA <= controller_24PA; |
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376 | radio_5PA <= controller_5PA; |
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377 | radio_ANTSW <= controller_ANTSW; |
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378 | radio_LED <= controller_LED; |
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379 | radio_RX_ADC_DCS <= controller_RX_ADC_DCS; |
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380 | radio_RX_ADC_DFS <= controller_RX_ADC_DFS; |
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381 | radio_RX_ADC_PWDNA <= controller_RX_ADC_PWDNA; |
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382 | radio_RX_ADC_PWDNB <= controller_RX_ADC_PWDNB; |
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383 | radio_RSSI_ADC_CLAMP <= controller_RSSI_ADC_CLAMP; |
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384 | radio_RSSI_ADC_HIZ <= controller_RSSI_ADC_HIZ; |
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385 | radio_RSSI_ADC_SLEEP <= controller_RSSI_ADC_SLEEP; |
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386 | |
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387 | /*******************************************/ |
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388 | /* Radio Board -> Radio Controller Drivers */ |
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389 | /*******************************************/ |
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390 | controller_DIPSW <= radio_DIPSW; |
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391 | controller_LD <= radio_LD; |
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392 | controller_RX_ADC_OTRA <= radio_RX_ADC_OTRA; |
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393 | controller_RX_ADC_OTRB <= radio_RX_ADC_OTRB; |
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394 | controller_RSSI_ADC_OTR <= radio_RSSI_ADC_OTR; |
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395 | controller_DAC_PLL_LOCK <= radio_DAC_PLL_LOCK; |
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396 | radio_DAC_RESET <= controller_DAC_RESET; |
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397 | end |
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398 | |
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399 | //Delay the user's RSSI clk input by 1 cycle |
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400 | reg user_RSSI_ADC_clk_d1; |
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401 | always @( posedge controller_logic_clk ) |
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402 | begin |
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403 | user_RSSI_ADC_clk_d1 <= user_RSSI_ADC_clk; |
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404 | end |
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405 | |
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406 | //Capture the RSSI ADC data in the IOB input registers |
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407 | //synthesis attribute IOB of radio_RSSI_ADC_D_d1 IS true; |
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408 | //synthesis attribute KEEP of radio_RSSI_ADC_D_d1 IS true; |
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409 | reg [9:0] radio_RSSI_ADC_D_d1; |
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410 | always @( posedge controller_logic_clk ) |
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411 | begin |
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412 | //Use rising edge of user-supplied RSSI ADC clock as CE for the RSS ADC data register |
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413 | if(user_RSSI_ADC_clk_d1 & ~user_RSSI_ADC_clk) |
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414 | begin |
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415 | radio_RSSI_ADC_D_d1 <= radio_RSSI_ADC_D; |
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416 | end |
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417 | end |
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418 | |
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419 | |
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420 | assign controller_RSSI_ADC_D = radio_RSSI_ADC_D_d1; |
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421 | assign user_RSSI_ADC_D = radio_RSSI_ADC_D_d1; |
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422 | |
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423 | //Use XST attributes to force the registers for these signals into the IOBs |
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424 | //synthesis attribute IOB of radio_RSSI_ADC_clk IS true; |
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425 | //synthesis attribute IOB of radio_DAC_I IS true; |
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426 | //synthesis attribute IOB of radio_DAC_Q IS true; |
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427 | //synthesis attribute IOB of radio_B IS true; |
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428 | //synthesis attribute IOB of controller_DIPSW IS true; |
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429 | //synthesis attribute IOB of controller_LD IS true; |
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430 | //synthesis attribute IOB of controller_RX_ADC_OTRA IS true; |
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431 | //synthesis attribute IOB of controller_RX_ADC_OTRB IS true; |
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432 | //synthesis attribute IOB of controller_RSSI_ADC_OTR IS true; |
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433 | //synthesis attribute IOB of controller_DAC_PLL_LOCK IS true; |
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434 | //synthesis attribute IOB of dac_spi_cs IS true; |
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435 | |
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436 | //synthesis attribute IOB of dac_spi_data IS true; |
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437 | //synthesis attribute IOB of dac_spi_clk IS true; |
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438 | //synthesis attribute IOB of radio_spi_clk IS true; |
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439 | //synthesis attribute IOB of radio_spi_data IS true; |
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440 | |
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441 | //synthesis attribute KEEP of dac_spi_data IS true; |
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442 | //synthesis attribute KEEP of dac_spi_clk IS true; |
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443 | //synthesis attribute KEEP of radio_spi_clk IS true; |
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444 | //synthesis attribute KEEP of radio_spi_data IS true; |
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445 | |
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446 | //synthesis attribute IOB of radio_spi_cs IS true; |
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447 | //synthesis attribute IOB of radio_SHDN IS true; |
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448 | //synthesis attribute IOB of radio_TxEn IS true; |
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449 | //synthesis attribute IOB of radio_RxEn IS true; |
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450 | //synthesis attribute IOB of radio_RxHP IS true; |
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451 | //synthesis attribute IOB of radio_24PA IS true; |
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452 | //synthesis attribute IOB of radio_5PA IS true; |
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453 | //synthesis attribute IOB of radio_ANTSW IS true; |
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454 | //synthesis attribute IOB of radio_LED IS true; |
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455 | //synthesis attribute IOB of radio_RX_ADC_DCS IS true; |
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456 | //synthesis attribute IOB of radio_RX_ADC_DFS IS true; |
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457 | //synthesis attribute IOB of radio_RX_ADC_PWDNA IS true; |
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458 | //synthesis attribute IOB of radio_RX_ADC_PWDNB IS true; |
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459 | //synthesis attribute IOB of radio_RSSI_ADC_CLAMP IS true; |
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460 | //synthesis attribute IOB of radio_RSSI_ADC_HIZ IS true; |
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461 | //synthesis attribute IOB of radio_RSSI_ADC_SLEEP IS true; |
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462 | //synthesis attribute IOB of radio_DAC_RESET IS true; |
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463 | |
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464 | endmodule |
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