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# Copyright (c) 2013 Mango Communications
# All Rights Reserved
# This code is covered by the WARP open-source license
# See http://warpproject.org/license/ for details
###################################################################

BEGIN radio_bridge

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION ARCH_SUPPORT_MAP = (virtex4=DEVELOPMENT)
OPTION USAGE_LEVEL = BASE_USER
OPTION DESC = WARP Radio Board Bridge Core
OPTION LONG_DESC = "Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards."
OPTION IP_GROUP = USER
OPTION RUN_NGCBUILD = FALSE
OPTION STYLE = HDL

IO_INTERFACE IO_IF = HW_Ports, IO_TYPE = W2_RADIOBRIDGE_V0
IO_INTERFACE IO_IF = USER_Ports, IO_TYPE = W2_RADIOBRIDGE_V0

PARAMETER C_FAMILY = virtex4, DT = STRING

#This clock must match the sampling clock at the Radio Board (the one driven by the Clock Board via the twisted pair cable)
PORT samp_clock = "", DIR = I, SIGIS = CLK, CLK_FREQ = 40000000, IO_IF = USER_Ports, ASSIGNMENT = REQUIRE, IO_IS = user_sampClock

## User Ports
PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IF = USER_Ports, IO_IS = userADCI
PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IF = USER_Ports, IO_IS = userADCQ

PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IF = USER_Ports, IO_IS = userDACI
PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IF = USER_Ports, IO_IS = userDACQ

PORT user_ADC_I_OTR = "", DIR = O, IO_IF = USER_Ports, IO_IS = ADC_I_OTR
PORT user_ADC_Q_OTR = "", DIR = O, IO_IF = USER_Ports, IO_IS = ADC_Q_OTR
	
PORT user_RSSI_ADC_D = "", DIR = O, VEC = [9:0], IO_IF = USER_Ports, IO_IS = user_RSSI_ADC_D
PORT user_RSSI_ADC_CLK = "", DIR = I, IO_IF = USER_Ports, IO_IS = user_RSSI_ADC_CLK

## Radio Bridge <-> Radio Board ports
PORT radio_DAC_I = "", DIR = O, VEC = [15:0], IO_IS = radioDACI, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioDACI
PORT radio_DAC_Q = "", DIR = O, VEC = [15:0], IO_IS = radioDACQ, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioDACQ

PORT radio_ADC_I = "", DIR = I, VEC = [13:0], IO_IS = radioADCI, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioADCI
PORT radio_ADC_Q = "", DIR = I, VEC = [13:0], IO_IS = radioADCQ, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioADCQ

PORT radio_ADC_I_OTR = "", DIR = I, IO_IF = HW_Ports, IO_IS = radio_ADC_I_OTR
PORT radio_ADC_Q_OTR = "", DIR = I, IO_IF = HW_Ports, IO_IS = radio_ADC_Q_OTR

PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [9:0], IO_IF = HW_Ports, IO_IS = radio_RSSI_ADC_D
PORT radio_RSSI_ADC_CLK = "", DIR = O, IO_IF = HW_Ports, IO_IS = radio_RSSI_ADC_CLK
END