source: PlatformSupport/CustomPeripherals/pcores/radio_bridge_v2_00_a/hdl/verilog/radio_bridge.v

//////////////////////////////////////////////////////////
// Copyright (c) 2013 Mango Communications, Inc.
// All Rights Reserved                  
// This code is covered by the WARP license
// See http://warpproject.org/license/ for details
//////////////////////////////////////////////////////////

module radio_bridge
(
    input samp_clock,
    
    output reg [0:13] user_ADC_I,
    output reg [0:13] user_ADC_Q,

    input [0:15] user_DAC_I,
    input [0:15] user_DAC_Q,

    output reg user_ADC_I_OTR,
    output reg user_ADC_Q_OTR,
    
    output reg [0:9] user_RSSI_ADC_D,
    input user_RSSI_ADC_CLK,

    output reg [0:15] radio_DAC_I,
    output reg [0:15] radio_DAC_Q,
    
    input [0:13] radio_ADC_I,
    input [0:13] radio_ADC_Q,

    input radio_ADC_I_OTR,
    input radio_ADC_Q_OTR,
    
    input [0:9] radio_RSSI_ADC_D,
    output reg radio_RSSI_ADC_CLK
);

parameter C_FAMILY = "virtex4";

reg [0:13] radio_ADC_I_nReg;
reg [0:13] radio_ADC_Q_nReg;
reg radio_ADC_I_OTR_nReg;
reg radio_ADC_Q_OTR_nReg;

//Capture the incoming ADC signals on the negative
// edge of the converter clock
//synthesis attribute IOB of radio_ADC_I_nReg IS true;
//synthesis attribute IOB of radio_ADC_Q_nReg IS true;
always @( negedge samp_clock )
begin
    radio_ADC_I_nReg <= radio_ADC_I;
    radio_ADC_Q_nReg <= radio_ADC_Q;

    radio_ADC_I_OTR_nReg <= radio_ADC_I_OTR;
    radio_ADC_Q_OTR_nReg <= radio_ADC_Q_OTR;
end

always @( posedge samp_clock )
begin
    user_ADC_I <= radio_ADC_I_nReg;
    user_ADC_Q <= radio_ADC_Q_nReg;

    radio_DAC_I <= user_DAC_I;
    radio_DAC_Q <= user_DAC_Q;
    
    user_ADC_I_OTR <= radio_ADC_I_OTR_nReg;
    user_ADC_Q_OTR <= radio_ADC_Q_OTR_nReg;
end

always @( posedge samp_clock )
begin
    radio_RSSI_ADC_CLK <= user_RSSI_ADC_CLK;
    user_RSSI_ADC_D <= radio_RSSI_ADC_D;
end

//Use XST attributes to force the registers for these signals into the IOBs
//synthesis attribute IOB of radio_DAC_I IS true;
//synthesis attribute IOB of radio_DAC_Q IS true;
//synthesis attribute IOB of radio_ADC_I_nReg IS true;
//synthesis attribute IOB of radio_ADC_I_nReg IS true;
//synthesis attribute IOB of radio_ADC_I_OTR_nReg IS true;
//synthesis attribute IOB of radio_ADC_Q_OTR_nReg IS true;
//synthesis attribute IOB of radio_RSSI_ADC_CLK IS true;
//synthesis attribute IOB of radio_RSSI_ADC_D IS true;


endmodule