1 | //---------------------------------------------------------------------------- |
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2 | // user_logic.v - module |
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3 | //---------------------------------------------------------------------------- |
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4 | // |
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5 | // *************************************************************************** |
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6 | // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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7 | // ** ** |
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8 | // ** Xilinx, Inc. ** |
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9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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21 | // ** FOR A PARTICULAR PURPOSE. ** |
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22 | // ** ** |
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23 | // *************************************************************************** |
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24 | // |
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25 | //---------------------------------------------------------------------------- |
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26 | // Filename: user_logic.v |
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27 | // Version: 3.00.c |
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28 | // Description: User logic module. |
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29 | // Date: Tue Feb 26 20:52:28 2013 (by Create and Import Peripheral Wizard) |
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30 | // Verilog Standard: Verilog-2001 |
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31 | //---------------------------------------------------------------------------- |
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32 | // Naming Conventions: |
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33 | // active low signals: "*_n" |
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34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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35 | // reset signals: "rst", "rst_n" |
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36 | // generics: "C_*" |
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37 | // user defined types: "*_TYPE" |
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38 | // state machine next state: "*_ns" |
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39 | // state machine current state: "*_cs" |
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40 | // combinatorial signals: "*_com" |
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41 | // pipelined or register delay signals: "*_d#" |
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42 | // counter signals: "*cnt*" |
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43 | // clock enable signals: "*_ce" |
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44 | // internal version of output port: "*_i" |
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45 | // device pins: "*_pin" |
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46 | // ports: "- Names begin with Uppercase" |
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47 | // processes: "*_PROCESS" |
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48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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49 | //---------------------------------------------------------------------------- |
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50 | |
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51 | `uselib lib=unisims_ver |
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52 | `uselib lib=proc_common_v3_00_a |
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53 | |
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54 | module user_logic |
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55 | ( |
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56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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57 | //I/O for MAX2829 pins |
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58 | output RFA_TxEn, |
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59 | output RFB_TxEn, |
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60 | output RFC_TxEn, |
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61 | output RFD_TxEn, |
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62 | |
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63 | output RFA_RxEn, |
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64 | output RFB_RxEn, |
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65 | output RFC_RxEn, |
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66 | output RFD_RxEn, |
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67 | |
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68 | output RFA_RxHP, |
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69 | output RFB_RxHP, |
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70 | output RFC_RxHP, |
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71 | output RFD_RxHP, |
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72 | |
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73 | output RFA_SHDN, |
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74 | output RFB_SHDN, |
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75 | output RFC_SHDN, |
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76 | output RFD_SHDN, |
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77 | |
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78 | output RFA_SPI_SCLK, |
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79 | output RFB_SPI_SCLK, |
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80 | output RFC_SPI_SCLK, |
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81 | output RFD_SPI_SCLK, |
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82 | |
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83 | output RFA_SPI_MOSI, |
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84 | output RFB_SPI_MOSI, |
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85 | output RFC_SPI_MOSI, |
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86 | output RFD_SPI_MOSI, |
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87 | |
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88 | output RFA_SPI_CSn, |
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89 | output RFB_SPI_CSn, |
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90 | output RFC_SPI_CSn, |
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91 | output RFD_SPI_CSn, |
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92 | |
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93 | output [6:0] RFA_B, |
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94 | output [6:0] RFB_B, |
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95 | output [6:0] RFC_B, |
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96 | output [6:0] RFD_B, |
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97 | |
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98 | input RFA_LD, |
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99 | input RFB_LD, |
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100 | input RFC_LD, |
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101 | input RFD_LD, |
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102 | |
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103 | //Outputs to PA and ant switch pins |
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104 | output RFA_PAEn_24, |
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105 | output RFB_PAEn_24, |
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106 | output RFC_PAEn_24, |
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107 | output RFD_PAEn_24, |
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108 | |
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109 | output RFA_PAEn_5, |
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110 | output RFB_PAEn_5, |
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111 | output RFC_PAEn_5, |
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112 | output RFD_PAEn_5, |
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113 | |
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114 | output [1:0] RFA_AntSw, |
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115 | output [1:0] RFB_AntSw, |
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116 | output [1:0] RFC_AntSw, |
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117 | output [1:0] RFD_AntSw, |
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118 | |
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119 | //I/O for user logic to control state from hardware |
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120 | input usr_RFA_TxEn, |
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121 | input usr_RFB_TxEn, |
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122 | input usr_RFC_TxEn, |
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123 | input usr_RFD_TxEn, |
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124 | |
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125 | input usr_RFA_RxEn, |
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126 | input usr_RFB_RxEn, |
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127 | input usr_RFC_RxEn, |
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128 | input usr_RFD_RxEn, |
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129 | |
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130 | input usr_RFA_RxHP, |
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131 | input usr_RFB_RxHP, |
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132 | input usr_RFC_RxHP, |
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133 | input usr_RFD_RxHP, |
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134 | |
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135 | input usr_RFA_SHDN, |
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136 | input usr_RFB_SHDN, |
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137 | input usr_RFC_SHDN, |
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138 | input usr_RFD_SHDN, |
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139 | |
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140 | input [1:0] usr_RFA_RxGainRF, |
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141 | input [1:0] usr_RFB_RxGainRF, |
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142 | input [1:0] usr_RFC_RxGainRF, |
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143 | input [1:0] usr_RFD_RxGainRF, |
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144 | |
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145 | input [4:0] usr_RFA_RxGainBB, |
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146 | input [4:0] usr_RFB_RxGainBB, |
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147 | input [4:0] usr_RFC_RxGainBB, |
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148 | input [4:0] usr_RFD_RxGainBB, |
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149 | |
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150 | input [5:0] usr_RFA_TxGain, |
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151 | input [5:0] usr_RFB_TxGain, |
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152 | input [5:0] usr_RFC_TxGain, |
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153 | input [5:0] usr_RFD_TxGain, |
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154 | |
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155 | input usr_SPI_ctrlSrc, |
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156 | input usr_SPI_go, |
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157 | output usr_SPI_active, |
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158 | input [3:0] usr_SPI_rfsel, |
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159 | input [3:0] usr_SPI_regaddr, |
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160 | input [13:0] usr_SPI_regdata, |
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161 | |
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162 | output usr_RFA_PHYStart, |
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163 | output usr_RFB_PHYStart, |
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164 | output usr_RFC_PHYStart, |
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165 | output usr_RFD_PHYStart, |
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166 | |
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167 | output usr_any_PHYStart, |
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168 | |
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169 | output usr_RFA_statLED_Tx, |
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170 | output usr_RFA_statLED_Rx, |
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171 | output usr_RFB_statLED_Tx, |
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172 | output usr_RFB_statLED_Rx, |
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173 | output usr_RFC_statLED_Tx, |
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174 | output usr_RFC_statLED_Rx, |
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175 | output usr_RFD_statLED_Tx, |
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176 | output usr_RFD_statLED_Rx, |
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177 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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178 | |
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179 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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180 | // -- Bus protocol ports, do not add to or delete |
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181 | input Bus2IP_Clk, |
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182 | input Bus2IP_Resetn, |
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183 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data, |
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184 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE, |
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185 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE, |
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186 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE, |
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187 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data, |
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188 | output IP2Bus_RdAck, |
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189 | output IP2Bus_WrAck, |
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190 | output IP2Bus_Error |
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191 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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192 | ); // user_logic |
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193 | |
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194 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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195 | // --USER parameters added here |
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196 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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197 | |
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198 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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199 | // -- Bus protocol parameters, do not add to or delete |
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200 | //parameter C_NUM_REG = 30; |
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201 | parameter C_NUM_REG = 64; |
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202 | parameter C_SLV_DWIDTH = 32; |
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203 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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204 | |
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205 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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206 | // --USER ports added here |
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207 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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208 | |
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209 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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210 | // -- Bus protocol ports, do not add to or delete |
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211 | /* Moved to module declaration above |
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212 | input Bus2IP_Clk; |
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213 | input Bus2IP_Resetn; |
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214 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; |
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215 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; |
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216 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE; |
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217 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE; |
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218 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; |
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219 | output IP2Bus_RdAck; |
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220 | output IP2Bus_WrAck; |
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221 | output IP2Bus_Error; |
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222 | */ |
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223 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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224 | |
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225 | //---------------------------------------------------------------------------- |
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226 | // Implementation |
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227 | //---------------------------------------------------------------------------- |
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228 | |
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229 | // --USER nets declarations added here, as needed for user logic |
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230 | `define MAX2829_REG0_ON_RESET 14'b01000101000000 |
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231 | `define MAX2829_REG1_ON_RESET 14'b00000011001010 |
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232 | `define MAX2829_REG2_ON_RESET 14'b01000000000111 |
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233 | `define MAX2829_REG3_ON_RESET 14'b11000010100010 |
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234 | `define MAX2829_REG4_ON_RESET 14'b01110111011101 |
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235 | `define MAX2829_REG5_ON_RESET 14'b01100000100100 |
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236 | `define MAX2829_REG6_ON_RESET 14'b01110000000000 |
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237 | `define MAX2829_REG7_ON_RESET 14'b00000000101010 |
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238 | `define MAX2829_REG8_ON_RESET 14'b00000000100101 |
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239 | `define MAX2829_REG9_ON_RESET 14'b00001000000000 |
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240 | `define MAX2829_REGA_ON_RESET 14'b00001111000000 |
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241 | `define MAX2829_REGB_ON_RESET 14'b00000001111111 |
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242 | `define MAX2829_REGC_ON_RESET 14'b00000000000000 |
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243 | |
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244 | `define TXTIMING_REG_ON_RESET 32'h10305020 //Sane default Tx Timing values |
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245 | `define TXGAINS_REG_ON_RESET 32'h32323232 //Tx Gain targets = 50 |
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246 | `define CLKDIV_GAINTIMING_REG_ON_RESET 32'h00004F22 //Gain step=0xF, time step=4, clk divs = 2 |
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247 | |
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248 | // Nets for user logic slave model s/w accessible register example |
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249 | reg [C_SLV_DWIDTH-1 : 0] slv_reg0; |
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250 | reg [C_SLV_DWIDTH-1 : 0] slv_reg1; |
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251 | reg [C_SLV_DWIDTH-1 : 0] slv_reg2; |
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252 | reg [C_SLV_DWIDTH-1 : 0] slv_reg3; |
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253 | reg [C_SLV_DWIDTH-1 : 0] slv_reg4; |
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254 | reg [C_SLV_DWIDTH-1 : 0] slv_reg5; |
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255 | reg [C_SLV_DWIDTH-1 : 0] slv_reg6; |
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256 | reg [C_SLV_DWIDTH-1 : 0] slv_reg7; |
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257 | reg [C_SLV_DWIDTH-1 : 0] slv_reg8; |
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258 | reg [C_SLV_DWIDTH-1 : 0] slv_reg9; |
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259 | reg [C_SLV_DWIDTH-1 : 0] slv_reg10; |
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260 | |
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261 | wire [10 : 0] slv_reg_write_sel; |
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262 | wire [63 : 0] slv_reg_read_sel; |
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263 | reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; |
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264 | wire slv_read_ack; |
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265 | wire slv_write_ack; |
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266 | integer byte_index, bit_index; |
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267 | |
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268 | wire slv_write_ack_normalRegisters; |
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269 | |
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270 | wire [31:0] status_reg; |
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271 | |
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272 | //Use Verilog array-of-arrays syntax for the register banks to mirror MAX2829 internal registers |
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273 | // RFx_MAX2829_mirrorRegs[N] maps to MAX2829 reg N, for N=[0x0, 0xC] |
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274 | // All registers are 14 bits in the MAX2829 |
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275 | reg [13:0] RFA_MAX2829_mirrorRegs [12:0]; |
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276 | reg [13:0] RFB_MAX2829_mirrorRegs [12:0]; |
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277 | reg [13:0] RFC_MAX2829_mirrorRegs [12:0]; |
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278 | reg [13:0] RFD_MAX2829_mirrorRegs [12:0]; |
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279 | |
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280 | wire RFA_TxEn_ctrlSrc, RFB_TxEn_ctrlSrc, RFC_TxEn_ctrlSrc, RFD_TxEn_ctrlSrc; |
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281 | wire RFA_RxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFD_RxEn_ctrlSrc; |
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282 | wire RFA_RxHP_ctrlSrc, RFB_RxHP_ctrlSrc, RFC_RxHP_ctrlSrc, RFD_RxHP_ctrlSrc; |
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283 | wire RFA_SHDN_ctrlSrc, RFB_SHDN_ctrlSrc, RFC_SHDN_ctrlSrc, RFD_SHDN_ctrlSrc; |
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284 | wire RFA_TxGain_ctrlSrc, RFB_TxGain_ctrlSrc, RFC_TxGain_ctrlSrc, RFD_TxGain_ctrlSrc; |
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285 | wire RFA_RxGain_ctrlSrc, RFB_RxGain_ctrlSrc, RFC_RxGain_ctrlSrc, RFD_RxGain_ctrlSrc; |
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286 | |
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287 | wire RFA_TxEn_sw, RFB_TxEn_sw, RFC_TxEn_sw, RFD_TxEn_sw; |
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288 | wire RFA_RxEn_sw, RFB_RxEn_sw, RFC_RxEn_sw, RFD_RxEn_sw; |
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289 | wire RFA_RxHP_sw, RFB_RxHP_sw, RFC_RxHP_sw, RFD_RxHP_sw; |
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290 | wire RFA_SHDN_sw, RFB_SHDN_sw, RFC_SHDN_sw, RFD_SHDN_sw; |
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291 | |
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292 | wire RFA_PAEn, RFB_PAEn, RFC_PAEn, RFD_PAEn; |
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293 | |
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294 | wire [7:0] TxTiming_dly_TxGainRamp, TxTiming_dly_PowerAmpEn, TxTiming_dly_TxEn, TxTiming_dly_startPHY; |
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295 | |
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296 | wire [3:0] TxGainRamp_gainStep, TxGainRamp_timeStep; |
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297 | |
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298 | wire [5:0] RFA_TxGain_sw, RFB_TxGain_sw, RFC_TxGain_sw, RFD_TxGain_sw; |
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299 | wire [4:0] RFA_RxGainBB_sw, RFB_RxGainBB_sw, RFC_RxGainBB_sw, RFD_RxGainBB_sw; |
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300 | wire [1:0] RFA_RxGainRF_sw, RFB_RxGainRF_sw, RFC_RxGainRF_sw, RFD_RxGainRF_sw; |
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301 | |
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302 | wire [5:0] RFA_TxGain_target, RFB_TxGain_target, RFC_TxGain_target, RFD_TxGain_target; |
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303 | wire [5:0] RFA_TxGain_ramped, RFB_TxGain_ramped, RFC_TxGain_ramped, RFD_TxGain_ramped; |
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304 | |
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305 | wire [4:0] RFA_RxGainBB, RFB_RxGainBB, RFC_RxGainBB, RFD_RxGainBB; |
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306 | wire [1:0] RFA_RxGainRF, RFB_RxGainRF, RFC_RxGainRF, RFD_RxGainRF; |
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307 | |
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308 | wire [2:0] spi_clk_div_sel; |
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309 | wire [1:0] txTiming_clk_div_sel; |
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310 | |
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311 | wire [3:0] spi_rfsel_mask_sw; |
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312 | wire [3:0] spi_rfsel_mask; |
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313 | wire [13:0] spi_tx_regdata; |
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314 | wire [3:0] spi_tx_regaddr; |
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315 | wire spi_go; |
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316 | |
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317 | wire spi_tx_reg_write; |
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318 | wire spi_xfer_done; |
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319 | |
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320 | wire RFA_txStart, RFB_txStart, RFC_txStart, RFD_txStart; |
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321 | |
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322 | wire RFA_MAX2829_Reset, RFB_MAX2829_Reset, RFC_MAX2829_Reset, RFD_MAX2829_Reset; |
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323 | |
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324 | |
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325 | // Slave register write process; only implemented for RW and WO registers |
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326 | always @( posedge Bus2IP_Clk ) |
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327 | begin |
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328 | if ( Bus2IP_Resetn == 1'b0 ) |
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329 | begin |
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330 | slv_reg0 <= 0; //All zeros on reset- Tx/Rx disabled, SHDN (active low) enabled |
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331 | slv_reg1 <= `TXTIMING_REG_ON_RESET; |
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332 | slv_reg2 <= `TXGAINS_REG_ON_RESET; |
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333 | slv_reg3 <= 0; |
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334 | slv_reg4 <= `CLKDIV_GAINTIMING_REG_ON_RESET; |
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335 | slv_reg5 <= 0; |
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336 | slv_reg6 <= 0; |
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337 | slv_reg7 <= 0; |
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338 | slv_reg8 <= 0; |
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339 | slv_reg9 <= 0; |
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340 | slv_reg10 <= 0; |
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341 | end |
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342 | else |
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343 | case ( slv_reg_write_sel ) |
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344 | 11'b10000000000 : |
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345 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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346 | if ( Bus2IP_BE[byte_index] == 1 ) |
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347 | slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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348 | 11'b01000000000 : |
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349 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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350 | if ( Bus2IP_BE[byte_index] == 1 ) |
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351 | slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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352 | 11'b00100000000 : |
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353 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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354 | if ( Bus2IP_BE[byte_index] == 1 ) |
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355 | slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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356 | 11'b00010000000 : |
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357 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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358 | if ( Bus2IP_BE[byte_index] == 1 ) |
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359 | slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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360 | 11'b00001000000 : |
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361 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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362 | if ( Bus2IP_BE[byte_index] == 1 ) |
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363 | slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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364 | 11'b00000100000 : |
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365 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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366 | if ( Bus2IP_BE[byte_index] == 1 ) |
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367 | slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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368 | 11'b00000010000 : |
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369 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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370 | if ( Bus2IP_BE[byte_index] == 1 ) |
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371 | slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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372 | 11'b00000001000 : |
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373 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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374 | if ( Bus2IP_BE[byte_index] == 1 ) |
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375 | slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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376 | 11'b00000000100 : |
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377 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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378 | if ( Bus2IP_BE[byte_index] == 1 ) |
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379 | slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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380 | 11'b00000000010 : |
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381 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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382 | if ( Bus2IP_BE[byte_index] == 1 ) |
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383 | slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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384 | 11'b00000000001 : |
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385 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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386 | if ( Bus2IP_BE[byte_index] == 1 ) |
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387 | slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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388 | |
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389 | default : begin |
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390 | slv_reg0 <= slv_reg0; |
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391 | slv_reg1 <= slv_reg1; |
---|
392 | slv_reg2 <= slv_reg2; |
---|
393 | slv_reg3 <= slv_reg3; |
---|
394 | slv_reg4 <= slv_reg4; |
---|
395 | slv_reg5 <= slv_reg5; |
---|
396 | slv_reg6 <= slv_reg6; |
---|
397 | slv_reg7 <= slv_reg7; |
---|
398 | slv_reg8 <= slv_reg8; |
---|
399 | slv_reg9 <= slv_reg9; |
---|
400 | slv_reg10 <= slv_reg10; |
---|
401 | end |
---|
402 | endcase |
---|
403 | |
---|
404 | end // SLAVE_REG_WRITE_PROC |
---|
405 | |
---|
406 | // Slave model register read mux |
---|
407 | // All registers can be read |
---|
408 | always @* |
---|
409 | begin |
---|
410 | case ( slv_reg_read_sel ) |
---|
411 | 64'b1000000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg0; |
---|
412 | 64'b0100000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg1; |
---|
413 | 64'b0010000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg2; |
---|
414 | 64'b0001000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg3; |
---|
415 | 64'b0000100000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg4; |
---|
416 | 64'b0000010000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg5; |
---|
417 | 64'b0000001000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg6; |
---|
418 | 64'b0000000100000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg7; |
---|
419 | 64'b0000000010000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg8; |
---|
420 | 64'b0000000001000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg9; |
---|
421 | 64'b0000000000100000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg10; |
---|
422 | 64'b0000000000010000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= status_reg; |
---|
423 | 64'b0000000000001000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[0]}; |
---|
424 | 64'b0000000000000100000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[1]}; |
---|
425 | 64'b0000000000000010000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[2]}; |
---|
426 | 64'b0000000000000001000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[3]}; |
---|
427 | 64'b0000000000000000100000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[4]}; |
---|
428 | 64'b0000000000000000010000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[5]}; |
---|
429 | 64'b0000000000000000001000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[6]}; |
---|
430 | 64'b0000000000000000000100000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[7]}; |
---|
431 | 64'b0000000000000000000010000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[8]}; |
---|
432 | 64'b0000000000000000000001000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[9]}; |
---|
433 | 64'b0000000000000000000000100000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[10]}; |
---|
434 | 64'b0000000000000000000000010000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[11]}; |
---|
435 | 64'b0000000000000000000000001000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[12]}; |
---|
436 | 64'b0000000000000000000000000100000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[0]}; |
---|
437 | 64'b0000000000000000000000000010000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[1]}; |
---|
438 | 64'b0000000000000000000000000001000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[2]}; |
---|
439 | 64'b0000000000000000000000000000100000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[3]}; |
---|
440 | 64'b0000000000000000000000000000010000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[4]}; |
---|
441 | 64'b0000000000000000000000000000001000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[5]}; |
---|
442 | 64'b0000000000000000000000000000000100000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[6]}; |
---|
443 | 64'b0000000000000000000000000000000010000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[7]}; |
---|
444 | 64'b0000000000000000000000000000000001000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[8]}; |
---|
445 | 64'b0000000000000000000000000000000000100000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[9]}; |
---|
446 | 64'b0000000000000000000000000000000000010000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[10]}; |
---|
447 | 64'b0000000000000000000000000000000000001000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[11]}; |
---|
448 | 64'b0000000000000000000000000000000000000100000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[12]}; |
---|
449 | 64'b0000000000000000000000000000000000000010000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[0]}; |
---|
450 | 64'b0000000000000000000000000000000000000001000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[1]}; |
---|
451 | 64'b0000000000000000000000000000000000000000100000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[2]}; |
---|
452 | 64'b0000000000000000000000000000000000000000010000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[3]}; |
---|
453 | 64'b0000000000000000000000000000000000000000001000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[4]}; |
---|
454 | 64'b0000000000000000000000000000000000000000000100000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[5]}; |
---|
455 | 64'b0000000000000000000000000000000000000000000010000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[6]}; |
---|
456 | 64'b0000000000000000000000000000000000000000000001000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[7]}; |
---|
457 | 64'b0000000000000000000000000000000000000000000000100000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[8]}; |
---|
458 | 64'b0000000000000000000000000000000000000000000000010000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[9]}; |
---|
459 | 64'b0000000000000000000000000000000000000000000000001000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[10]}; |
---|
460 | 64'b0000000000000000000000000000000000000000000000000100000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[11]}; |
---|
461 | 64'b0000000000000000000000000000000000000000000000000010000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[12]}; |
---|
462 | 64'b0000000000000000000000000000000000000000000000000001000000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[0]}; |
---|
463 | 64'b0000000000000000000000000000000000000000000000000000100000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[1]}; |
---|
464 | 64'b0000000000000000000000000000000000000000000000000000010000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[2]}; |
---|
465 | 64'b0000000000000000000000000000000000000000000000000000001000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[3]}; |
---|
466 | 64'b0000000000000000000000000000000000000000000000000000000100000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[4]}; |
---|
467 | 64'b0000000000000000000000000000000000000000000000000000000010000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[5]}; |
---|
468 | 64'b0000000000000000000000000000000000000000000000000000000001000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[6]}; |
---|
469 | 64'b0000000000000000000000000000000000000000000000000000000000100000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[7]}; |
---|
470 | 64'b0000000000000000000000000000000000000000000000000000000000010000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[8]}; |
---|
471 | 64'b0000000000000000000000000000000000000000000000000000000000001000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[9]}; |
---|
472 | 64'b0000000000000000000000000000000000000000000000000000000000000100 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[10]}; |
---|
473 | 64'b0000000000000000000000000000000000000000000000000000000000000010 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[11]}; |
---|
474 | 64'b0000000000000000000000000000000000000000000000000000000000000001 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[12]}; default : slv_ip2bus_data <= 0; |
---|
475 | endcase |
---|
476 | end // SLAVE_REG_READ_PROC |
---|
477 | |
---|
478 | /* Address map: |
---|
479 | HDL is coded [MSB:LSB] = [31:0], per Xilinx's convention for AXI peripherals |
---|
480 | regX[31] maps to 0x80000000 in C driver |
---|
481 | regX[ 0] maps to 0x00000001 in C driver |
---|
482 | |
---|
483 | 0: RW: MAX2829 control signals and control source (sw vs. hw) |
---|
484 | Mask for RFA: 0x000000FF |
---|
485 | Mask for RFB: 0x0000FF00 |
---|
486 | Mask for RFC: 0x00FF0000 |
---|
487 | Mask for RFD: 0xFF000000 |
---|
488 | [31:28] = RFD Control: {TxEn, RxEn, RxHP, SHDN} 0xF0000000 |
---|
489 | [27:24] = RFD Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x0F000000 |
---|
490 | [23:20] = RFC Control: {TxEn, RxEn, RxHP, SHDN} 0x00F00000 |
---|
491 | [19:16] = RFC Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x000F0000 |
---|
492 | [15:12] = RFB Control: {TxEn, RxEn, RxHP, SHDN} 0x0000F000 |
---|
493 | [11: 8] = RFB Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x00000F00 |
---|
494 | [ 7: 4] = RFA Control: {TxEn, RxEn, RxHP, SHDN} 0x000000F0 |
---|
495 | [ 3: 0] = RFA Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x0000000F |
---|
496 | |
---|
497 | 1: RW: Tx Timing |
---|
498 | Shared by all RF interfaces |
---|
499 | [31:24] = Delay before Tx VGA ramp start 0xFF000000 |
---|
500 | [23:16] = Delay before PA enable 0x00FF0000 |
---|
501 | [15: 8] = Delay before MAX2829 TxEn assertion 0x0000FF00 |
---|
502 | [ 7: 0] = Delay before usr_startPHY assertion 0x000000FF |
---|
503 | |
---|
504 | 2: RW: Tx Gains |
---|
505 | [ 31] = RF D Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x80000000 |
---|
506 | [ 30] = Reserved |
---|
507 | [29:24] = RF D Tx Gain 0x3F000000 |
---|
508 | [ 23] = RF C Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00800000 |
---|
509 | [ 22] = Reserved |
---|
510 | [21:16] = RF C Tx Gain 0x003F0000 |
---|
511 | [ 15] = RF B Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00008000 |
---|
512 | [ 14] = Reserved |
---|
513 | [13: 8] = RF B Tx Gain 0x00003F00 |
---|
514 | [ 7] = RF A Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00000080 |
---|
515 | [ 6] = Reserved |
---|
516 | [ 5: 0] = RF A Tx Gain 0x0000003F |
---|
517 | |
---|
518 | 3: RW: Rx gains |
---|
519 | [ 31] = RFD Rx gain ctrl source (0=register values, 1=usr_ ports) 0x80000000 |
---|
520 | [30:29] = RFD Rx RF Gain 0x60000000 |
---|
521 | [28:24] = RFD Rx BB Gain 0x1F000000 |
---|
522 | [ 23] = RFC Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00800000 |
---|
523 | [22:21] = RFC Rx RF Gain 0x00600000 |
---|
524 | [20:16] = RFC Rx BB Gain 0x001F0000 |
---|
525 | [ 15] = RFB Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00008000 |
---|
526 | [14:13] = RFB Rx RF Gain 0x00006000 |
---|
527 | [12: 8] = RFB Rx BB Gain 0x00001F00 |
---|
528 | [ 7] = RFA Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00000080 |
---|
529 | [ 6: 5] = RFA Rx RF Gain 0x00000060 |
---|
530 | [ 4: 0] = RFA Rx BB Gain 0x0000001F |
---|
531 | |
---|
532 | 4: RW: Clock dividers & Tx gain ramp config |
---|
533 | [31:16] = Reserved 0xFFFF0000 |
---|
534 | [15:12] = Tx VGA ramp time step 0x0000F000 |
---|
535 | [11: 8] = Tx VGA ramp gain step 0x00000F00 |
---|
536 | [ 7] = Reserved 0x00000080 |
---|
537 | [ 6: 4] = SPI clock divider 0x00000070 |
---|
538 | [ 3: 2] = Reserved 0x0000000C |
---|
539 | [ 1: 0] = TxTiming clock divider 0x00000003 |
---|
540 | |
---|
541 | 5: WO: SPI write register |
---|
542 | Special register: |
---|
543 | * Write from software triggers SPI transaction |
---|
544 | * IPIF WrACK delayed until SPI is done (i.e. software doesn't have to poll; Xil_Out32 blocks until SPI is done) |
---|
545 | * Reads of this register return last SPI word transferred by software (might be stale, if usr_ SPI ports are also used) |
---|
546 | [31:28] SPI chip select mask RF[D:A] 0x80000000=RFD, 0x40000000=RFC, 0x20000000=RFB, 0x10000000=RFA |
---|
547 | [27:20] Reserved 0x0FF00000 |
---|
548 | [19:16] Register address to write 0x000F0000 |
---|
549 | [15:14] Reserved 0x0000C000 |
---|
550 | [13: 0] Register value to write 0x00003FFF |
---|
551 | |
---|
552 | |
---|
553 | |
---|
554 | 6 to 10: Reserved (RW 32-bit registers implemented; no connection to external hardware) |
---|
555 | |
---|
556 | 11: RO: Status bits |
---|
557 | Same per-RF masks as reg[0], same control signal masks as reg[0] |
---|
558 | [31:28] = RFD control status {TxEn, RxEn, RxHP, SHDN} |
---|
559 | [ 27] = RFD MAX2829 PLL locked (1=locked) |
---|
560 | [ 26] = RFD SPI transfer in progress |
---|
561 | [25:24] = {RFD PA_2 ON, RFD PA_5 ON} |
---|
562 | |
---|
563 | [23:20] = RFC control status {TxEn, RxEn, RxHP, SHDN} |
---|
564 | [ 19] = RFC MAX2829 PLL locked (1=locked) |
---|
565 | [ 18] = RFC SPI transfer in progress |
---|
566 | [17:16] = {RFC PA_2 ON, RFC PA_5 ON} |
---|
567 | |
---|
568 | [15:12] = RFB control status {TxEn, RxEn, RxHP, SHDN} |
---|
569 | [ 11] = RFB MAX2829 PLL locked (1=locked) |
---|
570 | [ 10] = RFB SPI transfer in progress |
---|
571 | [ 9: 8] = {RFB PA_2 ON, RFB PA_5 ON} |
---|
572 | |
---|
573 | [ 7: 4] = RFA control status {TxEn, RxEn, RxHP, SHDN} |
---|
574 | [ 3] = RFA MAX2829 PLL locked (1=locked) |
---|
575 | [ 2] = RFA SPI transfer in progress |
---|
576 | [ 1: 0] = {RFA PA_2 ON, RFA PA_5 ON} |
---|
577 | |
---|
578 | 12 to 63: RO: Read-only registers which mirror state of MAX2829 internal registers (since MAX2829 SPI is write-only) |
---|
579 | * Registers are initialized (on FPGA config and MAX2829 reset) to MAX2829 defaults, to match MAX2829 reset state |
---|
580 | * Register values are updated automatically by SPI writes (via reg4 or via usr_ SPI port use) |
---|
581 | * Every register is: |
---|
582 | [31:14] Reserved; returns 0 on read |
---|
583 | [13: 0] Register value (14 bits) |
---|
584 | |
---|
585 | 12...24: RO: Local copies of MAX2829 registers for RFA |
---|
586 | 12: RFA MAX2829 reg0 |
---|
587 | ... |
---|
588 | 24: RFA MAX2829 regC |
---|
589 | |
---|
590 | 25...37: RO: Local copies of MAX2829 registers for RFB |
---|
591 | 25: RFB MAX2829 reg0 |
---|
592 | ... |
---|
593 | 37: RFB MAX2829 regC |
---|
594 | |
---|
595 | 38...50: RO: Local copies of MAX2829 registers for RFC |
---|
596 | 38: RFC MAX2829 reg0 |
---|
597 | ... |
---|
598 | 50: RFC MAX2829 regC |
---|
599 | |
---|
600 | 51...63: RO: Local copies of MAX2829 registers for RFD |
---|
601 | 51: RFD MAX2829 reg0 |
---|
602 | ... |
---|
603 | 63: RFD MAX2829 regC |
---|
604 | |
---|
605 | */ |
---|
606 | |
---|
607 | //Only regs 0 to 10 can be written; 12 to 63 are RO |
---|
608 | assign slv_reg_write_sel = Bus2IP_WrCE[63:53]; //WrCE[63:0] maps to slv_reg[0:63] |
---|
609 | |
---|
610 | //All regs can be read; ACK all reads immediately |
---|
611 | assign slv_reg_read_sel = Bus2IP_RdCE[63:0]; |
---|
612 | assign slv_read_ack = |Bus2IP_RdCE[63:0]; |
---|
613 | |
---|
614 | //Write ack for reg5 (WrCE[58]) is delayed by SPI transfer |
---|
615 | // All other regs ACK writes immediately |
---|
616 | assign slv_write_ack_normalRegisters = |{Bus2IP_WrCE[63:59], Bus2IP_WrCE[57:53]}; |
---|
617 | |
---|
618 | assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; |
---|
619 | assign IP2Bus_RdAck = slv_read_ack; |
---|
620 | assign IP2Bus_Error = 0; |
---|
621 | |
---|
622 | //spi_tx_reg_write (Bus2IP_WrCE[58]) de-asserts as soon as transaction is ACK'd |
---|
623 | // so this mux switches back to the generic ACK as soon as the SPI xfer is done |
---|
624 | //Thus, the duration of assertion for spi_xfer_done doesn't really matter |
---|
625 | //A bit fast-n-loose, but works ok |
---|
626 | assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack_normalRegisters; |
---|
627 | |
---|
628 | //Register 0: MAX2829 control |
---|
629 | assign {RFD_TxEn_sw, RFD_RxEn_sw, RFD_RxHP_sw, RFD_SHDN_sw} = slv_reg0[31:28]; |
---|
630 | assign {RFD_TxEn_ctrlSrc, RFD_RxEn_ctrlSrc, RFD_RxHP_ctrlSrc, RFD_SHDN_ctrlSrc} = slv_reg0[27:24]; |
---|
631 | |
---|
632 | assign {RFC_TxEn_sw, RFC_RxEn_sw, RFC_RxHP_sw, RFC_SHDN_sw} = slv_reg0[23:20]; |
---|
633 | assign {RFC_TxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFC_RxHP_ctrlSrc, RFC_SHDN_ctrlSrc} = slv_reg0[19:16]; |
---|
634 | |
---|
635 | assign {RFB_TxEn_sw, RFB_RxEn_sw, RFB_RxHP_sw, RFB_SHDN_sw} = slv_reg0[15:12]; |
---|
636 | assign {RFB_TxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFB_RxHP_ctrlSrc, RFB_SHDN_ctrlSrc} = slv_reg0[11:8]; |
---|
637 | |
---|
638 | assign {RFA_TxEn_sw, RFA_RxEn_sw, RFA_RxHP_sw, RFA_SHDN_sw} = slv_reg0[7:4]; |
---|
639 | assign {RFA_TxEn_ctrlSrc, RFA_RxEn_ctrlSrc, RFA_RxHP_ctrlSrc, RFA_SHDN_ctrlSrc} = slv_reg0[3:0]; |
---|
640 | |
---|
641 | |
---|
642 | //Register 1: Tx timing |
---|
643 | assign TxTiming_dly_TxGainRamp = slv_reg1[31:24]; |
---|
644 | assign TxTiming_dly_PowerAmpEn = slv_reg1[23:16]; |
---|
645 | assign TxTiming_dly_TxEn = slv_reg1[15: 8]; |
---|
646 | assign TxTiming_dly_startPHY = slv_reg1[ 7: 0]; |
---|
647 | |
---|
648 | //Register 2: Tx gains |
---|
649 | assign RFD_TxGain_sw = slv_reg2[29:24]; |
---|
650 | assign RFC_TxGain_sw = slv_reg2[21:16]; |
---|
651 | assign RFB_TxGain_sw = slv_reg2[13: 8]; |
---|
652 | assign RFA_TxGain_sw = slv_reg2[ 5: 0]; |
---|
653 | |
---|
654 | assign RFD_TxGain_ctrlSrc = slv_reg2[31]; |
---|
655 | assign RFC_TxGain_ctrlSrc = slv_reg2[23]; |
---|
656 | assign RFB_TxGain_ctrlSrc = slv_reg2[15]; |
---|
657 | assign RFA_TxGain_ctrlSrc = slv_reg2[ 7]; |
---|
658 | |
---|
659 | //Register 3: Rx gains |
---|
660 | assign RFD_RxGainBB_sw = slv_reg3[28:24]; |
---|
661 | assign RFC_RxGainBB_sw = slv_reg3[20:16]; |
---|
662 | assign RFB_RxGainBB_sw = slv_reg3[12: 8]; |
---|
663 | assign RFA_RxGainBB_sw = slv_reg3[ 4: 0]; |
---|
664 | |
---|
665 | assign RFD_RxGainRF_sw = slv_reg3[30:29]; |
---|
666 | assign RFC_RxGainRF_sw = slv_reg3[22:21]; |
---|
667 | assign RFB_RxGainRF_sw = slv_reg3[14:13]; |
---|
668 | assign RFA_RxGainRF_sw = slv_reg3[ 6: 5]; |
---|
669 | |
---|
670 | assign RFD_RxGain_ctrlSrc = slv_reg3[31]; |
---|
671 | assign RFC_RxGain_ctrlSrc = slv_reg3[23]; |
---|
672 | assign RFB_RxGain_ctrlSrc = slv_reg3[15]; |
---|
673 | assign RFA_RxGain_ctrlSrc = slv_reg3[ 7]; |
---|
674 | |
---|
675 | //Register 4: Clock dividers & Tx gain ramp config |
---|
676 | assign TxGainRamp_timeStep = slv_reg4[15:12]; |
---|
677 | assign TxGainRamp_gainStep = slv_reg4[11: 8]; |
---|
678 | assign spi_clk_div_sel = slv_reg4[ 6: 4]; |
---|
679 | assign txTiming_clk_div_sel = slv_reg4[ 1: 0]; |
---|
680 | |
---|
681 | //Register 5: SPI write |
---|
682 | assign spi_rfsel_mask_sw = slv_reg5[31:28]; |
---|
683 | assign spi_tx_regaddr = slv_reg5[19:16]; |
---|
684 | assign spi_tx_regdata = slv_reg5[13: 0]; |
---|
685 | |
---|
686 | //Use the IPIF write-enable for the SPI Tx register as the SPI go |
---|
687 | // The bus will be paused until the SPI transfer is finished |
---|
688 | assign spi_tx_reg_write = Bus2IP_WrCE[58]; |
---|
689 | |
---|
690 | //Register 11: Read-only status bits |
---|
691 | assign status_reg[31:28] = {RFD_TxEn, RFD_RxEn, RFD_RxHP, RFD_SHDN}; |
---|
692 | assign status_reg[27:24] = {RFD_LD, ~RFD_SPI_CSn, RFD_PAEn_24, RFD_PAEn_5}; |
---|
693 | |
---|
694 | assign status_reg[23:20] = {RFC_TxEn, RFC_RxEn, RFC_RxHP, RFC_SHDN}; |
---|
695 | assign status_reg[19:16] = {RFC_LD, ~RFC_SPI_CSn, RFC_PAEn_24, RFC_PAEn_5}; |
---|
696 | |
---|
697 | assign status_reg[15:12] = {RFB_TxEn, RFB_RxEn, RFB_RxHP, RFB_SHDN}; |
---|
698 | assign status_reg[11: 8] = {RFB_LD, ~RFB_SPI_CSn, RFB_PAEn_24, RFB_PAEn_5}; |
---|
699 | |
---|
700 | assign status_reg[ 7: 4] = {RFA_TxEn, RFA_RxEn, RFA_RxHP, RFA_SHDN}; |
---|
701 | assign status_reg[ 3: 0] = {RFA_LD, ~RFA_SPI_CSn, RFA_PAEn_24, RFA_PAEn_5}; |
---|
702 | |
---|
703 | //Mux the various control signals between software and hardware control |
---|
704 | assign RFA_txStart = RFA_TxEn_ctrlSrc ? usr_RFA_TxEn : RFA_TxEn_sw; |
---|
705 | assign RFB_txStart = RFB_TxEn_ctrlSrc ? usr_RFB_TxEn : RFB_TxEn_sw; |
---|
706 | assign RFC_txStart = RFC_TxEn_ctrlSrc ? usr_RFC_TxEn : RFC_TxEn_sw; |
---|
707 | assign RFD_txStart = RFD_TxEn_ctrlSrc ? usr_RFD_TxEn : RFD_TxEn_sw; |
---|
708 | |
---|
709 | assign RFA_RxEn = RFA_RxEn_ctrlSrc ? usr_RFA_RxEn : RFA_RxEn_sw; |
---|
710 | assign RFB_RxEn = RFB_RxEn_ctrlSrc ? usr_RFB_RxEn : RFB_RxEn_sw; |
---|
711 | assign RFC_RxEn = RFC_RxEn_ctrlSrc ? usr_RFC_RxEn : RFC_RxEn_sw; |
---|
712 | assign RFD_RxEn = RFD_RxEn_ctrlSrc ? usr_RFD_RxEn : RFD_RxEn_sw; |
---|
713 | |
---|
714 | assign RFA_RxHP = RFA_RxHP_ctrlSrc ? usr_RFA_RxHP : RFA_RxHP_sw; |
---|
715 | assign RFB_RxHP = RFB_RxHP_ctrlSrc ? usr_RFB_RxHP : RFB_RxHP_sw; |
---|
716 | assign RFC_RxHP = RFC_RxHP_ctrlSrc ? usr_RFC_RxHP : RFC_RxHP_sw; |
---|
717 | assign RFD_RxHP = RFD_RxHP_ctrlSrc ? usr_RFD_RxHP : RFD_RxHP_sw; |
---|
718 | |
---|
719 | assign RFA_SHDN = RFA_SHDN_ctrlSrc ? usr_RFA_SHDN : RFA_SHDN_sw; |
---|
720 | assign RFB_SHDN = RFB_SHDN_ctrlSrc ? usr_RFB_SHDN : RFB_SHDN_sw; |
---|
721 | assign RFC_SHDN = RFC_SHDN_ctrlSrc ? usr_RFC_SHDN : RFC_SHDN_sw; |
---|
722 | assign RFD_SHDN = RFD_SHDN_ctrlSrc ? usr_RFD_SHDN : RFD_SHDN_sw; |
---|
723 | |
---|
724 | assign RFA_TxGain_target = RFA_TxGain_ctrlSrc ? usr_RFA_TxGain : RFA_TxGain_sw; |
---|
725 | assign RFB_TxGain_target = RFB_TxGain_ctrlSrc ? usr_RFB_TxGain : RFB_TxGain_sw; |
---|
726 | assign RFC_TxGain_target = RFC_TxGain_ctrlSrc ? usr_RFC_TxGain : RFC_TxGain_sw; |
---|
727 | assign RFD_TxGain_target = RFD_TxGain_ctrlSrc ? usr_RFD_TxGain : RFD_TxGain_sw; |
---|
728 | |
---|
729 | assign RFA_RxGainBB = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainBB : RFA_RxGainBB_sw; |
---|
730 | assign RFB_RxGainBB = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainBB : RFB_RxGainBB_sw; |
---|
731 | assign RFC_RxGainBB = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainBB : RFC_RxGainBB_sw; |
---|
732 | assign RFD_RxGainBB = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainBB : RFD_RxGainBB_sw; |
---|
733 | |
---|
734 | assign RFA_RxGainRF = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainRF : RFA_RxGainRF_sw; |
---|
735 | assign RFB_RxGainRF = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainRF : RFB_RxGainRF_sw; |
---|
736 | assign RFC_RxGainRF = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainRF : RFC_RxGainRF_sw; |
---|
737 | assign RFD_RxGainRF = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainRF : RFD_RxGainRF_sw; |
---|
738 | |
---|
739 | |
---|
740 | //Output OR'd PHYStart signal (most PHYs use this, so any TxEnable will start the PHY) |
---|
741 | // Individual PHYStarts are provided in case user has multiple PHYs connected to different RF paths |
---|
742 | assign usr_any_PHYStart = usr_RFA_PHYStart || usr_RFB_PHYStart || usr_RFC_PHYStart || usr_RFD_PHYStart; |
---|
743 | |
---|
744 | //SKY13370 needs 100-250nsec to settle, so make the switch as soon as we know Tx process is starting |
---|
745 | //2-bit control signal in hardware, but only two valid states: |
---|
746 | // [V1 V2] = [1 0] => Rx path connected to SMA, Tx path terminated to 50 ohms (PA must be off!) |
---|
747 | // [V1 V2] = [0 1] => Tx path connected to SMA, Rx path terminated to 50 ohms |
---|
748 | //RFx_AntSw[0] = SKY13370.V1, RFx_AntSw[1] = SKY13370.V2 |
---|
749 | assign RFA_AntSw[1:0] = {~RFA_txStart, RFA_txStart}; |
---|
750 | assign RFB_AntSw[1:0] = {~RFB_txStart, RFB_txStart}; |
---|
751 | assign RFC_AntSw[1:0] = {~RFC_txStart, RFC_txStart}; |
---|
752 | assign RFD_AntSw[1:0] = {~RFD_txStart, RFD_txStart}; |
---|
753 | |
---|
754 | //PAs are enabled by single wire per band |
---|
755 | // One path's 2.4 and 5GHz PAs should never be enabled simultaneously |
---|
756 | //2.4GHz PA is on when: |
---|
757 | // TxTiming state machine asserts PAEn AND |
---|
758 | // MAX2829.reg5[0] == 0 (indicating MAX2829 is tuned to 2.4GHz band) |
---|
759 | //5GHz PA is on when: |
---|
760 | // TxTiming state machine asserts PAEn AND |
---|
761 | // MAX2829.reg5[0] == 1 (indicating MAX2829 is tuned to 5GHz band) |
---|
762 | //RFx_MAX2829_mirrorRegs are indexed [MSB:LSB]=[13:0] to match other busses in this core, |
---|
763 | // so the LSB (bit [0] in MAX2829 datasheet) is RFA_MAX2829_mirrorRegs[x][0] here |
---|
764 | assign RFA_PAEn_24 = (RFA_PAEn & ~(RFA_MAX2829_mirrorRegs[5][0])); |
---|
765 | assign RFB_PAEn_24 = (RFB_PAEn & ~(RFB_MAX2829_mirrorRegs[5][0])); |
---|
766 | assign RFC_PAEn_24 = (RFC_PAEn & ~(RFC_MAX2829_mirrorRegs[5][0])); |
---|
767 | assign RFD_PAEn_24 = (RFD_PAEn & ~(RFD_MAX2829_mirrorRegs[5][0])); |
---|
768 | |
---|
769 | assign RFA_PAEn_5 = (RFA_PAEn & (RFA_MAX2829_mirrorRegs[5][0])); |
---|
770 | assign RFB_PAEn_5 = (RFB_PAEn & (RFB_MAX2829_mirrorRegs[5][0])); |
---|
771 | assign RFC_PAEn_5 = (RFC_PAEn & (RFC_MAX2829_mirrorRegs[5][0])); |
---|
772 | assign RFD_PAEn_5 = (RFD_PAEn & (RFD_MAX2829_mirrorRegs[5][0])); |
---|
773 | |
---|
774 | |
---|
775 | //MAX2829 gain control bus |
---|
776 | // radio_controller.RFx_B[6:0] maps to MAX2829.B[7:1] |
---|
777 | // radio_controller.RFx_B[6] is MSB, radio_controller.RFx_B[0] is LSB |
---|
778 | // MAX2829.B7 is MSB, MAX2829.B1 is LSB |
---|
779 | //When SPI gain control is disabled: |
---|
780 | // In Tx mode: |
---|
781 | // MAX2829.B[7] is don't care |
---|
782 | // MAX2829.B[6:1] = Tx RF VGA (6'd63 is max gain, 6'd0 is min gain (approx max-30dB)) |
---|
783 | // In Rx mode: |
---|
784 | // MAX2829.B[7:6] = Rx RF LNA (2'd3 is max gain (30dB), 2'd1 is min gain (0dB), 2'd0 is invalid) |
---|
785 | // MAX2829.B[5:1] = Rx BB VGA (5'd31 is max gain (approx 62dB), 5'd0 is min gain (approx 0dB) |
---|
786 | //assign RFA_B = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB}; |
---|
787 | //assign RFB_B = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB}; |
---|
788 | //assign RFC_B = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB}; |
---|
789 | //assign RFD_B = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB}; |
---|
790 | assign {RFA_B[0], RFA_B[1], RFA_B[2], RFA_B[3], RFA_B[4], RFA_B[5], RFA_B[6]} = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB}; |
---|
791 | assign {RFB_B[0], RFB_B[1], RFB_B[2], RFB_B[3], RFB_B[4], RFB_B[5], RFB_B[6]} = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB}; |
---|
792 | assign {RFC_B[0], RFC_B[1], RFC_B[2], RFC_B[3], RFC_B[4], RFC_B[5], RFC_B[6]} = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB}; |
---|
793 | assign {RFD_B[0], RFD_B[1], RFD_B[2], RFD_B[3], RFD_B[4], RFD_B[5], RFD_B[6]} = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB}; |
---|
794 | |
---|
795 | //Simple state machines for fixed timing of Tx events (MAX2829 TxEn, PA enable and PHY start) |
---|
796 | // One per RF path, to handle case of user designs which do Tx/Rx asychronously across paths |
---|
797 | // All use same timing values, as these are really tuned to the hardware, not the Tx signal |
---|
798 | radio_controller_TxTiming RFA_txTiming ( |
---|
799 | .clk(Bus2IP_Clk), |
---|
800 | .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low |
---|
801 | |
---|
802 | .clk_div(txTiming_clk_div_sel), |
---|
803 | |
---|
804 | .sw_start(RFA_txStart), |
---|
805 | |
---|
806 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
807 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
808 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
809 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
810 | |
---|
811 | .gainRamp_TxGainTarget(RFA_TxGain_target), |
---|
812 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
813 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
814 | .gainRamp_TxGainOut(RFA_TxGain_ramped), |
---|
815 | |
---|
816 | .TxEn(RFA_TxEn), |
---|
817 | .PAEn(RFA_PAEn), |
---|
818 | .PHYStart(usr_RFA_PHYStart) |
---|
819 | ); |
---|
820 | radio_controller_TxTiming RFB_txTiming ( |
---|
821 | .clk(Bus2IP_Clk), |
---|
822 | .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low |
---|
823 | |
---|
824 | .clk_div(txTiming_clk_div_sel), |
---|
825 | |
---|
826 | .sw_start(RFB_txStart), |
---|
827 | |
---|
828 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
829 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
830 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
831 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
832 | |
---|
833 | .gainRamp_TxGainTarget(RFB_TxGain_target), |
---|
834 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
835 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
836 | .gainRamp_TxGainOut(RFB_TxGain_ramped), |
---|
837 | |
---|
838 | .TxEn(RFB_TxEn), |
---|
839 | .PAEn(RFB_PAEn), |
---|
840 | .PHYStart(usr_RFB_PHYStart) |
---|
841 | ); |
---|
842 | radio_controller_TxTiming RFC_txTiming ( |
---|
843 | .clk(Bus2IP_Clk), |
---|
844 | .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low |
---|
845 | |
---|
846 | .clk_div(txTiming_clk_div_sel), |
---|
847 | |
---|
848 | .sw_start(RFC_txStart), |
---|
849 | |
---|
850 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
851 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
852 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
853 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
854 | |
---|
855 | .gainRamp_TxGainTarget(RFC_TxGain_target), |
---|
856 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
857 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
858 | .gainRamp_TxGainOut(RFC_TxGain_ramped), |
---|
859 | |
---|
860 | .TxEn(RFC_TxEn), |
---|
861 | .PAEn(RFC_PAEn), |
---|
862 | .PHYStart(usr_RFC_PHYStart) |
---|
863 | ); |
---|
864 | radio_controller_TxTiming RFD_txTiming ( |
---|
865 | .clk(Bus2IP_Clk), |
---|
866 | .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low |
---|
867 | |
---|
868 | .clk_div(txTiming_clk_div_sel), |
---|
869 | |
---|
870 | .sw_start(RFD_txStart), |
---|
871 | |
---|
872 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
873 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
874 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
875 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
876 | |
---|
877 | .gainRamp_TxGainTarget(RFD_TxGain_target), |
---|
878 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
879 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
880 | .gainRamp_TxGainOut(RFD_TxGain_ramped), |
---|
881 | |
---|
882 | .TxEn(RFD_TxEn), |
---|
883 | .PAEn(RFD_PAEn), |
---|
884 | .PHYStart(usr_RFD_PHYStart) |
---|
885 | ); |
---|
886 | |
---|
887 | //Signals to detect when MAX2829 hardware reset occurs (TxEn=1, RxEn=1, SHDN=0) |
---|
888 | // Reset can be triggered by hardware or software, depending on the user config |
---|
889 | assign RFA_MAX2829_Reset = (RFA_TxEn & RFA_RxEn & ~RFA_SHDN); |
---|
890 | assign RFB_MAX2829_Reset = (RFB_TxEn & RFB_RxEn & ~RFB_SHDN); |
---|
891 | assign RFC_MAX2829_Reset = (RFC_TxEn & RFC_RxEn & ~RFC_SHDN); |
---|
892 | assign RFD_MAX2829_Reset = (RFD_TxEn & RFD_RxEn & ~RFD_SHDN); |
---|
893 | |
---|
894 | //Use a counter to generate a blinking error signal to indicate a radio in standby that hasn't yet locked |
---|
895 | reg [23:0] error_blink_counter = 24'b0; |
---|
896 | always @(posedge Bus2IP_Clk) |
---|
897 | error_blink_counter <= error_blink_counter + 1; |
---|
898 | |
---|
899 | assign usr_RFA_statLED_Tx = RFA_SHDN ? (RFA_TxEn | ((~RFA_LD) & error_blink_counter[23])) : 1'b0; |
---|
900 | assign usr_RFA_statLED_Rx = RFA_SHDN ? (RFA_RxEn | ((~RFA_LD) & error_blink_counter[23])) : 1'b0;; |
---|
901 | |
---|
902 | assign usr_RFB_statLED_Tx = RFB_SHDN ? (RFB_TxEn | ((~RFB_LD) & error_blink_counter[23])) : 1'b0; |
---|
903 | assign usr_RFB_statLED_Rx = RFB_SHDN ? (RFB_RxEn | ((~RFB_LD) & error_blink_counter[23])) : 1'b0;; |
---|
904 | |
---|
905 | assign usr_RFC_statLED_Tx = RFC_SHDN ? (RFC_TxEn | ((~RFC_LD) & error_blink_counter[23])) : 1'b0; |
---|
906 | assign usr_RFC_statLED_Rx = RFC_SHDN ? (RFC_RxEn | ((~RFC_LD) & error_blink_counter[23])) : 1'b0;; |
---|
907 | |
---|
908 | assign usr_RFD_statLED_Tx = RFD_SHDN ? (RFD_TxEn | ((~RFD_LD) & error_blink_counter[23])) : 1'b0; |
---|
909 | assign usr_RFD_statLED_Rx = RFD_SHDN ? (RFD_RxEn | ((~RFD_LD) & error_blink_counter[23])) : 1'b0;; |
---|
910 | |
---|
911 | |
---|
912 | //Mask per-RF path to enable SPI transactions |
---|
913 | // Driven by register for software control, usr_ port for hardware control |
---|
914 | assign spi_rfsel_mask = usr_SPI_ctrlSrc ? usr_SPI_rfsel : spi_rfsel_mask_sw; |
---|
915 | |
---|
916 | |
---|
917 | //Processes to update mirror registers following SPI write |
---|
918 | // Note these registers are *not* changed by a software reset |
---|
919 | // The only reset condition is the MAX2829 hardware reset (TxEn=1, RxEn=1, SHDN=0) |
---|
920 | always @(posedge Bus2IP_Clk) |
---|
921 | begin |
---|
922 | if(RFA_MAX2829_Reset) |
---|
923 | begin |
---|
924 | RFA_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
---|
925 | RFA_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
---|
926 | RFA_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
---|
927 | RFA_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
---|
928 | RFA_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
---|
929 | RFA_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
---|
930 | RFA_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
---|
931 | RFA_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
---|
932 | RFA_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
---|
933 | RFA_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
---|
934 | RFA_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
---|
935 | RFA_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
---|
936 | RFA_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
---|
937 | end |
---|
938 | else if(spi_go) |
---|
939 | begin |
---|
940 | if(spi_rfsel_mask & 4'b0001) //RFA selected |
---|
941 | RFA_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata; |
---|
942 | end |
---|
943 | end |
---|
944 | |
---|
945 | always @(posedge Bus2IP_Clk) |
---|
946 | begin |
---|
947 | if(RFB_MAX2829_Reset) |
---|
948 | begin |
---|
949 | RFB_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
---|
950 | RFB_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
---|
951 | RFB_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
---|
952 | RFB_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
---|
953 | RFB_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
---|
954 | RFB_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
---|
955 | RFB_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
---|
956 | RFB_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
---|
957 | RFB_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
---|
958 | RFB_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
---|
959 | RFB_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
---|
960 | RFB_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
---|
961 | RFB_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
---|
962 | end |
---|
963 | else if(spi_go) |
---|
964 | begin |
---|
965 | if(spi_rfsel_mask & 4'b0010) //RFB selected |
---|
966 | RFB_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata; |
---|
967 | end |
---|
968 | end |
---|
969 | |
---|
970 | always @(posedge Bus2IP_Clk) |
---|
971 | begin |
---|
972 | if(RFC_MAX2829_Reset) |
---|
973 | begin |
---|
974 | RFC_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
---|
975 | RFC_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
---|
976 | RFC_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
---|
977 | RFC_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
---|
978 | RFC_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
---|
979 | RFC_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
---|
980 | RFC_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
---|
981 | RFC_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
---|
982 | RFC_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
---|
983 | RFC_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
---|
984 | RFC_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
---|
985 | RFC_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
---|
986 | RFC_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
---|
987 | end |
---|
988 | else if(spi_go) |
---|
989 | begin |
---|
990 | if(spi_rfsel_mask & 4'b0100) //RFC selected |
---|
991 | RFC_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata; |
---|
992 | end |
---|
993 | end |
---|
994 | |
---|
995 | always @(posedge Bus2IP_Clk) |
---|
996 | begin |
---|
997 | if(RFD_MAX2829_Reset) |
---|
998 | begin |
---|
999 | RFD_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
---|
1000 | RFD_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
---|
1001 | RFD_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
---|
1002 | RFD_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
---|
1003 | RFD_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
---|
1004 | RFD_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
---|
1005 | RFD_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
---|
1006 | RFD_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
---|
1007 | RFD_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
---|
1008 | RFD_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
---|
1009 | RFD_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
---|
1010 | RFD_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
---|
1011 | RFD_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
---|
1012 | end |
---|
1013 | else if(spi_go) |
---|
1014 | begin |
---|
1015 | if(spi_rfsel_mask & 4'b1000) //RFD selected |
---|
1016 | RFD_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata; |
---|
1017 | end |
---|
1018 | end |
---|
1019 | |
---|
1020 | //MAX2829 CS is active-low; warp_spi_io.spi_cs is active high |
---|
1021 | assign RFA_SPI_CSn = ~(spi_rfsel_mask[0] & spi_cs); |
---|
1022 | assign RFB_SPI_CSn = ~(spi_rfsel_mask[1] & spi_cs); |
---|
1023 | assign RFC_SPI_CSn = ~(spi_rfsel_mask[2] & spi_cs); |
---|
1024 | assign RFD_SPI_CSn = ~(spi_rfsel_mask[3] & spi_cs); |
---|
1025 | |
---|
1026 | assign RFA_SPI_MOSI = spi_mosi; |
---|
1027 | assign RFB_SPI_MOSI = spi_mosi; |
---|
1028 | assign RFC_SPI_MOSI = spi_mosi; |
---|
1029 | assign RFD_SPI_MOSI = spi_mosi; |
---|
1030 | |
---|
1031 | //Mask each SCLK output by the corresponding CS |
---|
1032 | // No point toggling SCLKs that will be ignored |
---|
1033 | assign RFA_SPI_SCLK = (spi_sclk & spi_rfsel_mask[0]); |
---|
1034 | assign RFB_SPI_SCLK = (spi_sclk & spi_rfsel_mask[1]); |
---|
1035 | assign RFC_SPI_SCLK = (spi_sclk & spi_rfsel_mask[2]); |
---|
1036 | assign RFD_SPI_SCLK = (spi_sclk & spi_rfsel_mask[3]); |
---|
1037 | |
---|
1038 | //MAX2829 SPI uses 18-bit transfers, formatted as {regData[13:0] regAddr[3:0]}, data and addr both transfer MSB first |
---|
1039 | wire [17:0] spi_tx_data_word; |
---|
1040 | assign spi_tx_data_word[17:0] = usr_SPI_ctrlSrc ? {usr_SPI_regdata, usr_SPI_regaddr} : {spi_tx_regdata, spi_tx_regaddr}; |
---|
1041 | |
---|
1042 | assign spi_go = usr_SPI_ctrlSrc ? usr_SPI_go : spi_tx_reg_write; |
---|
1043 | |
---|
1044 | assign usr_SPI_active = spi_cs; |
---|
1045 | |
---|
1046 | warp_spi_io #(.SPI_XFER_LEN(18)) spi_io ( |
---|
1047 | .sys_clk(Bus2IP_Clk), |
---|
1048 | .reset(~Bus2IP_Resetn),//reset input is active high, IPIF resetn is active low |
---|
1049 | .go(spi_go), |
---|
1050 | .done(spi_xfer_done), |
---|
1051 | .clkDiv(spi_clk_div_sel), |
---|
1052 | |
---|
1053 | .currBitNum(), |
---|
1054 | |
---|
1055 | .txData({14'b0, spi_tx_data_word}), |
---|
1056 | |
---|
1057 | .rxData1(), |
---|
1058 | .rxData2(), |
---|
1059 | .rxData3(), |
---|
1060 | .rxData4(), |
---|
1061 | |
---|
1062 | .spi_cs(spi_cs), |
---|
1063 | .spi_sclk(spi_sclk), |
---|
1064 | |
---|
1065 | .spi_mosi(spi_mosi), |
---|
1066 | |
---|
1067 | .spi_miso1(1'b0), |
---|
1068 | .spi_miso2(1'b0), |
---|
1069 | .spi_miso3(1'b0), |
---|
1070 | .spi_miso4(1'b0) |
---|
1071 | ); |
---|
1072 | |
---|
1073 | endmodule |
---|