1 | module radio_controller_TxTiming |
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2 | ( |
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3 | input clk, |
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4 | input reset, |
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5 | |
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6 | input [0:1] clk_div, |
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7 | |
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8 | input sw_start, |
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9 | |
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10 | input [0:7] dly_GainRamp, |
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11 | input [0:7] dly_TxEn, |
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12 | input [0:7] dly_PHYStart, |
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13 | input [0:7] dly_PowerAmpEn, |
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14 | |
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15 | input [0:5] gainRamp_TxGainTarget, |
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16 | input [0:3] gainRamp_GainStep, |
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17 | input [0:3] gainRamp_TimeStep, |
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18 | |
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19 | output [0:5] gainRamp_TxGainOut, |
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20 | |
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21 | output reg TxEn, |
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22 | output reg PAEn, |
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23 | output reg PHYStart |
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24 | ); |
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25 | |
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26 | reg [0:11] timing_counter_big; |
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27 | reg [0: 7] timing_counter; |
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28 | |
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29 | //clk_div = 0 -> Select 8 LSB for fastest processing ([4:11]) |
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30 | //clk_div = 3 -> Select 8 MSB for slowest processing ([1:8]) |
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31 | |
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32 | wire TxEn_i; |
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33 | wire PAEn_i; |
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34 | wire PHYStart_i; |
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35 | |
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36 | always @(posedge clk) |
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37 | begin |
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38 | TxEn <= TxEn_i; |
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39 | PAEn <= PAEn_i; |
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40 | PHYStart <= PHYStart_i; |
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41 | end |
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42 | |
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43 | always @* |
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44 | begin |
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45 | case(clk_div) |
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46 | 2'b00: timing_counter <= timing_counter_big[3:10]; |
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47 | 2'b01: timing_counter <= timing_counter_big[2:9]; |
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48 | 2'b10: timing_counter <= timing_counter_big[1:8]; |
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49 | 2'b11: timing_counter <= timing_counter_big[0:7]; |
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50 | endcase |
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51 | end |
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52 | |
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53 | //Enable the outputs when the timing counter has excedded the various control thresholds given by the dly_* inputs |
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54 | // A delay value of 254 will hold the corresponding output high forever |
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55 | // A delay value of 255 will hold the corresponding output low forever |
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56 | assign TxEn_i = (((timing_counter > dly_TxEn) || dly_TxEn == 8'd254) && dly_TxEn != 8'd255); |
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57 | assign PAEn_i = (((timing_counter > dly_PowerAmpEn) || dly_PowerAmpEn == 8'd254)&& dly_PowerAmpEn != 8'd255); |
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58 | assign PHYStart_i = (((timing_counter > dly_PHYStart) || dly_PHYStart == 8'd254) && dly_PHYStart != 8'd255);; |
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59 | |
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60 | //Instantiate a counter that starts when the software enables Tx mode and stops at its max value |
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61 | // The counter used for timing is sliced from this big counter |
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62 | always @( posedge clk ) |
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63 | begin |
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64 | if(reset | ~sw_start) |
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65 | timing_counter_big <= 0; |
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66 | else if(sw_start & timing_counter < 255) |
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67 | timing_counter_big <= timing_counter_big + 1; |
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68 | end |
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69 | |
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70 | |
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71 | //Tx gain ramp logic |
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72 | // Tx gain output starts at zero |
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73 | // Once master counte reaches dly_GainRamp, Tx gain output begins incrementing |
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74 | // Gain increments by gainRamp_GainStep every gainRamp_TimeStep cycles until reaching gainRamp_TxGainTarget |
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75 | // Gain remains at gainRamp_TxGainTarget until Tx is disabled and process starts over |
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76 | wire GainRampEn; |
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77 | wire [0:6] NewTxGain; |
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78 | reg [0:6] TxGainAccum; |
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79 | reg [0:3] GainRamp_clockEn_counter; |
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80 | |
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81 | wire [0:3] gainRamp_TimeStep_safe; |
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82 | wire [0:3] gainRamp_GainStep_safe; |
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83 | |
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84 | //If user inputs are zero, force them to 1 to avoid stalling the logic below |
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85 | // To bypass/disable the ramp, use 254/255 for dly_GainRamp |
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86 | assign gainRamp_TimeStep_safe = (gainRamp_TimeStep == 0) ? 4'd1 : gainRamp_TimeStep; |
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87 | assign gainRamp_GainStep_safe = (gainRamp_GainStep == 0) ? 4'd1 : gainRamp_GainStep; |
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88 | |
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89 | //Start the gain ramp after the specified delay |
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90 | // A delay of 254 bypasses the ramp and holds the output gain at the target indefinitely |
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91 | // A delay of 255 disables the remp and holds the output gain at 0 |
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92 | assign GainRampEn = (((timing_counter > dly_GainRamp) || dly_GainRamp == 8'd254) && dly_GainRamp != 8'd255); |
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93 | |
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94 | //The output gain signal is the output of an accumulator, enabled after dly_RampGain clock cycles |
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95 | //This signal is the input to the accumulator register. TxGainAccum has one extra MSB to ease overflow detection |
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96 | assign NewTxGain = ( (TxGainAccum + gainRamp_GainStep_safe) > gainRamp_TxGainTarget) ? gainRamp_TxGainTarget : (TxGainAccum + gainRamp_GainStep_safe); |
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97 | |
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98 | //The hw_TxGain output, which eventually connects to the radio's parallel gain control bus, |
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99 | // gets the 6 LSB of the internal accumulator value |
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100 | assign gainRamp_TxGainOut = TxGainAccum[1:6]; |
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101 | |
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102 | //Instiantiates a counter which runs once the timing counter exceeds the threshold |
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103 | // for starting the ramping of Tx gains; the counter increments every (TxGain_rampTimeStep+1) cycles |
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104 | always @( posedge clk ) |
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105 | begin |
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106 | if(reset || (~sw_start) || (~GainRampEn)) |
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107 | TxGainAccum <= 0; |
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108 | else if( GainRampEn & (GainRamp_clockEn_counter == gainRamp_TimeStep_safe)) |
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109 | TxGainAccum <= NewTxGain; |
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110 | end |
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111 | |
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112 | //Instantiate a counter used to drive the clock enable of the gain ramp counter above |
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113 | always @( posedge clk ) |
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114 | begin |
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115 | if(reset || (~sw_start) || (~GainRampEn) || (GainRamp_clockEn_counter == gainRamp_TimeStep_safe)) |
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116 | GainRamp_clockEn_counter <= 0; |
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117 | else |
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118 | GainRamp_clockEn_counter <= GainRamp_clockEn_counter + 1; |
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119 | end |
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120 | |
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121 | |
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122 | endmodule |
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