//---------------------------------------------------------------------------- // user_logic.v - module //---------------------------------------------------------------------------- // // *************************************************************************** // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** // ** ** // ** Xilinx, Inc. ** // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** // ** FOR A PARTICULAR PURPOSE. ** // ** ** // *************************************************************************** // //---------------------------------------------------------------------------- // Filename: user_logic.v // Version: 3.00.c // Description: User logic module. // Date: Tue Feb 26 20:52:28 2013 (by Create and Import Peripheral Wizard) // Verilog Standard: Verilog-2001 //---------------------------------------------------------------------------- // Naming Conventions: // active low signals: "*_n" // clock signals: "clk", "clk_div#", "clk_#x" // reset signals: "rst", "rst_n" // generics: "C_*" // user defined types: "*_TYPE" // state machine next state: "*_ns" // state machine current state: "*_cs" // combinatorial signals: "*_com" // pipelined or register delay signals: "*_d#" // counter signals: "*cnt*" // clock enable signals: "*_ce" // internal version of output port: "*_i" // device pins: "*_pin" // ports: "- Names begin with Uppercase" // processes: "*_PROCESS" // component instantiations: "I_<#|FUNC>" //---------------------------------------------------------------------------- `uselib lib=unisims_ver `uselib lib=proc_common_v3_00_a module user_logic ( // -- ADD USER PORTS BELOW THIS LINE --------------- //I/O for MAX2829 pins output reg RFA_TxEn, output reg RFB_TxEn, output reg RFC_TxEn, output reg RFD_TxEn, output reg RFA_RxEn, output reg RFB_RxEn, output reg RFC_RxEn, output reg RFD_RxEn, output reg RFA_RxHP, output reg RFB_RxHP, output reg RFC_RxHP, output reg RFD_RxHP, output reg RFA_SHDN, output reg RFB_SHDN, output reg RFC_SHDN, output reg RFD_SHDN, output RFA_SPI_SCLK, output RFB_SPI_SCLK, output RFC_SPI_SCLK, output RFD_SPI_SCLK, output RFA_SPI_MOSI, output RFB_SPI_MOSI, output RFC_SPI_MOSI, output RFD_SPI_MOSI, output RFA_SPI_CSn, output RFB_SPI_CSn, output RFC_SPI_CSn, output RFD_SPI_CSn, output reg [6:0] RFA_B, output reg [6:0] RFB_B, output reg [6:0] RFC_B, output reg [6:0] RFD_B, input RFA_LD, input RFB_LD, input RFC_LD, input RFD_LD, //Outputs to PA and ant switch pins output reg RFA_PAEn_24, output reg RFB_PAEn_24, output reg RFC_PAEn_24, output reg RFD_PAEn_24, output reg RFA_PAEn_5, output reg RFB_PAEn_5, output reg RFC_PAEn_5, output reg RFD_PAEn_5, output reg [1:0] RFA_AntSw, output reg [1:0] RFB_AntSw, output reg [1:0] RFC_AntSw, output reg [1:0] RFD_AntSw, //I/O for user logic to control state from hardware input usr_RFA_TxEn, input usr_RFB_TxEn, input usr_RFC_TxEn, input usr_RFD_TxEn, input usr_RFA_RxEn, input usr_RFB_RxEn, input usr_RFC_RxEn, input usr_RFD_RxEn, input usr_RFA_RxHP, input usr_RFB_RxHP, input usr_RFC_RxHP, input usr_RFD_RxHP, input usr_RFA_SHDN, input usr_RFB_SHDN, input usr_RFC_SHDN, input usr_RFD_SHDN, input [1:0] usr_RFA_RxGainRF, input [1:0] usr_RFB_RxGainRF, input [1:0] usr_RFC_RxGainRF, input [1:0] usr_RFD_RxGainRF, input [4:0] usr_RFA_RxGainBB, input [4:0] usr_RFB_RxGainBB, input [4:0] usr_RFC_RxGainBB, input [4:0] usr_RFD_RxGainBB, input [5:0] usr_RFA_TxGain, input [5:0] usr_RFB_TxGain, input [5:0] usr_RFC_TxGain, input [5:0] usr_RFD_TxGain, input usr_SPI_ctrlSrc, input usr_SPI_go, output usr_SPI_active, input [3:0] usr_SPI_rfsel, input [3:0] usr_SPI_regaddr, input [13:0] usr_SPI_regdata, output usr_RFA_PHYStart, output usr_RFB_PHYStart, output usr_RFC_PHYStart, output usr_RFD_PHYStart, output usr_any_PHYStart, output reg usr_RFA_statLED_Tx, output reg usr_RFA_statLED_Rx, output reg usr_RFB_statLED_Tx, output reg usr_RFB_statLED_Rx, output reg usr_RFC_statLED_Tx, output reg usr_RFC_statLED_Rx, output reg usr_RFD_statLED_Tx, output reg usr_RFD_statLED_Rx, // -- ADD USER PORTS ABOVE THIS LINE --------------- // -- DO NOT EDIT BELOW THIS LINE ------------------ // -- Bus protocol ports, do not add to or delete input Bus2IP_Clk, input Bus2IP_Resetn, input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data, input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE, input [C_NUM_REG-1 : 0] Bus2IP_RdCE, input [C_NUM_REG-1 : 0] Bus2IP_WrCE, output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data, output IP2Bus_RdAck, output IP2Bus_WrAck, output IP2Bus_Error // -- DO NOT EDIT ABOVE THIS LINE ------------------ ); // user_logic // -- ADD USER PARAMETERS BELOW THIS LINE ------------ // --USER parameters added here // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ // -- DO NOT EDIT BELOW THIS LINE -------------------- // -- Bus protocol parameters, do not add to or delete //parameter C_NUM_REG = 30; parameter C_NUM_REG = 64; parameter C_SLV_DWIDTH = 32; // -- DO NOT EDIT ABOVE THIS LINE -------------------- // -- ADD USER PORTS BELOW THIS LINE ----------------- // --USER ports added here // -- ADD USER PORTS ABOVE THIS LINE ----------------- // -- DO NOT EDIT BELOW THIS LINE -------------------- // -- Bus protocol ports, do not add to or delete /* Moved to module declaration above input Bus2IP_Clk; input Bus2IP_Resetn; input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; input [C_NUM_REG-1 : 0] Bus2IP_RdCE; input [C_NUM_REG-1 : 0] Bus2IP_WrCE; output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; output IP2Bus_RdAck; output IP2Bus_WrAck; output IP2Bus_Error; */ // -- DO NOT EDIT ABOVE THIS LINE -------------------- //---------------------------------------------------------------------------- // Implementation //---------------------------------------------------------------------------- // --USER nets declarations added here, as needed for user logic `define TXTIMING_REG_ON_RESET 32'h10305020 //Sane default Tx Timing values `define TXGAINS_REG_ON_RESET 32'h32323232 //Tx Gain targets = 50 `define CLKDIV_GAINTIMING_REG_ON_RESET 32'h00004F22 //Gain step=0xF, time step=4, clk divs = 2 // Nets for user logic slave model s/w accessible register example reg [C_SLV_DWIDTH-1 : 0] slv_reg0; reg [C_SLV_DWIDTH-1 : 0] slv_reg1; reg [C_SLV_DWIDTH-1 : 0] slv_reg2; reg [C_SLV_DWIDTH-1 : 0] slv_reg3; reg [C_SLV_DWIDTH-1 : 0] slv_reg4; reg [C_SLV_DWIDTH-1 : 0] slv_reg5; reg [C_SLV_DWIDTH-1 : 0] slv_reg6; reg [C_SLV_DWIDTH-1 : 0] slv_reg7; reg [C_SLV_DWIDTH-1 : 0] slv_reg8; reg [C_SLV_DWIDTH-1 : 0] slv_reg9; reg [C_SLV_DWIDTH-1 : 0] slv_reg10; wire [10 : 0] slv_reg_write_sel; wire [63 : 0] slv_reg_read_sel; reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; wire slv_read_ack; wire slv_write_ack; integer byte_index, bit_index; wire slv_write_ack_normalRegisters; wire [31:0] status_reg; //Use Verilog array-of-arrays syntax for the register banks to mirror MAX2829 internal registers // RFx_MAX2829_mirrorRegs[N] maps to MAX2829 reg N, for N=[0x0, 0xC] // All registers are 14 bits in the MAX2829 wire [13:0] RFA_mirrorReg_data [12:0]; wire [13:0] RFB_mirrorReg_data [12:0]; wire [13:0] RFC_mirrorReg_data [12:0]; wire [13:0] RFD_mirrorReg_data [12:0]; wire RFA_TxEn_ctrlSrc, RFB_TxEn_ctrlSrc, RFC_TxEn_ctrlSrc, RFD_TxEn_ctrlSrc; wire RFA_RxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFD_RxEn_ctrlSrc; wire RFA_RxHP_ctrlSrc, RFB_RxHP_ctrlSrc, RFC_RxHP_ctrlSrc, RFD_RxHP_ctrlSrc; wire RFA_SHDN_ctrlSrc, RFB_SHDN_ctrlSrc, RFC_SHDN_ctrlSrc, RFD_SHDN_ctrlSrc; wire RFA_TxGain_ctrlSrc, RFB_TxGain_ctrlSrc, RFC_TxGain_ctrlSrc, RFD_TxGain_ctrlSrc; wire RFA_RxGain_ctrlSrc, RFB_RxGain_ctrlSrc, RFC_RxGain_ctrlSrc, RFD_RxGain_ctrlSrc; wire RFA_TxEn_sw, RFB_TxEn_sw, RFC_TxEn_sw, RFD_TxEn_sw; wire RFA_RxEn_sw, RFB_RxEn_sw, RFC_RxEn_sw, RFD_RxEn_sw; wire RFA_RxHP_sw, RFB_RxHP_sw, RFC_RxHP_sw, RFD_RxHP_sw; wire RFA_SHDN_sw, RFB_SHDN_sw, RFC_SHDN_sw, RFD_SHDN_sw; wire RFA_PAEn, RFB_PAEn, RFC_PAEn, RFD_PAEn; wire [7:0] TxTiming_dly_TxGainRamp, TxTiming_dly_PowerAmpEn, TxTiming_dly_TxEn, TxTiming_dly_startPHY; wire [3:0] TxGainRamp_gainStep, TxGainRamp_timeStep; wire [5:0] RFA_TxGain_sw, RFB_TxGain_sw, RFC_TxGain_sw, RFD_TxGain_sw; wire [4:0] RFA_RxGainBB_sw, RFB_RxGainBB_sw, RFC_RxGainBB_sw, RFD_RxGainBB_sw; wire [1:0] RFA_RxGainRF_sw, RFB_RxGainRF_sw, RFC_RxGainRF_sw, RFD_RxGainRF_sw; wire [5:0] RFA_TxGain_target, RFB_TxGain_target, RFC_TxGain_target, RFD_TxGain_target; wire [5:0] RFA_TxGain_ramped, RFB_TxGain_ramped, RFC_TxGain_ramped, RFD_TxGain_ramped; wire [4:0] RFA_RxGainBB, RFB_RxGainBB, RFC_RxGainBB, RFD_RxGainBB; wire [1:0] RFA_RxGainRF, RFB_RxGainRF, RFC_RxGainRF, RFD_RxGainRF; wire [2:0] spi_clk_div_sel; wire [1:0] txTiming_clk_div_sel; wire [3:0] spi_rfsel_mask_sw; wire [3:0] spi_rfsel_mask; wire [13:0] spi_tx_regdata; wire [3:0] spi_tx_regaddr; wire spi_go; wire spi_tx_reg_write; wire spi_xfer_done; wire RFA_txStart, RFB_txStart, RFC_txStart, RFD_txStart; wire RFA_MAX2829_Reset, RFB_MAX2829_Reset, RFC_MAX2829_Reset, RFD_MAX2829_Reset; reg RFA_MAX2829_Reset_d, RFB_MAX2829_Reset_d, RFC_MAX2829_Reset_d, RFD_MAX2829_Reset_d; //Register all outputs to the radios wire RFA_TxEn_w; wire RFB_TxEn_w; wire RFC_TxEn_w; wire RFD_TxEn_w; wire RFA_RxEn_w; wire RFB_RxEn_w; wire RFC_RxEn_w; wire RFD_RxEn_w; wire RFA_RxHP_w; wire RFB_RxHP_w; wire RFC_RxHP_w; wire RFD_RxHP_w; wire RFA_SHDN_w; wire RFB_SHDN_w; wire RFC_SHDN_w; wire RFD_SHDN_w; wire RFA_PAEn_24_w; wire RFB_PAEn_24_w; wire RFC_PAEn_24_w; wire RFD_PAEn_24_w; wire RFA_PAEn_5_w; wire RFB_PAEn_5_w; wire RFC_PAEn_5_w; wire RFD_PAEn_5_w; wire [6:0] RFA_B_w; wire [6:0] RFB_B_w; wire [6:0] RFC_B_w; wire [6:0] RFD_B_w; wire [1:0] RFA_AntSw_w; wire [1:0] RFB_AntSw_w; wire [1:0] RFC_AntSw_w; wire [1:0] RFD_AntSw_w; always @(posedge Bus2IP_Clk) begin RFA_TxEn <= RFA_TxEn_w; RFB_TxEn <= RFB_TxEn_w; RFC_TxEn <= RFC_TxEn_w; RFD_TxEn <= RFD_TxEn_w; RFA_RxEn <= RFA_RxEn_w; RFB_RxEn <= RFB_RxEn_w; RFC_RxEn <= RFC_RxEn_w; RFD_RxEn <= RFD_RxEn_w; RFA_RxHP <= RFA_RxHP_w; RFB_RxHP <= RFB_RxHP_w; RFC_RxHP <= RFC_RxHP_w; RFD_RxHP <= RFD_RxHP_w; RFA_SHDN <= RFA_SHDN_w; RFB_SHDN <= RFB_SHDN_w; RFC_SHDN <= RFC_SHDN_w; RFD_SHDN <= RFD_SHDN_w; RFA_PAEn_24 <= RFA_PAEn_24_w; RFB_PAEn_24 <= RFB_PAEn_24_w; RFC_PAEn_24 <= RFC_PAEn_24_w; RFD_PAEn_24 <= RFD_PAEn_24_w; RFA_PAEn_5 <= RFA_PAEn_5_w; RFB_PAEn_5 <= RFB_PAEn_5_w; RFC_PAEn_5 <= RFC_PAEn_5_w; RFD_PAEn_5 <= RFD_PAEn_5_w; RFA_B <= RFA_B_w; RFB_B <= RFB_B_w; RFC_B <= RFC_B_w; RFD_B <= RFD_B_w; RFA_AntSw <= RFA_AntSw_w; RFB_AntSw <= RFB_AntSw_w; RFC_AntSw <= RFC_AntSw_w; RFD_AntSw <= RFD_AntSw_w; end //Register combinational reset signal here for lower fanout always @(posedge Bus2IP_Clk) begin RFA_MAX2829_Reset_d <= RFA_MAX2829_Reset; RFB_MAX2829_Reset_d <= RFB_MAX2829_Reset; RFC_MAX2829_Reset_d <= RFC_MAX2829_Reset; RFD_MAX2829_Reset_d <= RFD_MAX2829_Reset; end // Slave register write process; only implemented for RW and WO registers always @( posedge Bus2IP_Clk ) begin if ( Bus2IP_Resetn == 1'b0 ) begin slv_reg0 <= 0; //All zeros on reset- Tx/Rx disabled, SHDN (active low) enabled slv_reg1 <= `TXTIMING_REG_ON_RESET; slv_reg2 <= `TXGAINS_REG_ON_RESET; slv_reg3 <= 0; slv_reg4 <= `CLKDIV_GAINTIMING_REG_ON_RESET; slv_reg5 <= 0; slv_reg6 <= 0; slv_reg7 <= 0; slv_reg8 <= 0; slv_reg9 <= 0; slv_reg10 <= 0; end else case ( slv_reg_write_sel ) 11'b10000000000 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b01000000000 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00100000000 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00010000000 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00001000000 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00000100000 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00000010000 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00000001000 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00000000100 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00000000010 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; 11'b00000000001 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; default : begin slv_reg0 <= slv_reg0; slv_reg1 <= slv_reg1; slv_reg2 <= slv_reg2; slv_reg3 <= slv_reg3; slv_reg4 <= slv_reg4; slv_reg5 <= slv_reg5; slv_reg6 <= slv_reg6; slv_reg7 <= slv_reg7; slv_reg8 <= slv_reg8; slv_reg9 <= slv_reg9; slv_reg10 <= slv_reg10; end endcase end // SLAVE_REG_WRITE_PROC // Slave model register read mux // All registers can be read always @* begin case ( slv_reg_read_sel ) 64'b1000000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg0; 64'b0100000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg1; 64'b0010000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg2; 64'b0001000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg3; 64'b0000100000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg4; 64'b0000010000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg5; 64'b0000001000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg6; 64'b0000000100000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg7; 64'b0000000010000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg8; 64'b0000000001000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg9; 64'b0000000000100000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg10; 64'b0000000000010000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= status_reg; 64'b0000000000001000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[0]}; 64'b0000000000000100000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[1]}; 64'b0000000000000010000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[2]}; 64'b0000000000000001000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[3]}; 64'b0000000000000000100000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[4]}; 64'b0000000000000000010000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[5]}; 64'b0000000000000000001000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[6]}; 64'b0000000000000000000100000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[7]}; 64'b0000000000000000000010000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[8]}; 64'b0000000000000000000001000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[9]}; 64'b0000000000000000000000100000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[10]}; 64'b0000000000000000000000010000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[11]}; 64'b0000000000000000000000001000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[12]}; 64'b0000000000000000000000000100000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[0]}; 64'b0000000000000000000000000010000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[1]}; 64'b0000000000000000000000000001000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[2]}; 64'b0000000000000000000000000000100000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[3]}; 64'b0000000000000000000000000000010000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[4]}; 64'b0000000000000000000000000000001000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[5]}; 64'b0000000000000000000000000000000100000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[6]}; 64'b0000000000000000000000000000000010000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[7]}; 64'b0000000000000000000000000000000001000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[8]}; 64'b0000000000000000000000000000000000100000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[9]}; 64'b0000000000000000000000000000000000010000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[10]}; 64'b0000000000000000000000000000000000001000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[11]}; 64'b0000000000000000000000000000000000000100000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[12]}; 64'b0000000000000000000000000000000000000010000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[0]}; 64'b0000000000000000000000000000000000000001000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[1]}; 64'b0000000000000000000000000000000000000000100000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[2]}; 64'b0000000000000000000000000000000000000000010000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[3]}; 64'b0000000000000000000000000000000000000000001000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[4]}; 64'b0000000000000000000000000000000000000000000100000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[5]}; 64'b0000000000000000000000000000000000000000000010000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[6]}; 64'b0000000000000000000000000000000000000000000001000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[7]}; 64'b0000000000000000000000000000000000000000000000100000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[8]}; 64'b0000000000000000000000000000000000000000000000010000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[9]}; 64'b0000000000000000000000000000000000000000000000001000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[10]}; 64'b0000000000000000000000000000000000000000000000000100000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[11]}; 64'b0000000000000000000000000000000000000000000000000010000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[12]}; 64'b0000000000000000000000000000000000000000000000000001000000000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[0]}; 64'b0000000000000000000000000000000000000000000000000000100000000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[1]}; 64'b0000000000000000000000000000000000000000000000000000010000000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[2]}; 64'b0000000000000000000000000000000000000000000000000000001000000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[3]}; 64'b0000000000000000000000000000000000000000000000000000000100000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[4]}; 64'b0000000000000000000000000000000000000000000000000000000010000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[5]}; 64'b0000000000000000000000000000000000000000000000000000000001000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[6]}; 64'b0000000000000000000000000000000000000000000000000000000000100000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[7]}; 64'b0000000000000000000000000000000000000000000000000000000000010000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[8]}; 64'b0000000000000000000000000000000000000000000000000000000000001000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[9]}; 64'b0000000000000000000000000000000000000000000000000000000000000100 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[10]}; 64'b0000000000000000000000000000000000000000000000000000000000000010 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[11]}; 64'b0000000000000000000000000000000000000000000000000000000000000001 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[12]}; default : slv_ip2bus_data <= 0; endcase end // SLAVE_REG_READ_PROC /* Address map: HDL is coded [MSB:LSB] = [31:0], per Xilinx's convention for AXI peripherals regX[31] maps to 0x80000000 in C driver regX[ 0] maps to 0x00000001 in C driver 0: RW: MAX2829 control signals and control source (sw vs. hw) Mask for RFA: 0x000000FF Mask for RFB: 0x0000FF00 Mask for RFC: 0x00FF0000 Mask for RFD: 0xFF000000 [31:28] = RFD Control: {TxEn, RxEn, RxHP, SHDN} 0xF0000000 [27:24] = RFD Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x0F000000 [23:20] = RFC Control: {TxEn, RxEn, RxHP, SHDN} 0x00F00000 [19:16] = RFC Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x000F0000 [15:12] = RFB Control: {TxEn, RxEn, RxHP, SHDN} 0x0000F000 [11: 8] = RFB Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x00000F00 [ 7: 4] = RFA Control: {TxEn, RxEn, RxHP, SHDN} 0x000000F0 [ 3: 0] = RFA Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x0000000F 1: RW: Tx Timing Shared by all RF interfaces [31:24] = Delay before Tx VGA ramp start 0xFF000000 [23:16] = Delay before PA enable 0x00FF0000 [15: 8] = Delay before MAX2829 TxEn assertion 0x0000FF00 [ 7: 0] = Delay before usr_startPHY assertion 0x000000FF 2: RW: Tx Gains [ 31] = RF D Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x80000000 [ 30] = Reserved [29:24] = RF D Tx Gain 0x3F000000 [ 23] = RF C Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00800000 [ 22] = Reserved [21:16] = RF C Tx Gain 0x003F0000 [ 15] = RF B Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00008000 [ 14] = Reserved [13: 8] = RF B Tx Gain 0x00003F00 [ 7] = RF A Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00000080 [ 6] = Reserved [ 5: 0] = RF A Tx Gain 0x0000003F 3: RW: Rx gains [ 31] = RFD Rx gain ctrl source (0=register values, 1=usr_ ports) 0x80000000 [30:29] = RFD Rx RF Gain 0x60000000 [28:24] = RFD Rx BB Gain 0x1F000000 [ 23] = RFC Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00800000 [22:21] = RFC Rx RF Gain 0x00600000 [20:16] = RFC Rx BB Gain 0x001F0000 [ 15] = RFB Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00008000 [14:13] = RFB Rx RF Gain 0x00006000 [12: 8] = RFB Rx BB Gain 0x00001F00 [ 7] = RFA Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00000080 [ 6: 5] = RFA Rx RF Gain 0x00000060 [ 4: 0] = RFA Rx BB Gain 0x0000001F 4: RW: Clock dividers & Tx gain ramp config [31:16] = Reserved 0xFFFF0000 [15:12] = Tx VGA ramp time step 0x0000F000 [11: 8] = Tx VGA ramp gain step 0x00000F00 [ 7] = Reserved 0x00000080 [ 6: 4] = SPI clock divider 0x00000070 [ 3: 2] = Reserved 0x0000000C [ 1: 0] = TxTiming clock divider 0x00000003 5: WO: SPI write register Special register: * Write from software triggers SPI transaction * IPIF WrACK delayed until SPI is done (i.e. software doesn't have to poll; Xil_Out32 blocks until SPI is done) * Reads of this register return last SPI word transferred by software (might be stale, if usr_ SPI ports are also used) [31:28] SPI chip select mask RF[D:A] 0x80000000=RFD, 0x40000000=RFC, 0x20000000=RFB, 0x10000000=RFA [27:20] Reserved 0x0FF00000 [19:16] Register address to write 0x000F0000 [15:14] Reserved 0x0000C000 [13: 0] Register value to write 0x00003FFF 6 to 10: Reserved (RW 32-bit registers implemented; no connection to external hardware) 11: RO: Status bits Same per-RF masks as reg[0], same control signal masks as reg[0] [31:28] = RFD control status {TxEn, RxEn, RxHP, SHDN} [ 27] = RFD MAX2829 PLL locked (1=locked) [ 26] = RFD SPI transfer in progress [25:24] = {RFD PA_2 ON, RFD PA_5 ON} [23:20] = RFC control status {TxEn, RxEn, RxHP, SHDN} [ 19] = RFC MAX2829 PLL locked (1=locked) [ 18] = RFC SPI transfer in progress [17:16] = {RFC PA_2 ON, RFC PA_5 ON} [15:12] = RFB control status {TxEn, RxEn, RxHP, SHDN} [ 11] = RFB MAX2829 PLL locked (1=locked) [ 10] = RFB SPI transfer in progress [ 9: 8] = {RFB PA_2 ON, RFB PA_5 ON} [ 7: 4] = RFA control status {TxEn, RxEn, RxHP, SHDN} [ 3] = RFA MAX2829 PLL locked (1=locked) [ 2] = RFA SPI transfer in progress [ 1: 0] = {RFA PA_2 ON, RFA PA_5 ON} 12 to 63: RO: Read-only registers which mirror state of MAX2829 internal registers (since MAX2829 SPI is write-only) * Registers are initialized (on FPGA config and MAX2829 reset) to MAX2829 defaults, to match MAX2829 reset state * Register values are updated automatically by SPI writes (via reg4 or via usr_ SPI port use) * Every register is: [31:14] Reserved; returns 0 on read [13: 0] Register value (14 bits) 12...24: RO: Local copies of MAX2829 registers for RFA 12: RFA MAX2829 reg0 ... 24: RFA MAX2829 regC 25...37: RO: Local copies of MAX2829 registers for RFB 25: RFB MAX2829 reg0 ... 37: RFB MAX2829 regC 38...50: RO: Local copies of MAX2829 registers for RFC 38: RFC MAX2829 reg0 ... 50: RFC MAX2829 regC 51...63: RO: Local copies of MAX2829 registers for RFD 51: RFD MAX2829 reg0 ... 63: RFD MAX2829 regC */ //Only regs 0 to 10 can be written; 12 to 63 are RO assign slv_reg_write_sel = Bus2IP_WrCE[63:53]; //WrCE[63:0] maps to slv_reg[0:63] //All regs can be read; ACK all reads immediately assign slv_reg_read_sel = Bus2IP_RdCE[63:0]; assign slv_read_ack = |Bus2IP_RdCE[63:0]; //Write ack for reg5 (WrCE[58]) is delayed by SPI transfer // All other regs ACK writes immediately assign slv_write_ack_normalRegisters = |{Bus2IP_WrCE[63:59], Bus2IP_WrCE[57:53]}; assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; assign IP2Bus_RdAck = slv_read_ack; assign IP2Bus_Error = 0; //spi_tx_reg_write (Bus2IP_WrCE[58]) de-asserts as soon as transaction is ACK'd // so this mux switches back to the generic ACK as soon as the SPI xfer is done //Thus, the duration of assertion for spi_xfer_done doesn't really matter //A bit fast-n-loose, but works ok assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack_normalRegisters; //Register 0: MAX2829 control assign {RFD_TxEn_sw, RFD_RxEn_sw, RFD_RxHP_sw, RFD_SHDN_sw} = slv_reg0[31:28]; assign {RFD_TxEn_ctrlSrc, RFD_RxEn_ctrlSrc, RFD_RxHP_ctrlSrc, RFD_SHDN_ctrlSrc} = slv_reg0[27:24]; assign {RFC_TxEn_sw, RFC_RxEn_sw, RFC_RxHP_sw, RFC_SHDN_sw} = slv_reg0[23:20]; assign {RFC_TxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFC_RxHP_ctrlSrc, RFC_SHDN_ctrlSrc} = slv_reg0[19:16]; assign {RFB_TxEn_sw, RFB_RxEn_sw, RFB_RxHP_sw, RFB_SHDN_sw} = slv_reg0[15:12]; assign {RFB_TxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFB_RxHP_ctrlSrc, RFB_SHDN_ctrlSrc} = slv_reg0[11:8]; assign {RFA_TxEn_sw, RFA_RxEn_sw, RFA_RxHP_sw, RFA_SHDN_sw} = slv_reg0[7:4]; assign {RFA_TxEn_ctrlSrc, RFA_RxEn_ctrlSrc, RFA_RxHP_ctrlSrc, RFA_SHDN_ctrlSrc} = slv_reg0[3:0]; //Register 1: Tx timing assign TxTiming_dly_TxGainRamp = slv_reg1[31:24]; assign TxTiming_dly_PowerAmpEn = slv_reg1[23:16]; assign TxTiming_dly_TxEn = slv_reg1[15: 8]; assign TxTiming_dly_startPHY = slv_reg1[ 7: 0]; //Register 2: Tx gains assign RFD_TxGain_sw = slv_reg2[29:24]; assign RFC_TxGain_sw = slv_reg2[21:16]; assign RFB_TxGain_sw = slv_reg2[13: 8]; assign RFA_TxGain_sw = slv_reg2[ 5: 0]; assign RFD_TxGain_ctrlSrc = slv_reg2[31]; assign RFC_TxGain_ctrlSrc = slv_reg2[23]; assign RFB_TxGain_ctrlSrc = slv_reg2[15]; assign RFA_TxGain_ctrlSrc = slv_reg2[ 7]; //Register 3: Rx gains assign RFD_RxGainBB_sw = slv_reg3[28:24]; assign RFC_RxGainBB_sw = slv_reg3[20:16]; assign RFB_RxGainBB_sw = slv_reg3[12: 8]; assign RFA_RxGainBB_sw = slv_reg3[ 4: 0]; assign RFD_RxGainRF_sw = slv_reg3[30:29]; assign RFC_RxGainRF_sw = slv_reg3[22:21]; assign RFB_RxGainRF_sw = slv_reg3[14:13]; assign RFA_RxGainRF_sw = slv_reg3[ 6: 5]; assign RFD_RxGain_ctrlSrc = slv_reg3[31]; assign RFC_RxGain_ctrlSrc = slv_reg3[23]; assign RFB_RxGain_ctrlSrc = slv_reg3[15]; assign RFA_RxGain_ctrlSrc = slv_reg3[ 7]; //Register 4: Clock dividers & Tx gain ramp config assign TxGainRamp_timeStep = slv_reg4[15:12]; assign TxGainRamp_gainStep = slv_reg4[11: 8]; assign spi_clk_div_sel = slv_reg4[ 6: 4]; assign txTiming_clk_div_sel = slv_reg4[ 1: 0]; //Register 5: SPI write assign spi_rfsel_mask_sw = slv_reg5[31:28]; assign spi_tx_regaddr = slv_reg5[19:16]; assign spi_tx_regdata = slv_reg5[13: 0]; //Use the IPIF write-enable for the SPI Tx register as the SPI go // The bus will be paused until the SPI transfer is finished assign spi_tx_reg_write = Bus2IP_WrCE[58]; //Register 11: Read-only status bits assign status_reg[31:28] = {RFD_TxEn, RFD_RxEn, RFD_RxHP, RFD_SHDN}; assign status_reg[27:24] = {RFD_LD, ~RFD_SPI_CSn, RFD_PAEn_24, RFD_PAEn_5}; assign status_reg[23:20] = {RFC_TxEn, RFC_RxEn, RFC_RxHP, RFC_SHDN}; assign status_reg[19:16] = {RFC_LD, ~RFC_SPI_CSn, RFC_PAEn_24, RFC_PAEn_5}; assign status_reg[15:12] = {RFB_TxEn, RFB_RxEn, RFB_RxHP, RFB_SHDN}; assign status_reg[11: 8] = {RFB_LD, ~RFB_SPI_CSn, RFB_PAEn_24, RFB_PAEn_5}; assign status_reg[ 7: 4] = {RFA_TxEn, RFA_RxEn, RFA_RxHP, RFA_SHDN}; assign status_reg[ 3: 0] = {RFA_LD, ~RFA_SPI_CSn, RFA_PAEn_24, RFA_PAEn_5}; //Mux the various control signals between software and hardware control assign RFA_txStart = RFA_TxEn_ctrlSrc ? usr_RFA_TxEn : RFA_TxEn_sw; assign RFB_txStart = RFB_TxEn_ctrlSrc ? usr_RFB_TxEn : RFB_TxEn_sw; assign RFC_txStart = RFC_TxEn_ctrlSrc ? usr_RFC_TxEn : RFC_TxEn_sw; assign RFD_txStart = RFD_TxEn_ctrlSrc ? usr_RFD_TxEn : RFD_TxEn_sw; assign RFA_RxEn_w = RFA_RxEn_ctrlSrc ? usr_RFA_RxEn : RFA_RxEn_sw; assign RFB_RxEn_w = RFB_RxEn_ctrlSrc ? usr_RFB_RxEn : RFB_RxEn_sw; assign RFC_RxEn_w = RFC_RxEn_ctrlSrc ? usr_RFC_RxEn : RFC_RxEn_sw; assign RFD_RxEn_w = RFD_RxEn_ctrlSrc ? usr_RFD_RxEn : RFD_RxEn_sw; assign RFA_RxHP_w = RFA_RxHP_ctrlSrc ? usr_RFA_RxHP : RFA_RxHP_sw; assign RFB_RxHP_w = RFB_RxHP_ctrlSrc ? usr_RFB_RxHP : RFB_RxHP_sw; assign RFC_RxHP_w = RFC_RxHP_ctrlSrc ? usr_RFC_RxHP : RFC_RxHP_sw; assign RFD_RxHP_w = RFD_RxHP_ctrlSrc ? usr_RFD_RxHP : RFD_RxHP_sw; assign RFA_SHDN_w = RFA_SHDN_ctrlSrc ? usr_RFA_SHDN : RFA_SHDN_sw; assign RFB_SHDN_w = RFB_SHDN_ctrlSrc ? usr_RFB_SHDN : RFB_SHDN_sw; assign RFC_SHDN_w = RFC_SHDN_ctrlSrc ? usr_RFC_SHDN : RFC_SHDN_sw; assign RFD_SHDN_w = RFD_SHDN_ctrlSrc ? usr_RFD_SHDN : RFD_SHDN_sw; assign RFA_TxGain_target = RFA_TxGain_ctrlSrc ? usr_RFA_TxGain : RFA_TxGain_sw; assign RFB_TxGain_target = RFB_TxGain_ctrlSrc ? usr_RFB_TxGain : RFB_TxGain_sw; assign RFC_TxGain_target = RFC_TxGain_ctrlSrc ? usr_RFC_TxGain : RFC_TxGain_sw; assign RFD_TxGain_target = RFD_TxGain_ctrlSrc ? usr_RFD_TxGain : RFD_TxGain_sw; assign RFA_RxGainBB = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainBB : RFA_RxGainBB_sw; assign RFB_RxGainBB = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainBB : RFB_RxGainBB_sw; assign RFC_RxGainBB = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainBB : RFC_RxGainBB_sw; assign RFD_RxGainBB = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainBB : RFD_RxGainBB_sw; assign RFA_RxGainRF = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainRF : RFA_RxGainRF_sw; assign RFB_RxGainRF = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainRF : RFB_RxGainRF_sw; assign RFC_RxGainRF = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainRF : RFC_RxGainRF_sw; assign RFD_RxGainRF = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainRF : RFD_RxGainRF_sw; //Output OR'd PHYStart signal (most PHYs use this, so any TxEnable will start the PHY) // Individual PHYStarts are provided in case user has multiple PHYs connected to different RF paths assign usr_any_PHYStart = usr_RFA_PHYStart || usr_RFB_PHYStart || usr_RFC_PHYStart || usr_RFD_PHYStart; //SKY13370 needs 100-250nsec to settle, so make the switch as soon as we know Tx process is starting //2-bit control signal in hardware, but only two valid states: // [V1 V2] = [1 0] => Rx path connected to SMA, Tx path terminated to 50 ohms (PA must be off!) // [V1 V2] = [0 1] => Tx path connected to SMA, Rx path terminated to 50 ohms //RFx_AntSw[0] = SKY13370.V1, RFx_AntSw[1] = SKY13370.V2 assign RFA_AntSw_w[1:0] = {~RFA_txStart, RFA_txStart}; assign RFB_AntSw_w[1:0] = {~RFB_txStart, RFB_txStart}; assign RFC_AntSw_w[1:0] = {~RFC_txStart, RFC_txStart}; assign RFD_AntSw_w[1:0] = {~RFD_txStart, RFD_txStart}; //PAs are enabled by single wire per band // One path's 2.4 and 5GHz PAs should never be enabled simultaneously //2.4GHz PA is on when: // TxTiming state machine asserts PAEn AND // MAX2829.reg5[0] == 0 (indicating MAX2829 is tuned to 2.4GHz band) //5GHz PA is on when: // TxTiming state machine asserts PAEn AND // MAX2829.reg5[0] == 1 (indicating MAX2829 is tuned to 5GHz band) //RFx_MAX2829_mirrorRegs are indexed [MSB:LSB]=[13:0] to match other busses in this core, // so the LSB (bit [0] in MAX2829 datasheet) is RFA_MAX2829_mirrorRegs[x][0] here assign RFA_PAEn_24_w = (RFA_PAEn & ~(RFA_mirrorReg_data[5][0])); assign RFB_PAEn_24_w = (RFB_PAEn & ~(RFB_mirrorReg_data[5][0])); assign RFC_PAEn_24_w = (RFC_PAEn & ~(RFC_mirrorReg_data[5][0])); assign RFD_PAEn_24_w = (RFD_PAEn & ~(RFD_mirrorReg_data[5][0])); assign RFA_PAEn_5_w = (RFA_PAEn & (RFA_mirrorReg_data[5][0])); assign RFB_PAEn_5_w = (RFB_PAEn & (RFB_mirrorReg_data[5][0])); assign RFC_PAEn_5_w = (RFC_PAEn & (RFC_mirrorReg_data[5][0])); assign RFD_PAEn_5_w = (RFD_PAEn & (RFD_mirrorReg_data[5][0])); //MAX2829 gain control bus // radio_controller.RFx_B[6:0] maps to MAX2829.B[7:1] // radio_controller.RFx_B[6] is MSB, radio_controller.RFx_B[0] is LSB // MAX2829.B7 is MSB, MAX2829.B1 is LSB //When SPI gain control is disabled: // In Tx mode: // MAX2829.B[7] is don't care // MAX2829.B[6:1] = Tx RF VGA (6'd63 is max gain, 6'd0 is min gain (approx max-30dB)) // In Rx mode: // MAX2829.B[7:6] = Rx RF LNA (2'd3 is max gain (30dB), 2'd1 is min gain (0dB), 2'd0 is invalid) // MAX2829.B[5:1] = Rx BB VGA (5'd31 is max gain (approx 62dB), 5'd0 is min gain (approx 0dB) //assign RFA_B = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB}; //assign RFB_B = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB}; //assign RFC_B = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB}; //assign RFD_B = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB}; assign {RFA_B_w[0], RFA_B_w[1], RFA_B_w[2], RFA_B_w[3], RFA_B_w[4], RFA_B_w[5], RFA_B_w[6]} = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB}; assign {RFB_B_w[0], RFB_B_w[1], RFB_B_w[2], RFB_B_w[3], RFB_B_w[4], RFB_B_w[5], RFB_B_w[6]} = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB}; assign {RFC_B_w[0], RFC_B_w[1], RFC_B_w[2], RFC_B_w[3], RFC_B_w[4], RFC_B_w[5], RFC_B_w[6]} = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB}; assign {RFD_B_w[0], RFD_B_w[1], RFD_B_w[2], RFD_B_w[3], RFD_B_w[4], RFD_B_w[5], RFD_B_w[6]} = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB}; //Simple state machines for fixed timing of Tx events (MAX2829 TxEn, PA enable and PHY start) // One per RF path, to handle case of user designs which do Tx/Rx asychronously across paths // All use same timing values, as these are really tuned to the hardware, not the Tx signal radio_controller_TxTiming RFA_txTiming ( .clk(Bus2IP_Clk), .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low .clk_div(txTiming_clk_div_sel), .sw_start(RFA_txStart), .dly_GainRamp(TxTiming_dly_TxGainRamp), .dly_TxEn(TxTiming_dly_TxEn), .dly_PHYStart(TxTiming_dly_startPHY), .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), .gainRamp_TxGainTarget(RFA_TxGain_target), .gainRamp_GainStep(TxGainRamp_gainStep), .gainRamp_TimeStep(TxGainRamp_timeStep), .gainRamp_TxGainOut(RFA_TxGain_ramped), .TxEn(RFA_TxEn_w), .PAEn(RFA_PAEn), .PHYStart(usr_RFA_PHYStart) ); radio_controller_TxTiming RFB_txTiming ( .clk(Bus2IP_Clk), .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low .clk_div(txTiming_clk_div_sel), .sw_start(RFB_txStart), .dly_GainRamp(TxTiming_dly_TxGainRamp), .dly_TxEn(TxTiming_dly_TxEn), .dly_PHYStart(TxTiming_dly_startPHY), .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), .gainRamp_TxGainTarget(RFB_TxGain_target), .gainRamp_GainStep(TxGainRamp_gainStep), .gainRamp_TimeStep(TxGainRamp_timeStep), .gainRamp_TxGainOut(RFB_TxGain_ramped), .TxEn(RFB_TxEn_w), .PAEn(RFB_PAEn), .PHYStart(usr_RFB_PHYStart) ); radio_controller_TxTiming RFC_txTiming ( .clk(Bus2IP_Clk), .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low .clk_div(txTiming_clk_div_sel), .sw_start(RFC_txStart), .dly_GainRamp(TxTiming_dly_TxGainRamp), .dly_TxEn(TxTiming_dly_TxEn), .dly_PHYStart(TxTiming_dly_startPHY), .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), .gainRamp_TxGainTarget(RFC_TxGain_target), .gainRamp_GainStep(TxGainRamp_gainStep), .gainRamp_TimeStep(TxGainRamp_timeStep), .gainRamp_TxGainOut(RFC_TxGain_ramped), .TxEn(RFC_TxEn_w), .PAEn(RFC_PAEn), .PHYStart(usr_RFC_PHYStart) ); radio_controller_TxTiming RFD_txTiming ( .clk(Bus2IP_Clk), .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low .clk_div(txTiming_clk_div_sel), .sw_start(RFD_txStart), .dly_GainRamp(TxTiming_dly_TxGainRamp), .dly_TxEn(TxTiming_dly_TxEn), .dly_PHYStart(TxTiming_dly_startPHY), .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), .gainRamp_TxGainTarget(RFD_TxGain_target), .gainRamp_GainStep(TxGainRamp_gainStep), .gainRamp_TimeStep(TxGainRamp_timeStep), .gainRamp_TxGainOut(RFD_TxGain_ramped), .TxEn(RFD_TxEn_w), .PAEn(RFD_PAEn), .PHYStart(usr_RFD_PHYStart) ); //Signals to detect when MAX2829 hardware reset occurs (TxEn=1, RxEn=1, SHDN=0) // Reset can be triggered by hardware or software, depending on the user config assign RFA_MAX2829_Reset = (RFA_TxEn & RFA_RxEn & ~RFA_SHDN); assign RFB_MAX2829_Reset = (RFB_TxEn & RFB_RxEn & ~RFB_SHDN); assign RFC_MAX2829_Reset = (RFC_TxEn & RFC_RxEn & ~RFC_SHDN); assign RFD_MAX2829_Reset = (RFD_TxEn & RFD_RxEn & ~RFD_SHDN); //Use a counter to generate a blinking error signal to indicate a radio in standby that hasn't yet locked reg [23:0] error_blink_counter = 24'b0; always @(posedge Bus2IP_Clk) begin error_blink_counter <= error_blink_counter + 1; usr_RFA_statLED_Tx <= RFA_SHDN_w ? (RFA_TxEn_w | ((~RFA_LD) & error_blink_counter[23])) : 1'b0; usr_RFA_statLED_Rx <= RFA_SHDN_w ? (RFA_RxEn_w | ((~RFA_LD) & error_blink_counter[23])) : 1'b0;; usr_RFB_statLED_Tx <= RFB_SHDN_w ? (RFB_TxEn_w | ((~RFB_LD) & error_blink_counter[23])) : 1'b0; usr_RFB_statLED_Rx <= RFB_SHDN_w ? (RFB_RxEn_w | ((~RFB_LD) & error_blink_counter[23])) : 1'b0;; usr_RFC_statLED_Tx <= RFC_SHDN_w ? (RFC_TxEn_w | ((~RFC_LD) & error_blink_counter[23])) : 1'b0; usr_RFC_statLED_Rx <= RFC_SHDN_w ? (RFC_RxEn_w | ((~RFC_LD) & error_blink_counter[23])) : 1'b0;; usr_RFD_statLED_Tx <= RFD_SHDN_w ? (RFD_TxEn_w | ((~RFD_LD) & error_blink_counter[23])) : 1'b0; usr_RFD_statLED_Rx <= RFD_SHDN_w ? (RFD_RxEn_w | ((~RFD_LD) & error_blink_counter[23])) : 1'b0;; end //Mask per-RF path to enable SPI transactions // Driven by register for software control, usr_ port for hardware control assign spi_rfsel_mask = usr_SPI_ctrlSrc ? usr_SPI_rfsel : spi_rfsel_mask_sw; wire RFA_reg_write_en; wire RFB_reg_write_en; wire RFC_reg_write_en; wire RFD_reg_write_en; assign RFA_reg_write_en = ((spi_rfsel_mask & 4'b0001) != 0); assign RFB_reg_write_en = ((spi_rfsel_mask & 4'b0010) != 0); assign RFC_reg_write_en = ((spi_rfsel_mask & 4'b0100) != 0); assign RFD_reg_write_en = ((spi_rfsel_mask & 4'b1000) != 0); radio_mirror_regs RFA_mirror_regs ( .clk(Bus2IP_Clk), .reset(RFA_MAX2829_Reset_d), .spi_reg_wr_data(spi_tx_regdata), .spi_reg_wr_addr(spi_tx_regaddr), .spi_reg_wr_en(RFA_reg_write_en), .mirror_reg0(RFA_mirrorReg_data[0]), .mirror_reg1(RFA_mirrorReg_data[1]), .mirror_reg2(RFA_mirrorReg_data[2]), .mirror_reg3(RFA_mirrorReg_data[3]), .mirror_reg4(RFA_mirrorReg_data[4]), .mirror_reg5(RFA_mirrorReg_data[5]), .mirror_reg6(RFA_mirrorReg_data[6]), .mirror_reg7(RFA_mirrorReg_data[7]), .mirror_reg8(RFA_mirrorReg_data[8]), .mirror_reg9(RFA_mirrorReg_data[9]), .mirror_regA(RFA_mirrorReg_data[10]), .mirror_regB(RFA_mirrorReg_data[11]), .mirror_regC(RFA_mirrorReg_data[12]) ); radio_mirror_regs RFB_mirror_regs ( .clk(Bus2IP_Clk), .reset(RFB_MAX2829_Reset_d), .spi_reg_wr_data(spi_tx_regdata), .spi_reg_wr_addr(spi_tx_regaddr), .spi_reg_wr_en(RFB_reg_write_en), .mirror_reg0(RFB_mirrorReg_data[0]), .mirror_reg1(RFB_mirrorReg_data[1]), .mirror_reg2(RFB_mirrorReg_data[2]), .mirror_reg3(RFB_mirrorReg_data[3]), .mirror_reg4(RFB_mirrorReg_data[4]), .mirror_reg5(RFB_mirrorReg_data[5]), .mirror_reg6(RFB_mirrorReg_data[6]), .mirror_reg7(RFB_mirrorReg_data[7]), .mirror_reg8(RFB_mirrorReg_data[8]), .mirror_reg9(RFB_mirrorReg_data[9]), .mirror_regA(RFB_mirrorReg_data[10]), .mirror_regB(RFB_mirrorReg_data[11]), .mirror_regC(RFB_mirrorReg_data[12]) ); radio_mirror_regs RFC_mirror_regs ( .clk(Bus2IP_Clk), .reset(RFC_MAX2829_Reset_d), .spi_reg_wr_data(spi_tx_regdata), .spi_reg_wr_addr(spi_tx_regaddr), .spi_reg_wr_en(RFC_reg_write_en), .mirror_reg0(RFC_mirrorReg_data[0]), .mirror_reg1(RFC_mirrorReg_data[1]), .mirror_reg2(RFC_mirrorReg_data[2]), .mirror_reg3(RFC_mirrorReg_data[3]), .mirror_reg4(RFC_mirrorReg_data[4]), .mirror_reg5(RFC_mirrorReg_data[5]), .mirror_reg6(RFC_mirrorReg_data[6]), .mirror_reg7(RFC_mirrorReg_data[7]), .mirror_reg8(RFC_mirrorReg_data[8]), .mirror_reg9(RFC_mirrorReg_data[9]), .mirror_regA(RFC_mirrorReg_data[10]), .mirror_regB(RFC_mirrorReg_data[11]), .mirror_regC(RFC_mirrorReg_data[12]) ); radio_mirror_regs RFD_mirror_regs ( .clk(Bus2IP_Clk), .reset(RFD_MAX2829_Reset_d), .spi_reg_wr_data(spi_tx_regdata), .spi_reg_wr_addr(spi_tx_regaddr), .spi_reg_wr_en(RFD_reg_write_en), .mirror_reg0(RFD_mirrorReg_data[0]), .mirror_reg1(RFD_mirrorReg_data[1]), .mirror_reg2(RFD_mirrorReg_data[2]), .mirror_reg3(RFD_mirrorReg_data[3]), .mirror_reg4(RFD_mirrorReg_data[4]), .mirror_reg5(RFD_mirrorReg_data[5]), .mirror_reg6(RFD_mirrorReg_data[6]), .mirror_reg7(RFD_mirrorReg_data[7]), .mirror_reg8(RFD_mirrorReg_data[8]), .mirror_reg9(RFD_mirrorReg_data[9]), .mirror_regA(RFD_mirrorReg_data[10]), .mirror_regB(RFD_mirrorReg_data[11]), .mirror_regC(RFD_mirrorReg_data[12]) ); //MAX2829 CS is active-low; warp_spi_io.spi_cs is active high assign RFA_SPI_CSn = ~(spi_rfsel_mask[0] & spi_cs); assign RFB_SPI_CSn = ~(spi_rfsel_mask[1] & spi_cs); assign RFC_SPI_CSn = ~(spi_rfsel_mask[2] & spi_cs); assign RFD_SPI_CSn = ~(spi_rfsel_mask[3] & spi_cs); assign RFA_SPI_MOSI = spi_mosi; assign RFB_SPI_MOSI = spi_mosi; assign RFC_SPI_MOSI = spi_mosi; assign RFD_SPI_MOSI = spi_mosi; //Mask each SCLK output by the corresponding CS // No point toggling SCLKs that will be ignored assign RFA_SPI_SCLK = (spi_sclk & spi_rfsel_mask[0]); assign RFB_SPI_SCLK = (spi_sclk & spi_rfsel_mask[1]); assign RFC_SPI_SCLK = (spi_sclk & spi_rfsel_mask[2]); assign RFD_SPI_SCLK = (spi_sclk & spi_rfsel_mask[3]); //MAX2829 SPI uses 18-bit transfers, formatted as {regData[13:0] regAddr[3:0]}, data and addr both transfer MSB first wire [17:0] spi_tx_data_word; assign spi_tx_data_word[17:0] = usr_SPI_ctrlSrc ? {usr_SPI_regdata, usr_SPI_regaddr} : {spi_tx_regdata, spi_tx_regaddr}; assign spi_go = usr_SPI_ctrlSrc ? usr_SPI_go : spi_tx_reg_write; assign usr_SPI_active = spi_cs; warp_spi_io #(.SPI_XFER_LEN(18)) spi_io ( .sys_clk(Bus2IP_Clk), .reset(~Bus2IP_Resetn),//reset input is active high, IPIF resetn is active low .go(spi_go), .done(spi_xfer_done), .clkDiv(spi_clk_div_sel), .currBitNum(), .txData({14'b0, spi_tx_data_word}), .rxData1(), .rxData2(), .rxData3(), .rxData4(), .spi_cs(spi_cs), .spi_sclk(spi_sclk), .spi_mosi(spi_mosi), .spi_miso1(1'b0), .spi_miso2(1'b0), .spi_miso3(1'b0), .spi_miso4(1'b0) ); endmodule