1 | //---------------------------------------------------------------------------- |
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2 | // user_logic.vhd - module |
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3 | //---------------------------------------------------------------------------- |
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4 | // |
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5 | // *************************************************************************** |
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6 | // ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. ** |
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7 | // ** ** |
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8 | // ** Xilinx, Inc. ** |
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9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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21 | // ** FOR A PARTICULAR PURPOSE. ** |
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22 | // ** ** |
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23 | // *************************************************************************** |
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24 | // |
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25 | //---------------------------------------------------------------------------- |
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26 | // Filename: user_logic.vhd |
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27 | // Version: 1.20.a |
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28 | // Description: User logic module. |
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29 | // Date: Wed Feb 06 13:11:10 2008 (by Create and Import Peripheral Wizard) |
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30 | // Verilog Standard: Verilog-2001 |
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31 | //---------------------------------------------------------------------------- |
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32 | // Naming Conventions: |
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33 | // active low signals: "*_n" |
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34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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35 | // reset signals: "rst", "rst_n" |
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36 | // generics: "C_*" |
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37 | // user defined types: "*_TYPE" |
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38 | // state machine next state: "*_ns" |
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39 | // state machine current state: "*_cs" |
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40 | // combinatorial signals: "*_com" |
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41 | // pipelined or register delay signals: "*_d#" |
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42 | // counter signals: "*cnt*" |
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43 | // clock enable signals: "*_ce" |
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44 | // internal version of output port: "*_i" |
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45 | // device pins: "*_pin" |
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46 | // ports: "- Names begin with Uppercase" |
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47 | // processes: "*_PROCESS" |
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48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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49 | //---------------------------------------------------------------------------- |
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50 | |
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51 | module user_logic |
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52 | ( |
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53 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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54 | controller_logic_clk1, |
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55 | spi_clk1, |
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56 | data_out1, |
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57 | controller_logic_clk2, |
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58 | spi_clk2, |
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59 | data_out2, |
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60 | controller_logic_clk3, |
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61 | spi_clk3, |
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62 | data_out3, |
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63 | controller_logic_clk4, |
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64 | spi_clk4, |
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65 | data_out4, |
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66 | Radio1_cs, |
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67 | Radio2_cs, |
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68 | Radio3_cs, |
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69 | Radio4_cs, |
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70 | Dac1_cs, |
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71 | Dac2_cs, |
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72 | Dac3_cs, |
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73 | Dac4_cs, |
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74 | Radio1_SHDN, |
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75 | Radio1_TxEn, |
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76 | Radio1_RxEn, |
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77 | Radio1_RxHP, |
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78 | Radio1_LD, |
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79 | Radio1_24PA, |
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80 | Radio1_5PA, |
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81 | Radio1_ANTSW, |
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82 | Radio1_LED, |
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83 | Radio1_ADC_RX_DCS, |
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84 | Radio1_ADC_RX_DFS, |
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85 | Radio1_ADC_RX_OTRA, |
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86 | Radio1_ADC_RX_OTRB, |
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87 | Radio1_ADC_RX_PWDNA, |
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88 | Radio1_ADC_RX_PWDNB, |
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89 | Radio1_DIPSW, |
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90 | Radio1_RSSI_ADC_CLAMP, |
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91 | Radio1_RSSI_ADC_HIZ, |
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92 | Radio1_RSSI_ADC_OTR, |
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93 | Radio1_RSSI_ADC_SLEEP, |
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94 | Radio1_RSSI_ADC_D, |
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95 | Radio1_TX_DAC_PLL_LOCK, |
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96 | Radio1_TX_DAC_RESET, |
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97 | Radio1_SHDN_external, |
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98 | Radio1_TxEn_external, |
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99 | Radio1_RxEn_external, |
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100 | Radio1_RxHP_external, |
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101 | Radio1_TxGain, |
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102 | Radio1_TxStart, |
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103 | Radio2_SHDN, |
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104 | Radio2_TxEn, |
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105 | Radio2_RxEn, |
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106 | Radio2_RxHP, |
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107 | Radio2_LD, |
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108 | Radio2_24PA, |
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109 | Radio2_5PA, |
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110 | Radio2_ANTSW, |
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111 | Radio2_LED, |
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112 | Radio2_ADC_RX_DCS, |
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113 | Radio2_ADC_RX_DFS, |
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114 | Radio2_ADC_RX_OTRA, |
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115 | Radio2_ADC_RX_OTRB, |
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116 | Radio2_ADC_RX_PWDNA, |
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117 | Radio2_ADC_RX_PWDNB, |
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118 | Radio2_DIPSW, |
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119 | Radio2_RSSI_ADC_CLAMP, |
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120 | Radio2_RSSI_ADC_HIZ, |
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121 | Radio2_RSSI_ADC_OTR, |
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122 | Radio2_RSSI_ADC_SLEEP, |
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123 | Radio2_RSSI_ADC_D, |
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124 | Radio2_TX_DAC_PLL_LOCK, |
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125 | Radio2_TX_DAC_RESET, |
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126 | Radio2_SHDN_external, |
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127 | Radio2_TxEn_external, |
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128 | Radio2_RxEn_external, |
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129 | Radio2_RxHP_external, |
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130 | Radio2_TxGain, |
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131 | Radio2_TxStart, |
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132 | Radio3_SHDN, |
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133 | Radio3_TxEn, |
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134 | Radio3_RxEn, |
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135 | Radio3_RxHP, |
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136 | Radio3_LD, |
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137 | Radio3_24PA, |
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138 | Radio3_5PA, |
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139 | Radio3_ANTSW, |
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140 | Radio3_LED, |
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141 | Radio3_ADC_RX_DCS, |
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142 | Radio3_ADC_RX_DFS, |
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143 | Radio3_ADC_RX_OTRA, |
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144 | Radio3_ADC_RX_OTRB, |
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145 | Radio3_ADC_RX_PWDNA, |
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146 | Radio3_ADC_RX_PWDNB, |
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147 | Radio3_DIPSW, |
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148 | Radio3_RSSI_ADC_CLAMP, |
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149 | Radio3_RSSI_ADC_HIZ, |
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150 | Radio3_RSSI_ADC_OTR, |
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151 | Radio3_RSSI_ADC_SLEEP, |
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152 | Radio3_RSSI_ADC_D, |
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153 | Radio3_TX_DAC_PLL_LOCK, |
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154 | Radio3_TX_DAC_RESET, |
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155 | Radio3_SHDN_external, |
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156 | Radio3_TxEn_external, |
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157 | Radio3_RxEn_external, |
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158 | Radio3_RxHP_external, |
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159 | Radio3_TxGain, |
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160 | Radio3_TxStart, |
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161 | Radio4_SHDN, |
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162 | Radio4_TxEn, |
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163 | Radio4_RxEn, |
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164 | Radio4_RxHP, |
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165 | Radio4_LD, |
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166 | Radio4_24PA, |
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167 | Radio4_5PA, |
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168 | Radio4_ANTSW, |
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169 | Radio4_LED, |
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170 | Radio4_ADC_RX_DCS, |
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171 | Radio4_ADC_RX_DFS, |
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172 | Radio4_ADC_RX_OTRA, |
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173 | Radio4_ADC_RX_OTRB, |
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174 | Radio4_ADC_RX_PWDNA, |
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175 | Radio4_ADC_RX_PWDNB, |
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176 | Radio4_DIPSW, |
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177 | Radio4_RSSI_ADC_CLAMP, |
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178 | Radio4_RSSI_ADC_HIZ, |
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179 | Radio4_RSSI_ADC_OTR, |
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180 | Radio4_RSSI_ADC_SLEEP, |
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181 | Radio4_RSSI_ADC_D, |
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182 | Radio4_TX_DAC_PLL_LOCK, |
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183 | Radio4_TX_DAC_RESET, |
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184 | Radio4_SHDN_external, |
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185 | Radio4_TxEn_external, |
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186 | Radio4_RxEn_external, |
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187 | Radio4_RxHP_external, |
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188 | Radio4_TxGain, |
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189 | Radio4_TxStart, |
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190 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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191 | |
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192 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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193 | // -- Bus protocol ports, do not add to or delete |
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194 | Bus2IP_Clk, // Bus to IP clock |
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195 | Bus2IP_Reset, // Bus to IP reset |
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196 | Bus2IP_Data, // Bus to IP data bus |
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197 | Bus2IP_BE, // Bus to IP byte enables |
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198 | Bus2IP_RdCE, // Bus to IP read chip enable |
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199 | Bus2IP_WrCE, // Bus to IP write chip enable |
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200 | IP2Bus_Data, // IP to Bus data bus |
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201 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
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202 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
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203 | IP2Bus_Error // IP to Bus error response |
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204 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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205 | ); // user_logic |
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206 | |
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207 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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208 | // --USER parameters added here |
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209 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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210 | |
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211 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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212 | // -- Bus protocol parameters, do not add to or delete |
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213 | parameter C_SLV_DWIDTH = 32; |
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214 | parameter C_NUM_REG = 17; |
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215 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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216 | |
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217 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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218 | output controller_logic_clk1; |
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219 | output spi_clk1; |
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220 | output data_out1; |
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221 | output controller_logic_clk2; |
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222 | output spi_clk2; |
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223 | output data_out2; |
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224 | output controller_logic_clk3; |
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225 | output spi_clk3; |
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226 | output data_out3; |
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227 | output controller_logic_clk4; |
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228 | output spi_clk4; |
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229 | output data_out4; |
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230 | output Radio1_cs; |
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231 | output Radio2_cs; |
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232 | output Radio3_cs; |
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233 | output Radio4_cs; |
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234 | output Dac1_cs; |
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235 | output Dac2_cs; |
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236 | output Dac3_cs; |
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237 | output Dac4_cs; |
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238 | |
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239 | output Radio1_SHDN; |
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240 | output Radio1_TxEn; |
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241 | output Radio1_RxEn; |
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242 | output Radio1_RxHP; |
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243 | input Radio1_LD; |
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244 | output Radio1_24PA; |
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245 | output Radio1_5PA; |
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246 | output [0 : 1] Radio1_ANTSW; |
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247 | output [0 : 2] Radio1_LED; |
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248 | output Radio1_ADC_RX_DCS; |
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249 | output Radio1_ADC_RX_DFS; |
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250 | input Radio1_ADC_RX_OTRA; |
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251 | input Radio1_ADC_RX_OTRB; |
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252 | output Radio1_ADC_RX_PWDNA; |
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253 | output Radio1_ADC_RX_PWDNB; |
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254 | input [0 : 3] Radio1_DIPSW; |
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255 | output Radio1_RSSI_ADC_CLAMP; |
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256 | output Radio1_RSSI_ADC_HIZ; |
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257 | input Radio1_RSSI_ADC_OTR; |
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258 | output Radio1_RSSI_ADC_SLEEP; |
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259 | input [0 : 9] Radio1_RSSI_ADC_D; |
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260 | input Radio1_TX_DAC_PLL_LOCK; |
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261 | output Radio1_TX_DAC_RESET; |
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262 | input Radio1_SHDN_external; |
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263 | input Radio1_TxEn_external; |
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264 | input Radio1_RxEn_external; |
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265 | input Radio1_RxHP_external; |
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266 | output [0 : 5] Radio1_TxGain; |
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267 | output Radio1_TxStart; |
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268 | |
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269 | output Radio2_SHDN; |
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270 | output Radio2_TxEn; |
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271 | output Radio2_RxEn; |
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272 | output Radio2_RxHP; |
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273 | input Radio2_LD; |
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274 | output Radio2_24PA; |
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275 | output Radio2_5PA; |
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276 | output [0 : 1] Radio2_ANTSW; |
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277 | output [0 : 2] Radio2_LED; |
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278 | output Radio2_ADC_RX_DCS; |
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279 | output Radio2_ADC_RX_DFS; |
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280 | input Radio2_ADC_RX_OTRA; |
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281 | input Radio2_ADC_RX_OTRB; |
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282 | output Radio2_ADC_RX_PWDNA; |
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283 | output Radio2_ADC_RX_PWDNB; |
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284 | input [0 : 3] Radio2_DIPSW; |
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285 | output Radio2_RSSI_ADC_CLAMP; |
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286 | output Radio2_RSSI_ADC_HIZ; |
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287 | input Radio2_RSSI_ADC_OTR; |
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288 | output Radio2_RSSI_ADC_SLEEP; |
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289 | input [0 : 9] Radio2_RSSI_ADC_D; |
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290 | input Radio2_TX_DAC_PLL_LOCK; |
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291 | output Radio2_TX_DAC_RESET; |
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292 | input Radio2_SHDN_external; |
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293 | input Radio2_TxEn_external; |
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294 | input Radio2_RxEn_external; |
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295 | input Radio2_RxHP_external; |
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296 | output [0 : 5] Radio2_TxGain; |
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297 | output Radio2_TxStart; |
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298 | |
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299 | output Radio3_SHDN; |
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300 | output Radio3_TxEn; |
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301 | output Radio3_RxEn; |
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302 | output Radio3_RxHP; |
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303 | input Radio3_LD; |
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304 | output Radio3_24PA; |
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305 | output Radio3_5PA; |
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306 | output [0 : 1] Radio3_ANTSW; |
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307 | output [0 : 2] Radio3_LED; |
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308 | output Radio3_ADC_RX_DCS; |
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309 | output Radio3_ADC_RX_DFS; |
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310 | input Radio3_ADC_RX_OTRA; |
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311 | input Radio3_ADC_RX_OTRB; |
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312 | output Radio3_ADC_RX_PWDNA; |
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313 | output Radio3_ADC_RX_PWDNB; |
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314 | input [0 : 3] Radio3_DIPSW; |
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315 | output Radio3_RSSI_ADC_CLAMP; |
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316 | output Radio3_RSSI_ADC_HIZ; |
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317 | input Radio3_RSSI_ADC_OTR; |
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318 | output Radio3_RSSI_ADC_SLEEP; |
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319 | input [0 : 9] Radio3_RSSI_ADC_D; |
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320 | input Radio3_TX_DAC_PLL_LOCK; |
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321 | output Radio3_TX_DAC_RESET; |
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322 | input Radio3_SHDN_external; |
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323 | input Radio3_TxEn_external; |
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324 | input Radio3_RxEn_external; |
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325 | input Radio3_RxHP_external; |
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326 | output [0 : 5] Radio3_TxGain; |
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327 | output Radio3_TxStart; |
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328 | |
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329 | output Radio4_SHDN; |
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330 | output Radio4_TxEn; |
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331 | output Radio4_RxEn; |
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332 | output Radio4_RxHP; |
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333 | input Radio4_LD; |
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334 | output Radio4_24PA; |
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335 | output Radio4_5PA; |
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336 | output [0 : 1] Radio4_ANTSW; |
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337 | output [0 : 2] Radio4_LED; |
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338 | output Radio4_ADC_RX_DCS; |
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339 | output Radio4_ADC_RX_DFS; |
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340 | input Radio4_ADC_RX_OTRA; |
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341 | input Radio4_ADC_RX_OTRB; |
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342 | output Radio4_ADC_RX_PWDNA; |
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343 | output Radio4_ADC_RX_PWDNB; |
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344 | input [0 : 3] Radio4_DIPSW; |
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345 | output Radio4_RSSI_ADC_CLAMP; |
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346 | output Radio4_RSSI_ADC_HIZ; |
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347 | input Radio4_RSSI_ADC_OTR; |
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348 | output Radio4_RSSI_ADC_SLEEP; |
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349 | input [0 : 9] Radio4_RSSI_ADC_D; |
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350 | input Radio4_TX_DAC_PLL_LOCK; |
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351 | output Radio4_TX_DAC_RESET; |
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352 | input Radio4_SHDN_external; |
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353 | input Radio4_TxEn_external; |
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354 | input Radio4_RxEn_external; |
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355 | input Radio4_RxHP_external; |
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356 | output [0 : 5] Radio4_TxGain; |
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357 | output Radio4_TxStart;// -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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358 | |
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359 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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360 | // -- Bus protocol ports, do not add to or delete |
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361 | input Bus2IP_Clk; |
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362 | input Bus2IP_Reset; |
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363 | input [0 : C_SLV_DWIDTH-1] Bus2IP_Data; |
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364 | input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE; |
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365 | input [0 : C_NUM_REG-1] Bus2IP_RdCE; |
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366 | input [0 : C_NUM_REG-1] Bus2IP_WrCE; |
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367 | output [0 : C_SLV_DWIDTH-1] IP2Bus_Data; |
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368 | output IP2Bus_RdAck; |
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369 | output IP2Bus_WrAck; |
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370 | output IP2Bus_Error; |
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371 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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372 | |
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373 | //---------------------------------------------------------------------------- |
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374 | // Implementation |
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375 | //---------------------------------------------------------------------------- |
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376 | |
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377 | // --USER nets declarations added here, as needed for user logic |
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378 | |
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379 | // Nets for user logic slave model s/w accessible register example |
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380 | reg [0 : C_SLV_DWIDTH-1] slv_reg0; |
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381 | reg [0 : C_SLV_DWIDTH-1] slv_reg1; |
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382 | reg [0 : C_SLV_DWIDTH-1] slv_reg2; |
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383 | reg [0 : C_SLV_DWIDTH-1] slv_reg3; |
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384 | reg [0 : C_SLV_DWIDTH-1] slv_reg4; |
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385 | reg [0 : C_SLV_DWIDTH-1] slv_reg5; |
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386 | reg [0 : C_SLV_DWIDTH-1] slv_reg6; |
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387 | reg [0 : C_SLV_DWIDTH-1] slv_reg7; |
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388 | reg [0 : C_SLV_DWIDTH-1] slv_reg8; |
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389 | reg [0 : C_SLV_DWIDTH-1] slv_reg9; |
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390 | reg [0 : C_SLV_DWIDTH-1] slv_reg10; |
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391 | reg [0 : C_SLV_DWIDTH-1] slv_reg11; |
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392 | reg [0 : C_SLV_DWIDTH-1] slv_reg12; |
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393 | reg [0 : C_SLV_DWIDTH-1] slv_reg13; |
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394 | reg [0 : C_SLV_DWIDTH-1] slv_reg14; |
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395 | reg [0 : C_SLV_DWIDTH-1] slv_reg15; |
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396 | reg [0 : C_SLV_DWIDTH-1] slv_reg16; |
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397 | wire [0 : 16] slv_reg_write_sel; |
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398 | wire [0 : 16] slv_reg_read_sel; |
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399 | reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data; |
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400 | wire slv_read_ack; |
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401 | wire slv_write_ack; |
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402 | integer byte_index, bit_index; |
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403 | |
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404 | // Nets for SPI interface connected to user_logic |
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405 | wire [7:0] ss_pad_o; |
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406 | wire mytip; |
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407 | wire [13:0] reg_ctrl; |
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408 | wire [7:0] reg_ss; |
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409 | wire [3:0] reg_divider; |
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410 | wire [17:0] reg_tx; |
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411 | |
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412 | // Intermediate signals for transmit gain state machine |
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413 | wire Radio1_PowerAmpEnable, Radio1_swTxEn, Radio1_sw24PAEn, Radio1_sw5PAEn; |
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414 | wire Radio2_PowerAmpEnable, Radio2_swTxEn, Radio2_sw24PAEn, Radio2_sw5PAEn; |
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415 | wire Radio3_PowerAmpEnable, Radio3_swTxEn, Radio3_sw24PAEn, Radio3_sw5PAEn; |
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416 | wire Radio4_PowerAmpEnable, Radio4_swTxEn, Radio4_sw24PAEn, Radio4_sw5PAEn; |
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417 | |
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418 | // Internal signals for calculating Tx gains |
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419 | wire [0:5] Radio1_TargetTxGain, Radio2_TargetTxGain, Radio3_TargetTxGain, Radio4_TargetTxGain; |
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420 | wire [0:3] Radio1_TxGainStep, Radio2_TxGainStep, Radio3_TxGainStep, Radio4_TxGainStep; |
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421 | wire [0:3] Radio1_TxGainTimeStep, Radio2_TxGainTimeStep, Radio3_TxGainTimeStep, Radio4_TxGainTimeStep; |
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422 | |
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423 | // Internal signals setting delays used to control Tx timing |
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424 | wire [0:7] Radio1_GainRampThresh, Radio1_PAThresh, Radio1_TxEnThresh; |
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425 | wire [0:7] Radio2_GainRampThresh, Radio2_PAThresh, Radio2_TxEnThresh; |
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426 | wire [0:7] Radio3_GainRampThresh, Radio3_PAThresh, Radio3_TxEnThresh; |
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427 | wire [0:7] Radio4_GainRampThresh, Radio4_PAThresh, Radio4_TxEnThresh; |
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428 | |
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429 | wire [0:11] Radio1_TxStartThresh, Radio2_TxStartThresh, Radio3_TxStartThresh, Radio4_TxStartThresh; |
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430 | |
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431 | // SPI Interface signals |
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432 | assign Radio1_cs = ss_pad_o[0]; |
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433 | assign Radio2_cs = ss_pad_o[1]; |
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434 | assign Radio3_cs = ss_pad_o[2]; |
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435 | assign Radio4_cs = ss_pad_o[3]; |
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436 | assign Dac1_cs = ss_pad_o[4]; |
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437 | assign Dac2_cs = ss_pad_o[5]; |
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438 | assign Dac3_cs = ss_pad_o[6]; |
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439 | assign Dac4_cs = ss_pad_o[7]; |
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440 | |
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441 | assign reg_ctrl = slv_reg5[18:31]; |
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442 | assign reg_divider = slv_reg6[28:31]; |
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443 | assign reg_ss = slv_reg7[24:31]; |
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444 | assign reg_tx = slv_reg8[14:31]; |
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445 | |
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446 | wire spi_clk; |
---|
447 | assign spi_clk1 = spi_clk; |
---|
448 | assign spi_clk2 = spi_clk; |
---|
449 | assign spi_clk3 = spi_clk; |
---|
450 | assign spi_clk4 = spi_clk; |
---|
451 | |
---|
452 | wire data_out; |
---|
453 | assign data_out1 = data_out; |
---|
454 | assign data_out2 = data_out; |
---|
455 | assign data_out3 = data_out; |
---|
456 | assign data_out4 = data_out; |
---|
457 | |
---|
458 | // Instantiate the SPI controller top-level |
---|
459 | spi_top spi_top( |
---|
460 | .opb_clk_i(Bus2IP_Clk), |
---|
461 | .opb_rst_i(Bus2IP_Reset), |
---|
462 | .reg_ctrl(reg_ctrl), |
---|
463 | .reg_ss(reg_ss), |
---|
464 | .reg_divider(reg_divider), |
---|
465 | .reg_tx(reg_tx), |
---|
466 | .ctrlwrite(Bus2IP_WrCE[5]), |
---|
467 | .busval(Bus2IP_Data[23]), |
---|
468 | .go(mytip), |
---|
469 | .ss_pad_o(ss_pad_o), |
---|
470 | .sclk_pad_o(spi_clk), |
---|
471 | .mosi_pad_o(data_out) |
---|
472 | ); |
---|
473 | |
---|
474 | |
---|
475 | // Copy the bus clock to the logic_clk output |
---|
476 | // The bridges use this to latch the signals used here that become top-level I/O |
---|
477 | assign controller_logic_clk1 = Bus2IP_Clk; |
---|
478 | assign controller_logic_clk2 = Bus2IP_Clk; |
---|
479 | assign controller_logic_clk3 = Bus2IP_Clk; |
---|
480 | assign controller_logic_clk4 = Bus2IP_Clk; |
---|
481 | |
---|
482 | //// Signals and Tx state machine for Radio 1 |
---|
483 | |
---|
484 | assign Radio1_SHDN = (slv_reg0[27])?~Radio1_SHDN_external:~slv_reg0[31]; |
---|
485 | assign Radio1_swTxEn = (slv_reg0[19])?Radio1_TxEn_external:slv_reg0[23]; |
---|
486 | assign Radio1_RxEn = (slv_reg0[11])?Radio1_RxEn_external:slv_reg0[15]; |
---|
487 | assign Radio1_RxHP = (slv_reg0[3])?Radio1_RxHP_external:slv_reg0[7]; |
---|
488 | |
---|
489 | assign Radio1_sw24PAEn = slv_reg1[31]; |
---|
490 | assign Radio1_sw5PAEn = slv_reg1[27]; |
---|
491 | |
---|
492 | assign Radio1_24PA = ~(Radio1_sw24PAEn & Radio1_PowerAmpEnable); //active low output |
---|
493 | assign Radio1_5PA = ~(Radio1_sw5PAEn & Radio1_PowerAmpEnable); //active low output |
---|
494 | |
---|
495 | assign Radio1_ANTSW[0] = (slv_reg0[19])? Radio1_TxEn_external : slv_reg1[15]; //slv_reg1[15]; |
---|
496 | assign Radio1_ANTSW[1] = (slv_reg0[11])? Radio1_RxEn_external : ~slv_reg1[15]; //~slv_reg1[15]; |
---|
497 | assign Radio1_ADC_RX_DCS = slv_reg1[7]; |
---|
498 | assign Radio1_LED[0] = Radio1_RxEn; |
---|
499 | assign Radio1_LED[1] = Radio1_TxEn; |
---|
500 | assign Radio1_LED[2] = ~Radio1_LD; |
---|
501 | assign Radio1_ADC_RX_PWDNA = slv_reg2[23]; |
---|
502 | assign Radio1_ADC_RX_PWDNB = slv_reg2[19]; |
---|
503 | assign Radio1_RSSI_ADC_SLEEP = slv_reg2[15]; |
---|
504 | assign Radio1_TX_DAC_RESET = slv_reg1[11]; |
---|
505 | |
---|
506 | assign Radio1_ADC_RX_DFS = 1'b1; //slv_reg1[3]; |
---|
507 | assign Radio1_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[3]; |
---|
508 | assign Radio1_RSSI_ADC_HIZ = 1'b0; //slv_reg2[7]; |
---|
509 | |
---|
510 | //Read the user register for programmed target Tx gain |
---|
511 | assign Radio1_TargetTxGain = slv_reg9[0:5]; |
---|
512 | |
---|
513 | //Read the user regsiter for programmed Tx gain ramp increment |
---|
514 | assign Radio1_TxGainStep = slv_reg9[6:9]; |
---|
515 | |
---|
516 | //Read the user register for programmed delay between gain steps |
---|
517 | assign Radio1_TxGainTimeStep = slv_reg9[10:13]; |
---|
518 | |
---|
519 | //slv_reg9[28:31] available for future use |
---|
520 | |
---|
521 | //Read the user registers for the the delays before each Tx event |
---|
522 | assign Radio1_GainRampThresh = slv_reg13[0:7]; |
---|
523 | assign Radio1_PAThresh = slv_reg13[8:15]; |
---|
524 | assign Radio1_TxEnThresh = slv_reg13[16:23]; |
---|
525 | assign Radio1_TxStartThresh = slv_reg9[16:27]; |
---|
526 | |
---|
527 | radio_controller_TxTiming Radio1_TxTiming ( |
---|
528 | .clk(Bus2IP_Clk), |
---|
529 | .reset(Bus2IP_Reset), |
---|
530 | |
---|
531 | .Tx_swEnable(Radio1_swTxEn), |
---|
532 | |
---|
533 | .TxGain_target(Radio1_TargetTxGain), |
---|
534 | .TxGain_rampGainStep(Radio1_TxGainStep), |
---|
535 | .TxGain_rampTimeStep(Radio1_TxGainTimeStep), |
---|
536 | |
---|
537 | .dly_hwTxEn(Radio1_TxEnThresh), |
---|
538 | .dly_TxStart(Radio1_TxStartThresh), |
---|
539 | .dly_PowerAmpEn(Radio1_PAThresh), |
---|
540 | .dly_RampGain(Radio1_GainRampThresh), |
---|
541 | |
---|
542 | .hw_TxEn(Radio1_TxEn), |
---|
543 | .hw_TxGain(Radio1_TxGain), |
---|
544 | .hw_PAEn(Radio1_PowerAmpEnable), |
---|
545 | .hw_TxStart(Radio1_TxStart) |
---|
546 | ); |
---|
547 | |
---|
548 | |
---|
549 | //// Signals and Tx state machine for Radio 2 |
---|
550 | |
---|
551 | assign Radio2_SHDN = (slv_reg0[26])?~Radio2_SHDN_external:~slv_reg0[30]; |
---|
552 | assign Radio2_swTxEn = (slv_reg0[18])?Radio2_TxEn_external:slv_reg0[22]; |
---|
553 | assign Radio2_RxEn = (slv_reg0[10])?Radio2_RxEn_external:slv_reg0[14]; |
---|
554 | assign Radio2_RxHP = (slv_reg0[2])?Radio2_RxHP_external:slv_reg0[6]; |
---|
555 | |
---|
556 | assign Radio2_sw24PAEn = slv_reg1[30]; |
---|
557 | assign Radio2_sw5PAEn = slv_reg1[26]; |
---|
558 | |
---|
559 | assign Radio2_24PA = ~(Radio2_sw24PAEn & Radio2_PowerAmpEnable); //active low output |
---|
560 | assign Radio2_5PA = ~(Radio2_sw5PAEn & Radio2_PowerAmpEnable); //active low output |
---|
561 | |
---|
562 | assign Radio2_ANTSW[0] = (slv_reg0[18])? Radio2_TxEn_external : slv_reg1[14]; //slv_reg1[14]; |
---|
563 | assign Radio2_ANTSW[1] = (slv_reg0[10])? Radio2_RxEn_external : ~slv_reg1[14]; //~slv_reg1[14]; |
---|
564 | assign Radio2_ADC_RX_DCS = slv_reg1[6]; |
---|
565 | assign Radio2_LED[0] = Radio2_RxEn; |
---|
566 | assign Radio2_LED[1] = Radio2_TxEn; |
---|
567 | assign Radio2_LED[2] = ~Radio2_LD; |
---|
568 | assign Radio2_ADC_RX_PWDNA = slv_reg2[22]; |
---|
569 | assign Radio2_ADC_RX_PWDNB = slv_reg2[18]; |
---|
570 | assign Radio2_RSSI_ADC_SLEEP = slv_reg2[14]; |
---|
571 | assign Radio2_TX_DAC_RESET = slv_reg1[10]; |
---|
572 | |
---|
573 | assign Radio2_ADC_RX_DFS = 1'b1; //slv_reg1[2]; |
---|
574 | assign Radio2_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[2]; |
---|
575 | assign Radio2_RSSI_ADC_HIZ = 1'b0; //slv_reg2[6]; |
---|
576 | |
---|
577 | //Read the user register for programmed target Tx gain |
---|
578 | assign Radio2_TargetTxGain = slv_reg10[0:5]; |
---|
579 | |
---|
580 | //Read the user regsiter for programmed Tx gain ramp increment |
---|
581 | assign Radio2_TxGainStep = slv_reg10[6:9]; |
---|
582 | |
---|
583 | //Read the user register for programmed delay between gain steps |
---|
584 | assign Radio2_TxGainTimeStep = slv_reg10[10:13]; |
---|
585 | |
---|
586 | //slv_reg10[28:31] available for future use |
---|
587 | |
---|
588 | //Read the user registers for the the delays before each Tx event |
---|
589 | assign Radio2_GainRampThresh = slv_reg14[0:7]; |
---|
590 | assign Radio2_PAThresh = slv_reg14[8:15]; |
---|
591 | assign Radio2_TxEnThresh = slv_reg14[16:23]; |
---|
592 | assign Radio2_TxStartThresh = slv_reg10[16:27]; |
---|
593 | |
---|
594 | radio_controller_TxTiming Radio2_TxTiming ( |
---|
595 | .clk(Bus2IP_Clk), |
---|
596 | .reset(Bus2IP_Reset), |
---|
597 | |
---|
598 | .Tx_swEnable(Radio2_swTxEn), |
---|
599 | |
---|
600 | .TxGain_target(Radio2_TargetTxGain), |
---|
601 | .TxGain_rampGainStep(Radio2_TxGainStep), |
---|
602 | .TxGain_rampTimeStep(Radio2_TxGainTimeStep), |
---|
603 | |
---|
604 | .dly_hwTxEn(Radio2_TxEnThresh), |
---|
605 | .dly_TxStart(Radio2_TxStartThresh), |
---|
606 | .dly_PowerAmpEn(Radio2_PAThresh), |
---|
607 | .dly_RampGain(Radio2_GainRampThresh), |
---|
608 | |
---|
609 | .hw_TxEn(Radio2_TxEn), |
---|
610 | .hw_TxGain(Radio2_TxGain), |
---|
611 | .hw_PAEn(Radio2_PowerAmpEnable), |
---|
612 | .hw_TxStart(Radio2_TxStart) |
---|
613 | ); |
---|
614 | |
---|
615 | |
---|
616 | //// Signals and Tx state machine for Radio 3 |
---|
617 | |
---|
618 | assign Radio3_SHDN = (slv_reg0[25])?~Radio3_SHDN_external:~slv_reg0[29]; |
---|
619 | assign Radio3_swTxEn = (slv_reg0[17])?Radio3_TxEn_external:slv_reg0[21]; |
---|
620 | assign Radio3_RxEn = (slv_reg0[9])?Radio3_RxEn_external:slv_reg0[13]; |
---|
621 | assign Radio3_RxHP = (slv_reg0[1])?Radio3_RxHP_external:slv_reg0[5]; |
---|
622 | |
---|
623 | assign Radio3_sw24PAEn = slv_reg1[29]; |
---|
624 | assign Radio3_sw5PAEn = slv_reg1[25]; |
---|
625 | |
---|
626 | assign Radio3_24PA = ~(Radio3_sw24PAEn & Radio3_PowerAmpEnable); //active low output |
---|
627 | assign Radio3_5PA = ~(Radio3_sw5PAEn & Radio3_PowerAmpEnable); //active low output |
---|
628 | |
---|
629 | assign Radio3_ANTSW[0] = (slv_reg0[17])? Radio3_TxEn_external : slv_reg1[13]; //slv_reg1[13]; |
---|
630 | assign Radio3_ANTSW[1] = (slv_reg0[9])? Radio3_RxEn_external : ~slv_reg1[13]; //~slv_reg1[13]; |
---|
631 | assign Radio3_ADC_RX_DCS = slv_reg1[5]; |
---|
632 | assign Radio3_LED[0] = Radio3_RxEn; |
---|
633 | assign Radio3_LED[1] = Radio3_TxEn; |
---|
634 | assign Radio3_LED[2] = ~Radio3_LD; |
---|
635 | assign Radio3_ADC_RX_PWDNA = slv_reg2[21]; |
---|
636 | assign Radio3_ADC_RX_PWDNB = slv_reg2[17]; |
---|
637 | assign Radio3_RSSI_ADC_SLEEP = slv_reg2[13]; |
---|
638 | assign Radio3_TX_DAC_RESET = slv_reg1[9]; |
---|
639 | |
---|
640 | assign Radio3_ADC_RX_DFS = 1'b1; //slv_reg1[1]; |
---|
641 | assign Radio3_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[1]; |
---|
642 | assign Radio3_RSSI_ADC_HIZ = 1'b0; //slv_reg2[5]; |
---|
643 | |
---|
644 | //Read the user register for programmed target Tx gain |
---|
645 | assign Radio3_TargetTxGain = slv_reg11[0:5]; |
---|
646 | |
---|
647 | //Read the user regsiter for programmed Tx gain ramp increment |
---|
648 | assign Radio3_TxGainStep = slv_reg11[6:9]; |
---|
649 | |
---|
650 | //Read the user register for programmed delay between gain steps |
---|
651 | assign Radio3_TxGainTimeStep = slv_reg11[10:13]; |
---|
652 | |
---|
653 | //slv_reg11[28:31] available for future use |
---|
654 | |
---|
655 | //Read the user registers for the the delays before each Tx event |
---|
656 | assign Radio3_GainRampThresh = slv_reg15[0:7]; |
---|
657 | assign Radio3_PAThresh = slv_reg15[8:15]; |
---|
658 | assign Radio3_TxEnThresh = slv_reg15[16:23]; |
---|
659 | assign Radio3_TxStartThresh = slv_reg11[16:27]; |
---|
660 | |
---|
661 | radio_controller_TxTiming Radio3_TxTiming ( |
---|
662 | .clk(Bus2IP_Clk), |
---|
663 | .reset(Bus2IP_Reset), |
---|
664 | |
---|
665 | .Tx_swEnable(Radio3_swTxEn), |
---|
666 | |
---|
667 | .TxGain_target(Radio3_TargetTxGain), |
---|
668 | .TxGain_rampGainStep(Radio3_TxGainStep), |
---|
669 | .TxGain_rampTimeStep(Radio3_TxGainTimeStep), |
---|
670 | |
---|
671 | .dly_hwTxEn(Radio3_TxEnThresh), |
---|
672 | .dly_TxStart(Radio3_TxStartThresh), |
---|
673 | .dly_PowerAmpEn(Radio3_PAThresh), |
---|
674 | .dly_RampGain(Radio3_GainRampThresh), |
---|
675 | |
---|
676 | .hw_TxEn(Radio3_TxEn), |
---|
677 | .hw_TxGain(Radio3_TxGain), |
---|
678 | .hw_PAEn(Radio3_PowerAmpEnable), |
---|
679 | .hw_TxStart(Radio3_TxStart) |
---|
680 | ); |
---|
681 | |
---|
682 | |
---|
683 | //// Signals and Tx state machine for Radio 4 |
---|
684 | |
---|
685 | assign Radio4_SHDN = (slv_reg0[24])?~Radio4_SHDN_external:~slv_reg0[28]; |
---|
686 | assign Radio4_swTxEn = (slv_reg0[16])?Radio4_TxEn_external:slv_reg0[20]; |
---|
687 | assign Radio4_RxEn = (slv_reg0[8])?Radio4_RxEn_external:slv_reg0[12]; |
---|
688 | assign Radio4_RxHP = (slv_reg0[0])?Radio4_RxHP_external:slv_reg0[4]; |
---|
689 | |
---|
690 | assign Radio4_sw24PAEn = slv_reg1[28]; |
---|
691 | assign Radio4_sw5PAEn = slv_reg1[24]; |
---|
692 | |
---|
693 | assign Radio4_24PA = ~(Radio4_sw24PAEn & Radio4_PowerAmpEnable); //active low output |
---|
694 | assign Radio4_5PA = ~(Radio4_sw5PAEn & Radio4_PowerAmpEnable); //active low output |
---|
695 | |
---|
696 | assign Radio4_ANTSW[0] = (slv_reg0[16])? Radio4_TxEn_external : slv_reg1[12]; //slv_reg1[12]; |
---|
697 | assign Radio4_ANTSW[1] = (slv_reg0[8])? Radio4_RxEn_external : ~slv_reg1[12]; //~slv_reg1[12]; |
---|
698 | assign Radio4_ADC_RX_DCS = slv_reg1[4]; |
---|
699 | assign Radio4_LED[0] = Radio4_RxEn; |
---|
700 | assign Radio4_LED[1] = Radio4_TxEn; |
---|
701 | assign Radio4_LED[2] = ~Radio4_LD; |
---|
702 | assign Radio4_ADC_RX_PWDNA = slv_reg2[20]; |
---|
703 | assign Radio4_ADC_RX_PWDNB = slv_reg2[16]; |
---|
704 | assign Radio4_RSSI_ADC_SLEEP = slv_reg2[12]; |
---|
705 | assign Radio4_TX_DAC_RESET = slv_reg1[8]; |
---|
706 | |
---|
707 | assign Radio4_ADC_RX_DFS = 1'b1; //slv_reg1[0]; |
---|
708 | assign Radio4_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[0]; |
---|
709 | assign Radio4_RSSI_ADC_HIZ = 1'b0; //slv_reg2[4]; |
---|
710 | |
---|
711 | //Read the user register for programmed target Tx gain |
---|
712 | assign Radio4_TargetTxGain = slv_reg12[0:5]; |
---|
713 | |
---|
714 | //Read the user regsiter for programmed Tx gain ramp increment |
---|
715 | assign Radio4_TxGainStep = slv_reg12[6:9]; |
---|
716 | |
---|
717 | //Read the user register for programmed delay between gain steps |
---|
718 | assign Radio4_TxGainTimeStep = slv_reg12[10:13]; |
---|
719 | |
---|
720 | //slv_reg12[28:31] available for future use |
---|
721 | |
---|
722 | //Read the user registers for the the delays before each Tx event |
---|
723 | assign Radio4_GainRampThresh = slv_reg16[0:7]; |
---|
724 | assign Radio4_PAThresh = slv_reg16[8:15]; |
---|
725 | assign Radio4_TxEnThresh = slv_reg16[16:23]; |
---|
726 | assign Radio4_TxStartThresh = slv_reg12[16:27]; |
---|
727 | |
---|
728 | radio_controller_TxTiming Radio4_TxTiming ( |
---|
729 | .clk(Bus2IP_Clk), |
---|
730 | .reset(Bus2IP_Reset), |
---|
731 | |
---|
732 | .Tx_swEnable(Radio4_swTxEn), |
---|
733 | |
---|
734 | .TxGain_target(Radio4_TargetTxGain), |
---|
735 | .TxGain_rampGainStep(Radio4_TxGainStep), |
---|
736 | .TxGain_rampTimeStep(Radio4_TxGainTimeStep), |
---|
737 | |
---|
738 | .dly_hwTxEn(Radio4_TxEnThresh), |
---|
739 | .dly_TxStart(Radio4_TxStartThresh), |
---|
740 | .dly_PowerAmpEn(Radio4_PAThresh), |
---|
741 | .dly_RampGain(Radio4_GainRampThresh), |
---|
742 | |
---|
743 | .hw_TxEn(Radio4_TxEn), |
---|
744 | .hw_TxGain(Radio4_TxGain), |
---|
745 | .hw_PAEn(Radio4_PowerAmpEnable), |
---|
746 | .hw_TxStart(Radio4_TxStart) |
---|
747 | ); |
---|
748 | |
---|
749 | assign |
---|
750 | slv_reg_write_sel = Bus2IP_WrCE[0:16], |
---|
751 | slv_reg_read_sel = Bus2IP_RdCE[0:16], |
---|
752 | slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15] || Bus2IP_WrCE[16], |
---|
753 | slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15] || Bus2IP_RdCE[16]; |
---|
754 | |
---|
755 | // implement slave model register(s) |
---|
756 | always @( posedge Bus2IP_Clk ) |
---|
757 | begin: SLAVE_REG_WRITE_PROC |
---|
758 | |
---|
759 | if ( Bus2IP_Reset == 1 ) |
---|
760 | begin |
---|
761 | slv_reg0 <= 0; |
---|
762 | slv_reg1 <= 0; |
---|
763 | slv_reg2 <= 0; |
---|
764 | slv_reg3 <= 0; |
---|
765 | slv_reg4 <= 0; |
---|
766 | slv_reg5 <= 0; |
---|
767 | slv_reg6 <= 0; |
---|
768 | slv_reg7 <= 0; |
---|
769 | slv_reg8 <= 0; |
---|
770 | slv_reg9 <= {14'h3fff, 22'h0}; //Gain increment, targets & delays all default to max values |
---|
771 | slv_reg10 <= {14'h3fff, 22'h0}; |
---|
772 | slv_reg11 <= {14'h3fff, 22'h0}; |
---|
773 | slv_reg12 <= {14'h3fff, 22'h0}; |
---|
774 | slv_reg13 <= 0; |
---|
775 | slv_reg14 <= 0; |
---|
776 | slv_reg15 <= 0; |
---|
777 | slv_reg16 <= 0; |
---|
778 | end |
---|
779 | else |
---|
780 | case ( slv_reg_write_sel ) |
---|
781 | 17'b10000000000000000 : |
---|
782 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
783 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
784 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
785 | slv_reg0[bit_index] <= Bus2IP_Data[bit_index]; |
---|
786 | 17'b01000000000000000 : |
---|
787 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
788 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
789 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
790 | slv_reg1[bit_index] <= Bus2IP_Data[bit_index]; |
---|
791 | 17'b00100000000000000 : |
---|
792 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
793 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
794 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
795 | slv_reg2[bit_index] <= Bus2IP_Data[bit_index]; |
---|
796 | 17'b00010000000000000 : |
---|
797 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
798 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
799 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
800 | slv_reg3[bit_index] <= Bus2IP_Data[bit_index]; |
---|
801 | 17'b00001000000000000 : |
---|
802 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
803 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
804 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
805 | slv_reg4[bit_index] <= Bus2IP_Data[bit_index]; |
---|
806 | 17'b00000100000000000 : |
---|
807 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
808 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
809 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
810 | slv_reg5[bit_index] <= Bus2IP_Data[bit_index]; |
---|
811 | 17'b00000010000000000 : |
---|
812 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
813 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
814 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
815 | slv_reg6[bit_index] <= Bus2IP_Data[bit_index]; |
---|
816 | 17'b00000001000000000 : |
---|
817 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
818 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
819 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
820 | slv_reg7[bit_index] <= Bus2IP_Data[bit_index]; |
---|
821 | 17'b00000000100000000 : |
---|
822 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
823 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
824 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
825 | slv_reg8[bit_index] <= Bus2IP_Data[bit_index]; |
---|
826 | 17'b00000000010000000 : |
---|
827 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
828 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
829 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
830 | slv_reg9[bit_index] <= Bus2IP_Data[bit_index]; |
---|
831 | 17'b00000000001000000 : |
---|
832 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
833 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
834 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
835 | slv_reg10[bit_index] <= Bus2IP_Data[bit_index]; |
---|
836 | 17'b00000000000100000 : |
---|
837 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
838 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
839 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
840 | slv_reg11[bit_index] <= Bus2IP_Data[bit_index]; |
---|
841 | 17'b00000000000010000 : |
---|
842 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
843 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
844 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
845 | slv_reg12[bit_index] <= Bus2IP_Data[bit_index]; |
---|
846 | 17'b00000000000001000 : |
---|
847 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
848 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
849 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
850 | slv_reg13[bit_index] <= Bus2IP_Data[bit_index]; |
---|
851 | 17'b00000000000000100 : |
---|
852 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
853 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
854 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
855 | slv_reg14[bit_index] <= Bus2IP_Data[bit_index]; |
---|
856 | 17'b00000000000000010 : |
---|
857 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
858 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
859 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
860 | slv_reg15[bit_index] <= Bus2IP_Data[bit_index]; |
---|
861 | 17'b00000000000000001 : |
---|
862 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
863 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
864 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
865 | slv_reg16[bit_index] <= Bus2IP_Data[bit_index]; |
---|
866 | default : ; |
---|
867 | endcase |
---|
868 | |
---|
869 | end // SLAVE_REG_WRITE_PROC |
---|
870 | |
---|
871 | // implement slave model register read mux |
---|
872 | always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 or slv_reg16 ) |
---|
873 | begin: SLAVE_REG_READ_PROC |
---|
874 | |
---|
875 | case ( slv_reg_read_sel ) |
---|
876 | 17'b10000000000000000 : slv_ip2bus_data <= slv_reg0; |
---|
877 | 17'b01000000000000000 : slv_ip2bus_data <= {Radio4_ADC_RX_DFS, |
---|
878 | Radio3_ADC_RX_DFS, |
---|
879 | Radio2_ADC_RX_DFS, |
---|
880 | Radio1_ADC_RX_DFS, |
---|
881 | slv_reg1[4:19], |
---|
882 | Radio4_LD, |
---|
883 | Radio3_LD, |
---|
884 | Radio2_LD, |
---|
885 | Radio1_LD, |
---|
886 | slv_reg1[24:31]}; |
---|
887 | 17'b00100000000000000 : slv_ip2bus_data <= {Radio4_RSSI_ADC_CLAMP, |
---|
888 | Radio3_RSSI_ADC_CLAMP, |
---|
889 | Radio2_RSSI_ADC_CLAMP, |
---|
890 | Radio1_RSSI_ADC_CLAMP, |
---|
891 | Radio4_RSSI_ADC_HIZ, |
---|
892 | Radio3_RSSI_ADC_HIZ, |
---|
893 | Radio2_RSSI_ADC_HIZ, |
---|
894 | Radio1_RSSI_ADC_HIZ, |
---|
895 | Radio4_RSSI_ADC_OTR, |
---|
896 | Radio3_RSSI_ADC_OTR, |
---|
897 | Radio2_RSSI_ADC_OTR, |
---|
898 | Radio1_RSSI_ADC_OTR, |
---|
899 | slv_reg4[12:23], |
---|
900 | Radio4_ADC_RX_OTRB, |
---|
901 | Radio3_ADC_RX_OTRB, |
---|
902 | Radio2_ADC_RX_OTRB, |
---|
903 | Radio1_ADC_RX_OTRB, |
---|
904 | Radio4_ADC_RX_OTRA, |
---|
905 | Radio3_ADC_RX_OTRA, |
---|
906 | Radio2_ADC_RX_OTRA, |
---|
907 | Radio1_ADC_RX_OTRA}; |
---|
908 | 17'b00010000000000000 : slv_ip2bus_data <= {Radio2_TX_DAC_PLL_LOCK, |
---|
909 | slv_reg3[1], |
---|
910 | Radio2_DIPSW[3], |
---|
911 | Radio2_DIPSW[2], |
---|
912 | Radio2_DIPSW[1], |
---|
913 | Radio2_DIPSW[0], |
---|
914 | Radio2_RSSI_ADC_D, |
---|
915 | Radio1_TX_DAC_PLL_LOCK, |
---|
916 | slv_reg3[17], |
---|
917 | Radio1_DIPSW[3], |
---|
918 | Radio1_DIPSW[2], |
---|
919 | Radio1_DIPSW[1], |
---|
920 | Radio1_DIPSW[0], |
---|
921 | Radio1_RSSI_ADC_D}; |
---|
922 | 17'b00001000000000000 : slv_ip2bus_data <= {Radio4_TX_DAC_PLL_LOCK, |
---|
923 | slv_reg4[1], |
---|
924 | Radio4_DIPSW[3], |
---|
925 | Radio4_DIPSW[2], |
---|
926 | Radio4_DIPSW[1], |
---|
927 | Radio4_DIPSW[0], |
---|
928 | Radio4_RSSI_ADC_D, |
---|
929 | Radio3_TX_DAC_PLL_LOCK, |
---|
930 | slv_reg4[17], |
---|
931 | Radio3_DIPSW[3], |
---|
932 | Radio3_DIPSW[2], |
---|
933 | Radio3_DIPSW[1], |
---|
934 | Radio3_DIPSW[0], |
---|
935 | Radio3_RSSI_ADC_D}; |
---|
936 | 17'b00000100000000000 : slv_ip2bus_data <= {slv_reg5[0:22], mytip, slv_reg5[24:31]}; |
---|
937 | 17'b00000010000000000 : slv_ip2bus_data <= slv_reg6; |
---|
938 | 17'b00000001000000000 : slv_ip2bus_data <= slv_reg7; |
---|
939 | 17'b00000000100000000 : slv_ip2bus_data <= slv_reg8; |
---|
940 | 17'b00000000010000000 : slv_ip2bus_data <= slv_reg9; |
---|
941 | 17'b00000000001000000 : slv_ip2bus_data <= slv_reg10; |
---|
942 | 17'b00000000000100000 : slv_ip2bus_data <= slv_reg11; |
---|
943 | 17'b00000000000010000 : slv_ip2bus_data <= slv_reg12; |
---|
944 | 17'b00000000000001000 : slv_ip2bus_data <= slv_reg13; |
---|
945 | 17'b00000000000000100 : slv_ip2bus_data <= slv_reg14; |
---|
946 | 17'b00000000000000010 : slv_ip2bus_data <= slv_reg15; |
---|
947 | 17'b00000000000000001 : slv_ip2bus_data <= slv_reg16; |
---|
948 | default : slv_ip2bus_data <= 0; |
---|
949 | endcase |
---|
950 | |
---|
951 | end // SLAVE_REG_READ_PROC |
---|
952 | |
---|
953 | // ------------------------------------------------------------ |
---|
954 | // Example code to drive IP to Bus signals |
---|
955 | // ------------------------------------------------------------ |
---|
956 | |
---|
957 | assign IP2Bus_Data = slv_ip2bus_data; |
---|
958 | assign IP2Bus_WrAck = slv_write_ack; |
---|
959 | assign IP2Bus_RdAck = slv_read_ack; |
---|
960 | assign IP2Bus_Error = 0; |
---|
961 | |
---|
962 | endmodule |
---|