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radio_controller.vhd

Last change on this file was 1883, checked in by murphpo, 11 years ago

File size: 39.0 KB

Line
1	------------------------------------------------------------------------------
2	-- radio_controller.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: radio_controller.vhd
36	-- Version: 3.00.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Wed Jul 04 20:55:56 2012 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68
69	library plbv46_slave_single_v1_01_a;
70	use plbv46_slave_single_v1_01_a.plbv46_slave_single;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_BASEADDR -- PLBv46 slave: base address
77	-- C_HIGHADDR -- PLBv46 slave: high address
78	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
79	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
80	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
81	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
82	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
83	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
84	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
85	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
86	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
87	-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
88	-- C_FAMILY -- Xilinx FPGA family
89	--
90	-- Definition of Ports:
91	-- SPLB_Clk -- PLB main bus clock
92	-- SPLB_Rst -- PLB main bus reset
93	-- PLB_ABus -- PLB address bus
94	-- PLB_UABus -- PLB upper address bus
95	-- PLB_PAValid -- PLB primary address valid indicator
96	-- PLB_SAValid -- PLB secondary address valid indicator
97	-- PLB_rdPrim -- PLB secondary to primary read request indicator
98	-- PLB_wrPrim -- PLB secondary to primary write request indicator
99	-- PLB_masterID -- PLB current master identifier
100	-- PLB_abort -- PLB abort request indicator
101	-- PLB_busLock -- PLB bus lock
102	-- PLB_RNW -- PLB read/not write
103	-- PLB_BE -- PLB byte enables
104	-- PLB_MSize -- PLB master data bus size
105	-- PLB_size -- PLB transfer size
106	-- PLB_type -- PLB transfer type
107	-- PLB_lockErr -- PLB lock error indicator
108	-- PLB_wrDBus -- PLB write data bus
109	-- PLB_wrBurst -- PLB burst write transfer indicator
110	-- PLB_rdBurst -- PLB burst read transfer indicator
111	-- PLB_wrPendReq -- PLB write pending bus request indicator
112	-- PLB_rdPendReq -- PLB read pending bus request indicator
113	-- PLB_wrPendPri -- PLB write pending request priority
114	-- PLB_rdPendPri -- PLB read pending request priority
115	-- PLB_reqPri -- PLB current request priority
116	-- PLB_TAttribute -- PLB transfer attribute
117	-- Sl_addrAck -- Slave address acknowledge
118	-- Sl_SSize -- Slave data bus size
119	-- Sl_wait -- Slave wait indicator
120	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
121	-- Sl_wrDAck -- Slave write data acknowledge
122	-- Sl_wrComp -- Slave write transfer complete indicator
123	-- Sl_wrBTerm -- Slave terminate write burst transfer
124	-- Sl_rdDBus -- Slave read data bus
125	-- Sl_rdWdAddr -- Slave read word address
126	-- Sl_rdDAck -- Slave read data acknowledge
127	-- Sl_rdComp -- Slave read transfer complete indicator
128	-- Sl_rdBTerm -- Slave terminate read burst transfer
129	-- Sl_MBusy -- Slave busy indicator
130	-- Sl_MWrErr -- Slave write error indicator
131	-- Sl_MRdErr -- Slave read error indicator
132	-- Sl_MIRQ -- Slave interrupt indicator
133	------------------------------------------------------------------------------
134
135	entity radio_controller is
136	generic
137	(
138	-- ADD USER GENERICS BELOW THIS LINE ---------------
139	--USER generics added here
140	-- ADD USER GENERICS ABOVE THIS LINE ---------------
141
142	-- DO NOT EDIT BELOW THIS LINE ---------------------
143	-- Bus protocol parameters, do not add to or delete
144	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
145	C_HIGHADDR : std_logic_vector := X"00000000";
146	C_SPLB_AWIDTH : integer := 32;
147	C_SPLB_DWIDTH : integer := 128;
148	C_SPLB_NUM_MASTERS : integer := 8;
149	C_SPLB_MID_WIDTH : integer := 3;
150	C_SPLB_NATIVE_DWIDTH : integer := 32;
151	C_SPLB_P2P : integer := 0;
152	C_SPLB_SUPPORT_BURSTS : integer := 0;
153	C_SPLB_SMALLEST_MASTER : integer := 32;
154	C_SPLB_CLK_PERIOD_PS : integer := 10000;
155	C_INCLUDE_DPHASE_TIMER : integer := 0;
156	C_FAMILY : string := "virtex6"
157	-- DO NOT EDIT ABOVE THIS LINE ---------------------
158	);
159	port
160	(
161	-- ADD USER PORTS BELOW THIS LINE ------------------
162	RFA_TxEn : out std_logic;
163	RFB_TxEn : out std_logic;
164	RFC_TxEn : out std_logic;
165	RFD_TxEn : out std_logic;
166
167	RFA_RxEn : out std_logic;
168	RFB_RxEn : out std_logic;
169	RFC_RxEn : out std_logic;
170	RFD_RxEn : out std_logic;
171
172	RFA_RxHP : out std_logic;
173	RFB_RxHP : out std_logic;
174	RFC_RxHP : out std_logic;
175	RFD_RxHP : out std_logic;
176
177	RFA_SHDN : out std_logic;
178	RFB_SHDN : out std_logic;
179	RFC_SHDN : out std_logic;
180	RFD_SHDN : out std_logic;
181
182	RFA_SPI_SCLK : out std_logic;
183	RFB_SPI_SCLK : out std_logic;
184	RFC_SPI_SCLK : out std_logic;
185	RFD_SPI_SCLK : out std_logic;
186
187	RFA_SPI_MOSI : out std_logic;
188	RFB_SPI_MOSI : out std_logic;
189	RFC_SPI_MOSI : out std_logic;
190	RFD_SPI_MOSI : out std_logic;
191
192	RFA_SPI_CSn : out std_logic;
193	RFB_SPI_CSn : out std_logic;
194	RFC_SPI_CSn : out std_logic;
195	RFD_SPI_CSn : out std_logic;
196
197	RFA_B : out std_logic_vector(0 to 6);
198	RFB_B : out std_logic_vector(0 to 6);
199	RFC_B : out std_logic_vector(0 to 6);
200	RFD_B : out std_logic_vector(0 to 6);
201
202	RFA_LD : in std_logic;
203	RFB_LD : in std_logic;
204	RFC_LD : in std_logic;
205	RFD_LD : in std_logic;
206
207	RFA_PAEn_24 : out std_logic;
208	RFB_PAEn_24 : out std_logic;
209	RFC_PAEn_24 : out std_logic;
210	RFD_PAEn_24 : out std_logic;
211
212	RFA_PAEn_5 : out std_logic;
213	RFB_PAEn_5 : out std_logic;
214	RFC_PAEn_5 : out std_logic;
215	RFD_PAEn_5 : out std_logic;
216
217	RFA_AntSw : out std_logic_vector(0 to 1);
218	RFB_AntSw : out std_logic_vector(0 to 1);
219	RFC_AntSw : out std_logic_vector(0 to 1);
220	RFD_AntSw : out std_logic_vector(0 to 1);
221
222	RFA_DIPSW : in std_logic_vector(0 to 3);
223	RFB_DIPSW : in std_logic_vector(0 to 3);
224	RFC_DIPSW : in std_logic_vector(0 to 3);
225	RFD_DIPSW : in std_logic_vector(0 to 3);
226
227	RFA_RX_ADC_DCS : OUT std_logic;
228	RFB_RX_ADC_DCS : OUT std_logic;
229	RFC_RX_ADC_DCS : OUT std_logic;
230	RFD_RX_ADC_DCS : OUT std_logic;
231
232	RFA_RX_ADC_DFS : OUT std_logic;
233	RFB_RX_ADC_DFS : OUT std_logic;
234	RFC_RX_ADC_DFS : OUT std_logic;
235	RFD_RX_ADC_DFS : OUT std_logic;
236
237	RFA_RX_ADC_PWDN : OUT std_logic;
238	RFB_RX_ADC_PWDN : OUT std_logic;
239	RFC_RX_ADC_PWDN : OUT std_logic;
240	RFD_RX_ADC_PWDN : OUT std_logic;
241
242	RFA_RSSI_ADC_CLAMP : OUT std_logic;
243	RFB_RSSI_ADC_CLAMP : OUT std_logic;
244	RFC_RSSI_ADC_CLAMP : OUT std_logic;
245	RFD_RSSI_ADC_CLAMP : OUT std_logic;
246
247	RFA_RSSI_ADC_HIZ : OUT std_logic;
248	RFB_RSSI_ADC_HIZ : OUT std_logic;
249	RFC_RSSI_ADC_HIZ : OUT std_logic;
250	RFD_RSSI_ADC_HIZ : OUT std_logic;
251
252	RFA_RSSI_ADC_SLEEP : OUT std_logic;
253	RFB_RSSI_ADC_SLEEP : OUT std_logic;
254	RFC_RSSI_ADC_SLEEP : OUT std_logic;
255	RFD_RSSI_ADC_SLEEP : OUT std_logic;
256
257	RFA_DAC_SPI_CSn : OUT std_logic;
258	RFB_DAC_SPI_CSn : OUT std_logic;
259	RFC_DAC_SPI_CSn : OUT std_logic;
260	RFD_DAC_SPI_CSn : OUT std_logic;
261
262	RFA_DAC_SPI_SCLK : OUT std_logic;
263	RFB_DAC_SPI_SCLK : OUT std_logic;
264	RFC_DAC_SPI_SCLK : OUT std_logic;
265	RFD_DAC_SPI_SCLK : OUT std_logic;
266
267	RFA_DAC_SPI_MOSI : OUT std_logic;
268	RFB_DAC_SPI_MOSI : OUT std_logic;
269	RFC_DAC_SPI_MOSI : OUT std_logic;
270	RFD_DAC_SPI_MOSI : OUT std_logic;
271
272	RFA_DAC_SPI_MISO : IN std_logic;
273	RFB_DAC_SPI_MISO : IN std_logic;
274	RFC_DAC_SPI_MISO : IN std_logic;
275	RFD_DAC_SPI_MISO : IN std_logic;
276
277	RFA_DAC_RESET : OUT std_logic;
278	RFB_DAC_RESET : OUT std_logic;
279	RFC_DAC_RESET : OUT std_logic;
280	RFD_DAC_RESET : OUT std_logic;
281
282	RFA_DAC_PLLLOCK : IN std_logic;
283	RFB_DAC_PLLLOCK : IN std_logic;
284	RFC_DAC_PLLLOCK : IN std_logic;
285	RFD_DAC_PLLLOCK : IN std_logic;
286
287	usr_RFA_TxEn : in std_logic;
288	usr_RFB_TxEn : in std_logic;
289	usr_RFC_TxEn : in std_logic;
290	usr_RFD_TxEn : in std_logic;
291
292	usr_RFA_RxEn : in std_logic;
293	usr_RFB_RxEn : in std_logic;
294	usr_RFC_RxEn : in std_logic;
295	usr_RFD_RxEn : in std_logic;
296
297	usr_RFA_RxHP : in std_logic;
298	usr_RFB_RxHP : in std_logic;
299	usr_RFC_RxHP : in std_logic;
300	usr_RFD_RxHP : in std_logic;
301
302	usr_RFA_SHDN : in std_logic;
303	usr_RFB_SHDN : in std_logic;
304	usr_RFC_SHDN : in std_logic;
305	usr_RFD_SHDN : in std_logic;
306
307	usr_RFA_RxGainRF : in std_logic_vector(0 to 1);
308	usr_RFB_RxGainRF : in std_logic_vector(0 to 1);
309	usr_RFC_RxGainRF : in std_logic_vector(0 to 1);
310	usr_RFD_RxGainRF : in std_logic_vector(0 to 1);
311
312	usr_RFA_RxGainBB : in std_logic_vector(0 to 4);
313	usr_RFB_RxGainBB : in std_logic_vector(0 to 4);
314	usr_RFC_RxGainBB : in std_logic_vector(0 to 4);
315	usr_RFD_RxGainBB : in std_logic_vector(0 to 4);
316
317	usr_RFA_TxGain : in std_logic_vector(0 to 5);
318	usr_RFB_TxGain : in std_logic_vector(0 to 5);
319	usr_RFC_TxGain : in std_logic_vector(0 to 5);
320	usr_RFD_TxGain : in std_logic_vector(0 to 5);
321
322	usr_SPI_ctrlSrc : in std_logic;
323	usr_SPI_go : in std_logic;
324	usr_SPI_active : out std_logic;
325	usr_SPI_rfsel : in std_logic_vector(0 to 3);
326	usr_SPI_regaddr : in std_logic_vector(0 to 3);
327	usr_SPI_regdata : in std_logic_vector(0 to 13);
328
329	usr_RFA_PHYStart : out std_logic;
330	usr_RFB_PHYStart : out std_logic;
331	usr_RFC_PHYStart : out std_logic;
332	usr_RFD_PHYStart : out std_logic;
333
334	usr_any_PHYStart : out std_logic;
335
336	usr_RFA_statLED_Tx : out std_logic;
337	usr_RFA_statLED_Rx : out std_logic;
338	usr_RFA_statLED_NoLock : OUT std_logic;
339
340	usr_RFB_statLED_Tx : out std_logic;
341	usr_RFB_statLED_Rx : out std_logic;
342	usr_RFB_statLED_NoLock : OUT std_logic;
343
344	usr_RFC_statLED_Tx : out std_logic;
345	usr_RFC_statLED_Rx : out std_logic;
346	usr_RFC_statLED_NoLock : OUT std_logic;
347
348	usr_RFD_statLED_Tx : out std_logic;
349	usr_RFD_statLED_Rx : out std_logic;
350	usr_RFD_statLED_NoLock : OUT std_logic;
351
352	-- ADD USER PORTS ABOVE THIS LINE ------------------
353
354	-- DO NOT EDIT BELOW THIS LINE ---------------------
355	-- Bus protocol ports, do not add to or delete
356	SPLB_Clk : in std_logic;
357	SPLB_Rst : in std_logic;
358	PLB_ABus : in std_logic_vector(0 to 31);
359	PLB_UABus : in std_logic_vector(0 to 31);
360	PLB_PAValid : in std_logic;
361	PLB_SAValid : in std_logic;
362	PLB_rdPrim : in std_logic;
363	PLB_wrPrim : in std_logic;
364	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
365	PLB_abort : in std_logic;
366	PLB_busLock : in std_logic;
367	PLB_RNW : in std_logic;
368	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
369	PLB_MSize : in std_logic_vector(0 to 1);
370	PLB_size : in std_logic_vector(0 to 3);
371	PLB_type : in std_logic_vector(0 to 2);
372	PLB_lockErr : in std_logic;
373	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
374	PLB_wrBurst : in std_logic;
375	PLB_rdBurst : in std_logic;
376	PLB_wrPendReq : in std_logic;
377	PLB_rdPendReq : in std_logic;
378	PLB_wrPendPri : in std_logic_vector(0 to 1);
379	PLB_rdPendPri : in std_logic_vector(0 to 1);
380	PLB_reqPri : in std_logic_vector(0 to 1);
381	PLB_TAttribute : in std_logic_vector(0 to 15);
382	Sl_addrAck : out std_logic;
383	Sl_SSize : out std_logic_vector(0 to 1);
384	Sl_wait : out std_logic;
385	Sl_rearbitrate : out std_logic;
386	Sl_wrDAck : out std_logic;
387	Sl_wrComp : out std_logic;
388	Sl_wrBTerm : out std_logic;
389	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
390	Sl_rdWdAddr : out std_logic_vector(0 to 3);
391	Sl_rdDAck : out std_logic;
392	Sl_rdComp : out std_logic;
393	Sl_rdBTerm : out std_logic;
394	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
395	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
396	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
397	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
398	-- DO NOT EDIT ABOVE THIS LINE ---------------------
399	);
400
401	attribute MAX_FANOUT : string;
402	attribute SIGIS : string;
403
404	attribute SIGIS of SPLB_Clk : signal is "CLK";
405	attribute SIGIS of SPLB_Rst : signal is "RST";
406
407	end entity radio_controller;
408
409	------------------------------------------------------------------------------
410	-- Architecture section
411	------------------------------------------------------------------------------
412
413	architecture IMP of radio_controller is
414
415	------------------------------------------
416	-- Array of base/high address pairs for each address range
417	------------------------------------------
418	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
419	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
420	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
421
422	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
423	(
424	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
425	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
426	);
427
428	------------------------------------------
429	-- Array of desired number of chip enables for each address range
430	------------------------------------------
431	constant USER_SLV_NUM_REG : integer := 64;
432	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
433
434	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
435	(
436	0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
437	);
438
439	------------------------------------------
440	-- Ratio of bus clock to core clock (for use in dual clock systems)
441	-- 1 = ratio is 1:1
442	-- 2 = ratio is 2:1
443	------------------------------------------
444	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
445
446	------------------------------------------
447	-- Width of the slave data bus (32 only)
448	------------------------------------------
449	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
450
451	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
452
453	------------------------------------------
454	-- Index for CS/CE
455	------------------------------------------
456	constant USER_SLV_CS_INDEX : integer := 0;
457	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
458
459	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
460
461	------------------------------------------
462	-- IP Interconnect (IPIC) signal declarations
463	------------------------------------------
464	signal ipif_Bus2IP_Clk : std_logic;
465	signal ipif_Bus2IP_Reset : std_logic;
466	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
467	signal ipif_IP2Bus_WrAck : std_logic;
468	signal ipif_IP2Bus_RdAck : std_logic;
469	signal ipif_IP2Bus_Error : std_logic;
470	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
471	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
472	signal ipif_Bus2IP_RNW : std_logic;
473	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
474	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
475	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
476	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
477	signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
478	signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
479	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
480	signal user_IP2Bus_RdAck : std_logic;
481	signal user_IP2Bus_WrAck : std_logic;
482	signal user_IP2Bus_Error : std_logic;
483
484	------------------------------------------
485	-- Component declaration for verilog user logic
486	------------------------------------------
487	component user_logic is
488	generic
489	(
490	-- ADD USER GENERICS BELOW THIS LINE ---------------
491	--USER generics added here
492	-- ADD USER GENERICS ABOVE THIS LINE ---------------
493
494	-- DO NOT EDIT BELOW THIS LINE ---------------------
495	-- Bus protocol parameters, do not add to or delete
496	C_SLV_DWIDTH : integer := 32;
497	C_NUM_REG : integer := 64
498	-- DO NOT EDIT ABOVE THIS LINE ---------------------
499	);
500	port
501	(
502	-- ADD USER PORTS BELOW THIS LINE ------------------
503	RFA_TxEn : out std_logic;
504	RFB_TxEn : out std_logic;
505	RFC_TxEn : out std_logic;
506	RFD_TxEn : out std_logic;
507
508	RFA_RxEn : out std_logic;
509	RFB_RxEn : out std_logic;
510	RFC_RxEn : out std_logic;
511	RFD_RxEn : out std_logic;
512
513	RFA_RxHP : out std_logic;
514	RFB_RxHP : out std_logic;
515	RFC_RxHP : out std_logic;
516	RFD_RxHP : out std_logic;
517
518	RFA_SHDN : out std_logic;
519	RFB_SHDN : out std_logic;
520	RFC_SHDN : out std_logic;
521	RFD_SHDN : out std_logic;
522
523	RFA_SPI_SCLK : out std_logic;
524	RFB_SPI_SCLK : out std_logic;
525	RFC_SPI_SCLK : out std_logic;
526	RFD_SPI_SCLK : out std_logic;
527
528	RFA_SPI_MOSI : out std_logic;
529	RFB_SPI_MOSI : out std_logic;
530	RFC_SPI_MOSI : out std_logic;
531	RFD_SPI_MOSI : out std_logic;
532
533	RFA_SPI_CSn : out std_logic;
534	RFB_SPI_CSn : out std_logic;
535	RFC_SPI_CSn : out std_logic;
536	RFD_SPI_CSn : out std_logic;
537
538	RFA_B : out std_logic_vector(0 to 6);
539	RFB_B : out std_logic_vector(0 to 6);
540	RFC_B : out std_logic_vector(0 to 6);
541	RFD_B : out std_logic_vector(0 to 6);
542
543	RFA_LD : in std_logic;
544	RFB_LD : in std_logic;
545	RFC_LD : in std_logic;
546	RFD_LD : in std_logic;
547
548	RFA_PAEn_24 : out std_logic;
549	RFB_PAEn_24 : out std_logic;
550	RFC_PAEn_24 : out std_logic;
551	RFD_PAEn_24 : out std_logic;
552
553	RFA_PAEn_5 : out std_logic;
554	RFB_PAEn_5 : out std_logic;
555	RFC_PAEn_5 : out std_logic;
556	RFD_PAEn_5 : out std_logic;
557
558	RFA_AntSw : out std_logic_vector(0 to 1);
559	RFB_AntSw : out std_logic_vector(0 to 1);
560	RFC_AntSw : out std_logic_vector(0 to 1);
561	RFD_AntSw : out std_logic_vector(0 to 1);
562
563	RFA_DIPSW : in std_logic_vector(0 to 3);
564	RFB_DIPSW : in std_logic_vector(0 to 3);
565	RFC_DIPSW : in std_logic_vector(0 to 3);
566	RFD_DIPSW : in std_logic_vector(0 to 3);
567
568	RFA_RX_ADC_DCS : OUT std_logic;
569	RFB_RX_ADC_DCS : OUT std_logic;
570	RFC_RX_ADC_DCS : OUT std_logic;
571	RFD_RX_ADC_DCS : OUT std_logic;
572
573	RFA_RX_ADC_DFS : OUT std_logic;
574	RFB_RX_ADC_DFS : OUT std_logic;
575	RFC_RX_ADC_DFS : OUT std_logic;
576	RFD_RX_ADC_DFS : OUT std_logic;
577
578	RFA_RX_ADC_PWDN : OUT std_logic;
579	RFB_RX_ADC_PWDN : OUT std_logic;
580	RFC_RX_ADC_PWDN : OUT std_logic;
581	RFD_RX_ADC_PWDN : OUT std_logic;
582
583	RFA_RSSI_ADC_CLAMP : OUT std_logic;
584	RFB_RSSI_ADC_CLAMP : OUT std_logic;
585	RFC_RSSI_ADC_CLAMP : OUT std_logic;
586	RFD_RSSI_ADC_CLAMP : OUT std_logic;
587
588	RFA_RSSI_ADC_HIZ : OUT std_logic;
589	RFB_RSSI_ADC_HIZ : OUT std_logic;
590	RFC_RSSI_ADC_HIZ : OUT std_logic;
591	RFD_RSSI_ADC_HIZ : OUT std_logic;
592
593	RFA_RSSI_ADC_SLEEP : OUT std_logic;
594	RFB_RSSI_ADC_SLEEP : OUT std_logic;
595	RFC_RSSI_ADC_SLEEP : OUT std_logic;
596	RFD_RSSI_ADC_SLEEP : OUT std_logic;
597
598	RFA_DAC_SPI_CSn : OUT std_logic;
599	RFB_DAC_SPI_CSn : OUT std_logic;
600	RFC_DAC_SPI_CSn : OUT std_logic;
601	RFD_DAC_SPI_CSn : OUT std_logic;
602
603	RFA_DAC_SPI_SCLK : OUT std_logic;
604	RFB_DAC_SPI_SCLK : OUT std_logic;
605	RFC_DAC_SPI_SCLK : OUT std_logic;
606	RFD_DAC_SPI_SCLK : OUT std_logic;
607
608	RFA_DAC_SPI_MOSI : OUT std_logic;
609	RFB_DAC_SPI_MOSI : OUT std_logic;
610	RFC_DAC_SPI_MOSI : OUT std_logic;
611	RFD_DAC_SPI_MOSI : OUT std_logic;
612
613	RFA_DAC_SPI_MISO : IN std_logic;
614	RFB_DAC_SPI_MISO : IN std_logic;
615	RFC_DAC_SPI_MISO : IN std_logic;
616	RFD_DAC_SPI_MISO : IN std_logic;
617
618	RFA_DAC_RESET : OUT std_logic;
619	RFB_DAC_RESET : OUT std_logic;
620	RFC_DAC_RESET : OUT std_logic;
621	RFD_DAC_RESET : OUT std_logic;
622
623	RFA_DAC_PLLLOCK : IN std_logic;
624	RFB_DAC_PLLLOCK : IN std_logic;
625	RFC_DAC_PLLLOCK : IN std_logic;
626	RFD_DAC_PLLLOCK : IN std_logic;
627
628	usr_RFA_TxEn : in std_logic;
629	usr_RFB_TxEn : in std_logic;
630	usr_RFC_TxEn : in std_logic;
631	usr_RFD_TxEn : in std_logic;
632
633	usr_RFA_RxEn : in std_logic;
634	usr_RFB_RxEn : in std_logic;
635	usr_RFC_RxEn : in std_logic;
636	usr_RFD_RxEn : in std_logic;
637
638	usr_RFA_RxHP : in std_logic;
639	usr_RFB_RxHP : in std_logic;
640	usr_RFC_RxHP : in std_logic;
641	usr_RFD_RxHP : in std_logic;
642
643	usr_RFA_SHDN : in std_logic;
644	usr_RFB_SHDN : in std_logic;
645	usr_RFC_SHDN : in std_logic;
646	usr_RFD_SHDN : in std_logic;
647
648	usr_RFA_RxGainRF : in std_logic_vector(0 to 1);
649	usr_RFB_RxGainRF : in std_logic_vector(0 to 1);
650	usr_RFC_RxGainRF : in std_logic_vector(0 to 1);
651	usr_RFD_RxGainRF : in std_logic_vector(0 to 1);
652
653	usr_RFA_RxGainBB : in std_logic_vector(0 to 4);
654	usr_RFB_RxGainBB : in std_logic_vector(0 to 4);
655	usr_RFC_RxGainBB : in std_logic_vector(0 to 4);
656	usr_RFD_RxGainBB : in std_logic_vector(0 to 4);
657
658	usr_RFA_TxGain : in std_logic_vector(0 to 5);
659	usr_RFB_TxGain : in std_logic_vector(0 to 5);
660	usr_RFC_TxGain : in std_logic_vector(0 to 5);
661	usr_RFD_TxGain : in std_logic_vector(0 to 5);
662
663	usr_SPI_ctrlSrc : in std_logic;
664	usr_SPI_go : in std_logic;
665	usr_SPI_active : out std_logic;
666	usr_SPI_rfsel : in std_logic_vector(0 to 3);
667	usr_SPI_regaddr : in std_logic_vector(0 to 3);
668	usr_SPI_regdata : in std_logic_vector(0 to 13);
669
670	usr_RFA_PHYStart : out std_logic;
671	usr_RFB_PHYStart : out std_logic;
672	usr_RFC_PHYStart : out std_logic;
673	usr_RFD_PHYStart : out std_logic;
674
675	usr_any_PHYStart : out std_logic;
676
677	usr_RFA_statLED_Tx : out std_logic;
678	usr_RFA_statLED_Rx : out std_logic;
679	usr_RFA_statLED_NoLock : OUT std_logic;
680
681	usr_RFB_statLED_Tx : out std_logic;
682	usr_RFB_statLED_Rx : out std_logic;
683	usr_RFB_statLED_NoLock : OUT std_logic;
684
685	usr_RFC_statLED_Tx : out std_logic;
686	usr_RFC_statLED_Rx : out std_logic;
687	usr_RFC_statLED_NoLock : OUT std_logic;
688
689	usr_RFD_statLED_Tx : out std_logic;
690	usr_RFD_statLED_Rx : out std_logic;
691	usr_RFD_statLED_NoLock : OUT std_logic;
692
693	-- ADD USER PORTS ABOVE THIS LINE ------------------
694
695	-- DO NOT EDIT BELOW THIS LINE ---------------------
696	-- Bus protocol ports, do not add to or delete
697	Bus2IP_Clk : in std_logic;
698	Bus2IP_Reset : in std_logic;
699	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
700	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
701	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
702	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
703	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
704	IP2Bus_RdAck : out std_logic;
705	IP2Bus_WrAck : out std_logic;
706	IP2Bus_Error : out std_logic
707	-- DO NOT EDIT ABOVE THIS LINE ---------------------
708	);
709	end component user_logic;
710
711	begin
712
713	------------------------------------------
714	-- instantiate plbv46_slave_single
715	------------------------------------------
716	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
717	generic map
718	(
719	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
720	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
721	C_SPLB_P2P => C_SPLB_P2P,
722	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
723	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
724	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
725	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
726	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
727	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
728	C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
729	C_FAMILY => C_FAMILY
730	)
731	port map
732	(
733	SPLB_Clk => SPLB_Clk,
734	SPLB_Rst => SPLB_Rst,
735	PLB_ABus => PLB_ABus,
736	PLB_UABus => PLB_UABus,
737	PLB_PAValid => PLB_PAValid,
738	PLB_SAValid => PLB_SAValid,
739	PLB_rdPrim => PLB_rdPrim,
740	PLB_wrPrim => PLB_wrPrim,
741	PLB_masterID => PLB_masterID,
742	PLB_abort => PLB_abort,
743	PLB_busLock => PLB_busLock,
744	PLB_RNW => PLB_RNW,
745	PLB_BE => PLB_BE,
746	PLB_MSize => PLB_MSize,
747	PLB_size => PLB_size,
748	PLB_type => PLB_type,
749	PLB_lockErr => PLB_lockErr,
750	PLB_wrDBus => PLB_wrDBus,
751	PLB_wrBurst => PLB_wrBurst,
752	PLB_rdBurst => PLB_rdBurst,
753	PLB_wrPendReq => PLB_wrPendReq,
754	PLB_rdPendReq => PLB_rdPendReq,
755	PLB_wrPendPri => PLB_wrPendPri,
756	PLB_rdPendPri => PLB_rdPendPri,
757	PLB_reqPri => PLB_reqPri,
758	PLB_TAttribute => PLB_TAttribute,
759	Sl_addrAck => Sl_addrAck,
760	Sl_SSize => Sl_SSize,
761	Sl_wait => Sl_wait,
762	Sl_rearbitrate => Sl_rearbitrate,
763	Sl_wrDAck => Sl_wrDAck,
764	Sl_wrComp => Sl_wrComp,
765	Sl_wrBTerm => Sl_wrBTerm,
766	Sl_rdDBus => Sl_rdDBus,
767	Sl_rdWdAddr => Sl_rdWdAddr,
768	Sl_rdDAck => Sl_rdDAck,
769	Sl_rdComp => Sl_rdComp,
770	Sl_rdBTerm => Sl_rdBTerm,
771	Sl_MBusy => Sl_MBusy,
772	Sl_MWrErr => Sl_MWrErr,
773	Sl_MRdErr => Sl_MRdErr,
774	Sl_MIRQ => Sl_MIRQ,
775	Bus2IP_Clk => ipif_Bus2IP_Clk,
776	Bus2IP_Reset => ipif_Bus2IP_Reset,
777	IP2Bus_Data => ipif_IP2Bus_Data,
778	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
779	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
780	IP2Bus_Error => ipif_IP2Bus_Error,
781	Bus2IP_Addr => ipif_Bus2IP_Addr,
782	Bus2IP_Data => ipif_Bus2IP_Data,
783	Bus2IP_RNW => ipif_Bus2IP_RNW,
784	Bus2IP_BE => ipif_Bus2IP_BE,
785	Bus2IP_CS => ipif_Bus2IP_CS,
786	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
787	Bus2IP_WrCE => ipif_Bus2IP_WrCE
788	);
789
790	------------------------------------------
791	-- instantiate User Logic
792	------------------------------------------
793	USER_LOGIC_I : component user_logic
794	generic map
795	(
796	-- MAP USER GENERICS BELOW THIS LINE ---------------
797	--USER generics mapped here
798	-- MAP USER GENERICS ABOVE THIS LINE ---------------
799
800	C_SLV_DWIDTH => USER_SLV_DWIDTH,
801	C_NUM_REG => USER_NUM_REG
802	)
803	port map
804	(
805	-- MAP USER PORTS BELOW THIS LINE ------------------
806	RFA_TxEn => RFA_TxEn,
807	RFB_TxEn => RFB_TxEn,
808	RFC_TxEn => RFC_TxEn,
809	RFD_TxEn => RFD_TxEn,
810
811	RFA_RxEn => RFA_RxEn,
812	RFB_RxEn => RFB_RxEn,
813	RFC_RxEn => RFC_RxEn,
814	RFD_RxEn => RFD_RxEn,
815
816	RFA_RxHP => RFA_RxHP,
817	RFB_RxHP => RFB_RxHP,
818	RFC_RxHP => RFC_RxHP,
819	RFD_RxHP => RFD_RxHP,
820
821	RFA_SHDN => RFA_SHDN,
822	RFB_SHDN => RFB_SHDN,
823	RFC_SHDN => RFC_SHDN,
824	RFD_SHDN => RFD_SHDN,
825
826	RFA_SPI_SCLK => RFA_SPI_SCLK,
827	RFB_SPI_SCLK => RFB_SPI_SCLK,
828	RFC_SPI_SCLK => RFC_SPI_SCLK,
829	RFD_SPI_SCLK => RFD_SPI_SCLK,
830
831	RFA_SPI_MOSI => RFA_SPI_MOSI,
832	RFB_SPI_MOSI => RFB_SPI_MOSI,
833	RFC_SPI_MOSI => RFC_SPI_MOSI,
834	RFD_SPI_MOSI => RFD_SPI_MOSI,
835
836	RFA_SPI_CSn => RFA_SPI_CSn,
837	RFB_SPI_CSn => RFB_SPI_CSn,
838	RFC_SPI_CSn => RFC_SPI_CSn,
839	RFD_SPI_CSn => RFD_SPI_CSn,
840
841	RFA_B => RFA_B,
842	RFB_B => RFB_B,
843	RFC_B => RFC_B,
844	RFD_B => RFD_B,
845
846	RFA_LD => RFA_LD,
847	RFB_LD => RFB_LD,
848	RFC_LD => RFC_LD,
849	RFD_LD => RFD_LD,
850
851	RFA_PAEn_24 => RFA_PAEn_24,
852	RFB_PAEn_24 => RFB_PAEn_24,
853	RFC_PAEn_24 => RFC_PAEn_24,
854	RFD_PAEn_24 => RFD_PAEn_24,
855
856	RFA_PAEn_5 => RFA_PAEn_5,
857	RFB_PAEn_5 => RFB_PAEn_5,
858	RFC_PAEn_5 => RFC_PAEn_5,
859	RFD_PAEn_5 => RFD_PAEn_5,
860
861	RFA_AntSw => RFA_AntSw,
862	RFB_AntSw => RFB_AntSw,
863	RFC_AntSw => RFC_AntSw,
864	RFD_AntSw => RFD_AntSw,
865
866	RFA_DIPSW => RFA_DIPSW,
867	RFB_DIPSW => RFB_DIPSW,
868	RFC_DIPSW => RFC_DIPSW,
869	RFD_DIPSW => RFD_DIPSW,
870
871	RFA_RX_ADC_DCS => RFA_RX_ADC_DCS,
872	RFB_RX_ADC_DCS => RFB_RX_ADC_DCS,
873	RFC_RX_ADC_DCS => RFC_RX_ADC_DCS,
874	RFD_RX_ADC_DCS => RFD_RX_ADC_DCS,
875
876	RFA_RX_ADC_DFS => RFA_RX_ADC_DFS,
877	RFB_RX_ADC_DFS => RFB_RX_ADC_DFS,
878	RFC_RX_ADC_DFS => RFC_RX_ADC_DFS,
879	RFD_RX_ADC_DFS => RFD_RX_ADC_DFS,
880
881	RFA_RX_ADC_PWDN => RFA_RX_ADC_PWDN,
882	RFB_RX_ADC_PWDN => RFB_RX_ADC_PWDN,
883	RFC_RX_ADC_PWDN => RFC_RX_ADC_PWDN,
884	RFD_RX_ADC_PWDN => RFD_RX_ADC_PWDN,
885
886	RFA_RSSI_ADC_CLAMP => RFA_RSSI_ADC_CLAMP,
887	RFB_RSSI_ADC_CLAMP => RFB_RSSI_ADC_CLAMP,
888	RFC_RSSI_ADC_CLAMP => RFC_RSSI_ADC_CLAMP,
889	RFD_RSSI_ADC_CLAMP => RFD_RSSI_ADC_CLAMP,
890
891	RFA_RSSI_ADC_HIZ => RFA_RSSI_ADC_HIZ,
892	RFB_RSSI_ADC_HIZ => RFB_RSSI_ADC_HIZ,
893	RFC_RSSI_ADC_HIZ => RFC_RSSI_ADC_HIZ,
894	RFD_RSSI_ADC_HIZ => RFD_RSSI_ADC_HIZ,
895
896	RFA_RSSI_ADC_SLEEP => RFA_RSSI_ADC_SLEEP,
897	RFB_RSSI_ADC_SLEEP => RFB_RSSI_ADC_SLEEP,
898	RFC_RSSI_ADC_SLEEP => RFC_RSSI_ADC_SLEEP,
899	RFD_RSSI_ADC_SLEEP => RFD_RSSI_ADC_SLEEP,
900
901	RFA_DAC_SPI_CSn => RFA_DAC_SPI_CSn,
902	RFB_DAC_SPI_CSn => RFB_DAC_SPI_CSn,
903	RFC_DAC_SPI_CSn => RFC_DAC_SPI_CSn,
904	RFD_DAC_SPI_CSn => RFD_DAC_SPI_CSn,
905
906	RFA_DAC_SPI_SCLK => RFA_DAC_SPI_SCLK,
907	RFB_DAC_SPI_SCLK => RFB_DAC_SPI_SCLK,
908	RFC_DAC_SPI_SCLK => RFC_DAC_SPI_SCLK,
909	RFD_DAC_SPI_SCLK => RFD_DAC_SPI_SCLK,
910
911	RFA_DAC_SPI_MOSI => RFA_DAC_SPI_MOSI,
912	RFB_DAC_SPI_MOSI => RFB_DAC_SPI_MOSI,
913	RFC_DAC_SPI_MOSI => RFC_DAC_SPI_MOSI,
914	RFD_DAC_SPI_MOSI => RFD_DAC_SPI_MOSI,
915
916	RFA_DAC_SPI_MISO => RFA_DAC_SPI_MISO,
917	RFB_DAC_SPI_MISO => RFB_DAC_SPI_MISO,
918	RFC_DAC_SPI_MISO => RFC_DAC_SPI_MISO,
919	RFD_DAC_SPI_MISO => RFD_DAC_SPI_MISO,
920
921	RFA_DAC_RESET => RFA_DAC_RESET,
922	RFB_DAC_RESET => RFB_DAC_RESET,
923	RFC_DAC_RESET => RFC_DAC_RESET,
924	RFD_DAC_RESET => RFD_DAC_RESET,
925
926	RFA_DAC_PLLLOCK => RFA_DAC_PLLLOCK,
927	RFB_DAC_PLLLOCK => RFB_DAC_PLLLOCK,
928	RFC_DAC_PLLLOCK => RFC_DAC_PLLLOCK,
929	RFD_DAC_PLLLOCK => RFD_DAC_PLLLOCK,
930
931	usr_RFA_TxEn => usr_RFA_TxEn,
932	usr_RFB_TxEn => usr_RFB_TxEn,
933	usr_RFC_TxEn => usr_RFC_TxEn,
934	usr_RFD_TxEn => usr_RFD_TxEn,
935
936	usr_RFA_RxEn => usr_RFA_RxEn,
937	usr_RFB_RxEn => usr_RFB_RxEn,
938	usr_RFC_RxEn => usr_RFC_RxEn,
939	usr_RFD_RxEn => usr_RFD_RxEn,
940
941	usr_RFA_RxHP => usr_RFA_RxHP,
942	usr_RFB_RxHP => usr_RFB_RxHP,
943	usr_RFC_RxHP => usr_RFC_RxHP,
944	usr_RFD_RxHP => usr_RFD_RxHP,
945
946	usr_RFA_SHDN => usr_RFA_SHDN,
947	usr_RFB_SHDN => usr_RFB_SHDN,
948	usr_RFC_SHDN => usr_RFC_SHDN,
949	usr_RFD_SHDN => usr_RFD_SHDN,
950
951	usr_RFA_RxGainRF => usr_RFA_RxGainRF,
952	usr_RFB_RxGainRF => usr_RFB_RxGainRF,
953	usr_RFC_RxGainRF => usr_RFC_RxGainRF,
954	usr_RFD_RxGainRF => usr_RFD_RxGainRF,
955
956	usr_RFA_RxGainBB => usr_RFA_RxGainBB,
957	usr_RFB_RxGainBB => usr_RFB_RxGainBB,
958	usr_RFC_RxGainBB => usr_RFC_RxGainBB,
959	usr_RFD_RxGainBB => usr_RFD_RxGainBB,
960
961	usr_RFA_TxGain => usr_RFA_TxGain,
962	usr_RFB_TxGain => usr_RFB_TxGain,
963	usr_RFC_TxGain => usr_RFC_TxGain,
964	usr_RFD_TxGain => usr_RFD_TxGain,
965
966	usr_SPI_ctrlSrc => usr_SPI_ctrlSrc,
967	usr_SPI_go => usr_SPI_go,
968	usr_SPI_active => usr_SPI_active,
969	usr_SPI_rfsel => usr_SPI_rfsel,
970	usr_SPI_regaddr => usr_SPI_regaddr,
971	usr_SPI_regdata => usr_SPI_regdata,
972
973	usr_RFA_PHYStart => usr_RFA_PHYStart,
974	usr_RFB_PHYStart => usr_RFB_PHYStart,
975	usr_RFC_PHYStart => usr_RFC_PHYStart,
976	usr_RFD_PHYStart => usr_RFD_PHYStart,
977
978	usr_any_PHYStart => usr_any_PHYStart,
979
980	usr_RFA_statLED_Tx => usr_RFA_statLED_Tx,
981	usr_RFA_statLED_Rx => usr_RFA_statLED_Rx,
982	usr_RFA_statLED_NoLock => usr_RFA_statLED_NoLock,
983
984	usr_RFB_statLED_Tx => usr_RFB_statLED_Tx,
985	usr_RFB_statLED_Rx => usr_RFB_statLED_Rx,
986	usr_RFB_statLED_NoLock => usr_RFB_statLED_NoLock,
987
988	usr_RFC_statLED_Tx => usr_RFC_statLED_Tx,
989	usr_RFC_statLED_Rx => usr_RFC_statLED_Rx,
990	usr_RFC_statLED_NoLock => usr_RFC_statLED_NoLock,
991
992	usr_RFD_statLED_Tx => usr_RFD_statLED_Tx,
993	usr_RFD_statLED_Rx => usr_RFD_statLED_Rx,
994	usr_RFD_statLED_NoLock => usr_RFD_statLED_NoLock,
995
996	-- MAP USER PORTS ABOVE THIS LINE ------------------
997
998	Bus2IP_Clk => ipif_Bus2IP_Clk,
999	Bus2IP_Reset => ipif_Bus2IP_Reset,
1000	Bus2IP_Data => ipif_Bus2IP_Data,
1001	Bus2IP_BE => ipif_Bus2IP_BE,
1002	Bus2IP_RdCE => user_Bus2IP_RdCE,
1003	Bus2IP_WrCE => user_Bus2IP_WrCE,
1004	IP2Bus_Data => user_IP2Bus_Data,
1005	IP2Bus_RdAck => user_IP2Bus_RdAck,
1006	IP2Bus_WrAck => user_IP2Bus_WrAck,
1007	IP2Bus_Error => user_IP2Bus_Error
1008	);
1009
1010	------------------------------------------
1011	-- connect internal signals
1012	------------------------------------------
1013	ipif_IP2Bus_Data <= user_IP2Bus_Data;
1014	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
1015	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
1016	ipif_IP2Bus_Error <= user_IP2Bus_Error;
1017
1018	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
1019	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
1020
1021	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/radio_controller_v2_00_a/hdl/vhdl/radio_controller.vhd

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