1 | /***************************************************************** |
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2 | * File: radio_controller.c |
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3 | * Copyright (c) 2013 Mango Communications, all rights reseved |
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4 | * Released under the WARP License |
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5 | * See http://warpproject.org/license for details |
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6 | *****************************************************************/ |
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7 | |
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8 | /** \file radio_controller.c |
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9 | |
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10 | \mainpage |
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11 | This is the driver for the radio_controller core, which implements an SPI master and digital I/O |
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12 | for controlling the MAX2829 and AD9777 ICs on the WARP Radio Board v1.4 |
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13 | |
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14 | @version 2.00.a |
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15 | @author Patrick Murphy |
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16 | @copyright (c) 2013 Mango Communications, Inc. All rights reserved.<br> |
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17 | Released under the WARP open source license (see http://warpproject.org/license) |
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18 | |
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19 | \brief Main source for radio_controller driver |
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20 | |
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21 | */ |
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22 | |
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23 | #include "radio_controller.h" |
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24 | #include "xparameters.h" |
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25 | |
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26 | #if defined XPAR_EEPROM_ONEWIRE_NUM_INSTANCES |
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27 | #include "EEPROM.h" |
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28 | #endif |
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29 | |
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30 | static u16 rc_tuningParams_24GHz_freqs[14] = { 2412, 2417, 2422, 2427, 2432, 2437, 2442, 2447, 2452, 2457, 2462, 2467, 2472, 2484}; |
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31 | static u16 rc_tuningParams_24GHz_reg3[14] = {0x00A0, 0x20A1, 0x30A1, 0x00A1, 0x20A2, 0x30A2, 0x00A2, 0x20A3, 0x30A3, 0x00A3, 0x20A4, 0x30A4, 0x00A4, 0x10A5}; |
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32 | static u16 rc_tuningParams_24GHz_reg4[14] = {0x3333, 0x0888, 0x1DDD, 0x3333, 0x0888, 0x1DDD, 0x3333, 0x0888, 0x1DDD, 0x3333, 0x0888, 0x1DDD, 0x3333, 0x2666}; |
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33 | |
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34 | static u16 rc_tuningParams_5GHz_freqs[23] = { 5180, 5200, 5220, 5240, 5260, 5280, 5300, 5320, 5500, 5520, 5540, 5560, 5580, 5600, 5620, 5640, 5660, 5680, 5700, 5745, 5765, 5785, 5805}; |
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35 | static u16 rc_tuningParams_5GHz_reg3[23] = {0x30CF, 0x0CCC, 0x00D0, 0x10D1, 0x20D2, 0x30D3, 0x00D4, 0x00D4, 0x00DC, 0x00DC, 0x10DD, 0x20DE, 0x30DF, 0x00E0, 0x00E0, 0x10E1, 0x20E2, 0x30E3, 0x00E4, 0x00E5, 0x10E6, 0x20E7, 0x30E8}; |
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36 | static u16 rc_tuningParams_5GHz_reg4[23] = {0x0CCC, 0x0000, 0x3333, 0x2666, 0x1999, 0x0CCC, 0x0000, 0x3333, 0x0000, 0x3333, 0x2666, 0x1999, 0x0CCC, 0x0000, 0x3333, 0x2666, 0x1999, 0x0CCC, 0x0000, 0x3333, 0x2666, 0x1999, 0x0CCC}; |
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37 | |
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38 | /** |
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39 | \defgroup user_functions Functions |
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40 | \brief Functions to call from user code |
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41 | \addtogroup user_functions |
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42 | |
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43 | Example: |
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44 | \code{.c} |
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45 | //Assumes user code sets RC_BASEADDR to base address of radio_controller core, as set in xparameters.h |
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46 | |
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47 | //Initialize the radio controller logic |
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48 | radio_controller_init(RC_CONTROLLER, 1, 1); |
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49 | |
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50 | \endcode |
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51 | |
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52 | @{ |
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53 | */ |
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54 | |
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55 | /** |
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56 | \brief Initializes the radio controller core and the selected MAX2829 transceivers. The selected transceivers |
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57 | are reset, configured with sane defaults and set to the Standby state. User code should call this function once |
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58 | at boot for all RF interfaces. |
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59 | \param ba Base memory address of radio_controller pcore |
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60 | \param rfSel Selects RF interface to initialize (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
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61 | \param clkDiv_SPI Clock divider for SPI serial clock (set to 3 for 160MHz bus) |
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62 | \param clkDiv_TxDelays Clock divider for Tx sequencing state machine (set to 1 for normal operation) |
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63 | \return Returns -1 if any MAX2829 indicates no PLL lock after init; otherwise returns 0 |
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64 | */ |
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65 | int radio_controller_init(u32 ba, u32 rfSel, u8 clkDiv_SPI, u8 clkDiv_TxDelays) { |
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66 | |
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67 | //Sanity check arguments |
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68 | if(((rfSel & RC_ANY_RF)==0) || (clkDiv_SPI>7) || (clkDiv_TxDelays>3)) |
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69 | return RC_INVALID_PARAM; |
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70 | |
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71 | //Radio controller init procedure: |
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72 | // -Set clock dividers for DAC & MAX2829 SPI and TxTiming state machines |
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73 | // -Reset AD7777 DAC, then configure for single ref resistor mode |
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74 | // -Set MAX2829 state to RESET |
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75 | // -Set MAX2829 state to SHDN |
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76 | // -Configure MAX2829 to sane defaults (see comments above each radio_controller_SPI_setRegBits call below) |
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77 | |
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78 | |
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79 | /************ FIXME: reg2 in user_logic.v init value is bogus *************/ |
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80 | Xil_Out32(ba+RC_SLV_REG2_OFFSET, 0); |
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81 | |
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82 | u32 rfCtrlMask = 0; |
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83 | u32 pll_lock_status; |
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84 | u32 pll_lock_wait_tries = 0; |
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85 | |
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86 | //Set sane defaults for ADC and DAC control lines |
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87 | // RSSI: CLAMP, SLEEP, HIZ all off |
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88 | // Rx ADC: DCS on (recommended for Fs>40MHz), DFS on (for 2's complement) |
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89 | Xil_Out32(ba+RC_SLV_REG8_OFFSET, (RC_REG8_MASK_RXADC_DFS | RC_REG8_MASK_RXADC_DCS)); |
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90 | |
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91 | //Initialize the AD9777 DACs |
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92 | |
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93 | // Max SPI_CLK is 15MHz; be conservative here (negligible overhead for 1 register write) |
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94 | radio_controller_setClkDiv_DAC_SPI(ba, 3); |
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95 | |
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96 | //Toggle DAC resets |
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97 | Xil_Out32(ba+RC_SLV_REG8_OFFSET, Xil_In32(ba+RC_SLV_REG8_OFFSET) | RC_REG8_MASK_DAC_RESET); |
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98 | Xil_Out32(ba+RC_SLV_REG8_OFFSET, Xil_In32(ba+RC_SLV_REG8_OFFSET) & (~RC_REG8_MASK_DAC_RESET)); |
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99 | |
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100 | //Set 1R mode (reg[0] = 0x4) |
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101 | radio_controller_DAC_SPI_write(ba, RC_REG6_DACSEL_ALL, 0x0, 0x4); |
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102 | |
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103 | //Initialize MAX2829 transceivers |
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104 | radio_controller_setClkDiv_SPI(ba, clkDiv_SPI); |
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105 | radio_controller_setClkDiv_TxDelays(ba, clkDiv_TxDelays); |
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106 | |
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107 | //Convert the user-supplied masks to the masks for the control registers |
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108 | if(rfSel & RC_RFA) rfCtrlMask |= RC_CTRLREGMASK_RFA; |
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109 | if(rfSel & RC_RFB) rfCtrlMask |= RC_CTRLREGMASK_RFB; |
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110 | if(rfSel & RC_RFC) rfCtrlMask |= RC_CTRLREGMASK_RFC; |
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111 | if(rfSel & RC_RFD) rfCtrlMask |= RC_CTRLREGMASK_RFD; |
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112 | |
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113 | radio_controller_setMode_shutdown(ba, rfCtrlMask); |
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114 | radio_controller_setMode_reset(ba, rfCtrlMask); |
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115 | usleep(1000); |
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116 | radio_controller_setMode_shutdown(ba, rfCtrlMask); |
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117 | usleep(1000); |
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118 | |
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119 | //MAX2829 reg2: |
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120 | // -MIMO mode (reg2[13]=1) |
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121 | // -Other bits set to defaults |
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122 | radio_controller_SPI_write(ba, rfSel, 2, 0x3007); |
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123 | |
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124 | //MAX2829 reg5: |
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125 | // -20MHz reference clock (reg5[3:1]=[0 0 1] (was -40MHz reference clock (reg5[3:1]=[0 1 0])) |
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126 | // -MIMO mode (reg5[13]=1) |
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127 | // -Other bits set to defaults |
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128 | radio_controller_SPI_write(ba, rfSel, 5, 0x3822); |
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129 | |
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130 | //MAX2829 reg8: |
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131 | // -RSSI output in [0.5,2.5]v (reg8[11]=1) |
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132 | // -RSSI output always on in Rx mode (reg8[10]=1) |
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133 | // -Other bits set to defaults |
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134 | radio_controller_SPI_write(ba, rfSel, 8, 0x0C25); |
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135 | |
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136 | //MAX2829 reg9: |
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137 | // -Max linearity for Tx PA driver (reg9[9:8]=[1 1] |
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138 | // -Max linearity for Tx VGA (reg9[7:6]=[1 1]) |
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139 | // -Max linearity for upconverter (reg9[3:2]=[1 1]) |
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140 | // -Tx baseband gain set to (max-3dB) (reg9[1:0]=[1 0]) |
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141 | radio_controller_SPI_write(ba, rfSel, 9, 0x03CD); |
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142 | |
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143 | |
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144 | //Finally bring the MAX2829 out of shutdown |
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145 | // The PLL should lock (LD -> 1) shortly after this call |
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146 | radio_controller_setMode_standby(ba, rfCtrlMask); |
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147 | |
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148 | pll_lock_status = 0; |
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149 | |
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150 | while(pll_lock_status != (RC_REG11_LD & rfCtrlMask)) { |
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151 | usleep(10000); |
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152 | pll_lock_status = Xil_In32(ba + RC_SLV_REG11_OFFSET) & RC_REG11_LD & rfCtrlMask; |
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153 | pll_lock_wait_tries++; |
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154 | if(pll_lock_wait_tries > 1000) { |
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155 | xil_printf("Radios didn't lock! RC stat reg: 0x%08x\n", Xil_In32(ba + RC_SLV_REG11_OFFSET)); |
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156 | return -1; |
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157 | } |
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158 | } |
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159 | // xil_printf("Radios locked after %d tries\n", pll_lock_wait_tries); |
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160 | |
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161 | |
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162 | //Set sane defaults |
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163 | radio_controller_setTxDelays(ba, 150, 0, 0, 250); |
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164 | radio_controller_setTxGainTiming(ba, 0xF, 3); |
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165 | |
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166 | return 0; |
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167 | } |
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168 | |
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169 | /** |
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170 | \brief Sets the selected RF interfaces to the Transmit state. The corresponding MAX2829s, PAs and RF switches are all |
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171 | set to the correct state for transmission. This call initiates the Tx sequencing state machine. Refer to the |
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172 | <a href="http://warp.rice.edu/trac/wiki/cores/radio_controller">radio_controller user guide</a> for more details. |
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173 | \param ba Base memory address of radio_controller pcore |
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174 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
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175 | \return Returns non-zero value if an input parameter was invalid; else returns 0 |
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176 | */ |
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177 | int radio_controller_TxEnable(u32 ba, u32 rfSel) { |
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178 | |
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179 | u32 rfCtrlMask, oldVal, newVal; |
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180 | |
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181 | if((rfSel & RC_ANY_RF)==0) |
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182 | return RC_INVALID_RFSEL; |
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183 | |
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184 | rfCtrlMask = 0; |
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185 | |
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186 | //Convert the user-supplied masks to the masks for the control registers |
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187 | if(rfSel & RC_RFA) rfCtrlMask = rfCtrlMask | RC_CTRLREGMASK_RFA; |
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188 | if(rfSel & RC_RFB) rfCtrlMask = rfCtrlMask | RC_CTRLREGMASK_RFB; |
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189 | if(rfSel & RC_RFC) rfCtrlMask = rfCtrlMask | RC_CTRLREGMASK_RFC; |
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190 | if(rfSel & RC_RFD) rfCtrlMask = rfCtrlMask | RC_CTRLREGMASK_RFD; |
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191 | |
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192 | oldVal = Xil_In32(ba + RC_SLV_REG0_OFFSET); |
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193 | |
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194 | //Force RxEn=0, SHDN=1 for radios selected by rfsel |
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195 | oldVal = (oldVal & (~(rfCtrlMask & RC_REG0_RXEN))) | (rfCtrlMask & RC_REG0_SHDN); |
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196 | |
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197 | newVal = oldVal | (rfCtrlMask & RC_REG0_TXEN); |
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198 | |
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199 | Xil_Out32(ba + RC_SLV_REG0_OFFSET, newVal); |
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200 | |
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201 | // radio_controller_setMode_standby(ba, rfCtrlMask); |
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202 | // radio_controller_setMode_Tx(ba, rfCtrlMask); |
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203 | |
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204 | return 0; |
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205 | } |
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206 | |
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207 | /** |
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208 | \brief Sets the selected RF interfaces to the Receive state. The corresponding MAX2829s and RF switches are |
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209 | set to the correct state for reception. The PAs in the selected RF interfaces are disabled. |
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210 | \param ba Base memory address of radio_controller pcore |
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211 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
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212 | \return Returns non-zero value if an input parameter was invalid; else returns 0 |
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213 | */ |
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214 | int radio_controller_RxEnable(u32 ba, u32 rfSel) { |
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215 | |
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216 | u32 rfCtrlMask, oldVal, newVal;; |
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217 | |
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218 | if((rfSel & RC_ANY_RF)==0) |
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219 | return RC_INVALID_RFSEL; |
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220 | |
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221 | rfCtrlMask = 0; |
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222 | |
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223 | //Convert the user-supplied masks to the masks for the control registers |
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224 | if(rfSel & RC_RFA) rfCtrlMask = rfCtrlMask | RC_CTRLREGMASK_RFA; |
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225 | if(rfSel & RC_RFB) rfCtrlMask = rfCtrlMask | RC_CTRLREGMASK_RFB; |
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226 | if(rfSel & RC_RFC) rfCtrlMask = rfCtrlMask | RC_CTRLREGMASK_RFC; |
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227 | if(rfSel & RC_RFD) rfCtrlMask = rfCtrlMask | RC_CTRLREGMASK_RFD; |
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228 | |
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229 | oldVal = Xil_In32(ba + RC_SLV_REG0_OFFSET); |
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230 | |
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231 | //Force TxEn=0, SHDN=1 for radios selected by rfsel |
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232 | oldVal = (oldVal & (~(rfCtrlMask & RC_REG0_TXEN))) | (rfCtrlMask & RC_REG0_SHDN); |
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233 | |
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234 | newVal = oldVal | (rfCtrlMask & RC_REG0_RXEN); |
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235 | |
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236 | Xil_Out32(ba + RC_SLV_REG0_OFFSET, newVal); |
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237 | |
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238 | // radio_controller_setMode_standby(ba, rfCtrlMask); |
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239 | // radio_controller_setMode_Rx(ba, rfCtrlMask); |
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240 | |
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241 | return 0; |
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242 | } |
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243 | |
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244 | /** |
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245 | \brief Sets the selected RF interfaces to the Standby state (Tx and Rx disabled). The corresponding MAX2829s and PAs are |
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246 | set to the correct state for standby. |
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247 | \param ba Base memory address of radio_controller pcore |
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248 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
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249 | \return Returns non-zero value if an input parameter was invalid; else returns 0 |
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250 | */ |
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251 | int radio_controller_TxRxDisable(u32 ba, u32 rfSel) { |
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252 | |
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253 | u32 rfCtrlMask = 0; |
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254 | |
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255 | if((rfSel & RC_ANY_RF)==0) |
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256 | return RC_INVALID_RFSEL; |
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257 | |
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258 | //Convert the user-supplied masks to the masks for the control registers |
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259 | if(rfSel & RC_RFA) rfCtrlMask |= RC_CTRLREGMASK_RFA; |
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260 | if(rfSel & RC_RFB) rfCtrlMask |= RC_CTRLREGMASK_RFB; |
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261 | if(rfSel & RC_RFC) rfCtrlMask |= RC_CTRLREGMASK_RFC; |
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262 | if(rfSel & RC_RFD) rfCtrlMask |= RC_CTRLREGMASK_RFD; |
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263 | |
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264 | radio_controller_setMode_standby(ba, rfCtrlMask); |
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265 | |
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266 | return 0; |
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267 | } |
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268 | |
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269 | /** |
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270 | \brief Sets the selected RF interfaces to the Standby state (Tx and Rx disabled). The corresponding MAX2829s and PAs are |
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271 | set to the correct state for standby. |
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272 | \param ba Base memory address of radio_controller pcore |
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273 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
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274 | \param bandSel Selects the 2.4GHz or 5GHz band; must be RC_24GHZ or RC_5GHZ |
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275 | \param chanNum New center frequency channel number, in [1,14] for 2.4GHz or [1,23] for 5GHz. The channel numbers |
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276 | and corresponding center frequencies are listed in the table below. |
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277 | \return Returns non-zero value if an input parameter was invalid; else returns 0 |
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278 | |
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279 | 2.4GHz <br> Chan | Freq <br> (MHz) | | 5GHz <br> Chan | Freq <br> (MHz) |
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280 | --- | ----- | - | --- | ----- |
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281 | 1 | 2412 | | 1 | 5180 |
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282 | 2 | 2417 | | 2 | 5200 |
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283 | 3 | 2422 | | 3 | 5220 |
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284 | 4 | 2427 | | 4 | 5240 |
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285 | 5 | 2432 | | 5 | 5260 |
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286 | 6 | 2437 | | 6 | 5280 |
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287 | 7 | 2442 | | 7 | 5300 |
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288 | 8 | 2447 | | 8 | 5320 |
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289 | 9 | 2452 | | 9 | 5500 |
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290 | 10 | 2457 | | 10 | 5520 |
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291 | 11 | 2462 | | 11 | 5540 |
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292 | 12 | 2467 | | 12 | 5560 |
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293 | 13 | 2472 | | 13 | 5580 |
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294 | 14 | 2484 | | 14 | 5600 |
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295 | - | - | | 15 | 5620 |
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296 | - | - | | 16 | 5640 |
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297 | - | - | | 17 | 5660 |
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298 | - | - | | 18 | 5680 |
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299 | - | - | | 19 | 5700 |
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300 | - | - | | 20 | 5745 |
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301 | - | - | | 21 | 5765 |
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302 | - | - | | 22 | 5785 |
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303 | - | - | | 23 | 5805 |
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304 | */ |
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305 | int radio_controller_setCenterFrequency(u32 ba, u32 rfSel, u8 bandSel, u8 chanNum) { |
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306 | |
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307 | if((bandSel == RC_24GHZ) && (chanNum >= 1) && (chanNum <= 14) && (rfSel & RC_ANY_RF)){ //14 valid 2.4GHz channels |
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308 | //MAX2829 tuning process for 2.4GHz channels: |
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309 | // -Set reg5[0] to 0 (selects 2.4GHz) |
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310 | // -Set reg3, reg4 with PLL tuning params |
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311 | |
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312 | radio_controller_SPI_setRegBits(ba, rfSel, 5, 0x1, 0x0); |
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313 | |
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314 | //Write the PLL parameters |
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315 | radio_controller_SPI_write(ba, rfSel, 3, rc_tuningParams_24GHz_reg3[chanNum-1]); |
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316 | radio_controller_SPI_write(ba, rfSel, 4, rc_tuningParams_24GHz_reg4[chanNum-1]); |
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317 | |
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318 | return(rc_tuningParams_24GHz_freqs[chanNum-1]); |
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319 | } |
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320 | |
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321 | if((bandSel == RC_5GHZ) && (chanNum >= 1) && (chanNum <= 23) && (rfSel & RC_ANY_RF)) { //23 valid 5GHz channels |
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322 | //MAX2829 tuning process for 5GHz channels: |
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323 | //(Assumes default config of 5GHz sub-band tuning via FSM; see MAX2829 datasheet for details) |
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324 | // -Set: |
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325 | // -reg5[0] to 1 (selects 5GHz) |
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326 | // -reg5[6] based on selected freq (0:4.9-5.35GHz, 1:5.47-5.875GHz) |
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327 | // -Set reg3, reg4 with PLL tuning params |
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328 | |
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329 | if(chanNum<=8) |
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330 | radio_controller_SPI_setRegBits(ba, rfSel, 5, 0x41, 0x01); |
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331 | else |
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332 | radio_controller_SPI_setRegBits(ba, rfSel, 5, 0x41, 0x41); |
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333 | |
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334 | //Reset the band select FSM |
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335 | radio_controller_SPI_setRegBits(ba, rfSel, 5, 0x80, 0x00); |
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336 | |
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337 | //Write the PLL parameters |
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338 | radio_controller_SPI_write(ba, rfSel, 3, rc_tuningParams_5GHz_reg3[chanNum-1]); |
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339 | radio_controller_SPI_write(ba, rfSel, 4, rc_tuningParams_5GHz_reg4[chanNum-1]); |
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340 | |
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341 | //Start the band select FSM |
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342 | radio_controller_SPI_setRegBits(ba, rfSel, 5, 0x80, 0x80); |
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343 | |
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344 | return(rc_tuningParams_5GHz_freqs[chanNum-1]); |
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345 | } |
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346 | |
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347 | //Some input param was invalid if we get here, so return an invalid frequency |
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348 | return RC_INVALID_PARAM; |
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349 | } |
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350 | |
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351 | /** |
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352 | \brief Reads the radio controller "mirror" register corresponding to the MAX2829 register at regAddr |
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353 | \param ba Base memory address of radio_controller pcore |
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354 | \param rfSel Selects RF interface to read (must be one of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
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355 | \param regAddr Register address to read, in [0x0,0xC] |
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356 | \return Returns 255 if input parameters are invalid; otherwise returns 14-bit register value |
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357 | */ |
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358 | u16 radio_controller_SPI_read(u32 ba, u32 rfSel, u8 regAddr) { |
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359 | if(((rfSel & RC_ANY_RF)==0) || (regAddr>0xC)) |
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360 | return 255; //impossible value for 14-bit registers; use for error checking |
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361 | |
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362 | //Use Xil_In32 to grab 16LSB of each register (Xil_In16 reads 16MSB of 32-bit register when address is aligned to 4 bytes) |
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363 | if(rfSel & RC_RFA) |
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364 | return (u16)(0xFFFF & Xil_In32(ba + RC_SPI_MIRRORREGS_RFA_BASEADDR + 4*regAddr)); |
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365 | |
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366 | if(rfSel & RC_RFB) |
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367 | return (u16)(0xFFFF & Xil_In32(ba + RC_SPI_MIRRORREGS_RFB_BASEADDR + 4*regAddr)); |
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368 | |
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369 | if(rfSel & RC_RFC) |
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370 | return (u16)(0xFFFF & Xil_In32(ba + RC_SPI_MIRRORREGS_RFC_BASEADDR + 4*regAddr)); |
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371 | |
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372 | if(rfSel & RC_RFD) |
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373 | return (u16)(0xFFFF & Xil_In32(ba + RC_SPI_MIRRORREGS_RFD_BASEADDR + 4*regAddr)); |
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374 | |
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375 | //Can't get here, but return error anyway so compiler doesn't complain |
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376 | return 254; |
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377 | } |
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378 | |
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379 | /** |
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380 | \brief Sets specific bits in a single register in selected MAX2829s |
---|
381 | \param ba Base memory address of radio_controller pcore |
---|
382 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
383 | \param regAddr Register address to write, in [0x0,0xC] |
---|
384 | \param regDataMask 14-bit mask of bits to affect (1 in mask selects bit for writing) |
---|
385 | \param regData 14-bit value to set; only bits with 1 in regDataMask are used |
---|
386 | \return Returns non-zero if input parameters are invalid; otherwise returns 0 |
---|
387 | */ |
---|
388 | int radio_controller_SPI_setRegBits(u32 ba, u32 rfSel, u8 regAddr, u16 regDataMask, u16 regData) { |
---|
389 | u16 curRegData; |
---|
390 | u16 newRegData; |
---|
391 | |
---|
392 | if(((rfSel & RC_ANY_RF)==0) || (regAddr>13)) |
---|
393 | return RC_INVALID_RFSEL; |
---|
394 | |
---|
395 | if(rfSel & RC_RFA) { |
---|
396 | curRegData = radio_controller_SPI_read(ba, RC_RFA, regAddr); |
---|
397 | newRegData = ((curRegData & ~regDataMask) | (regData & regDataMask)); |
---|
398 | radio_controller_SPI_write(ba, RC_RFA, regAddr, newRegData); |
---|
399 | } |
---|
400 | if(rfSel & RC_RFB) { |
---|
401 | curRegData = radio_controller_SPI_read(ba, RC_RFB, regAddr); |
---|
402 | newRegData = ((curRegData & ~regDataMask) | (regData & regDataMask)); |
---|
403 | radio_controller_SPI_write(ba, RC_RFB, regAddr, newRegData); |
---|
404 | } |
---|
405 | if(rfSel & RC_RFC) { |
---|
406 | curRegData = radio_controller_SPI_read(ba, RC_RFC, regAddr); |
---|
407 | newRegData = ((curRegData & ~regDataMask) | (regData & regDataMask)); |
---|
408 | radio_controller_SPI_write(ba, RC_RFC, regAddr, newRegData); |
---|
409 | } |
---|
410 | if(rfSel & RC_RFD) { |
---|
411 | curRegData = radio_controller_SPI_read(ba, RC_RFD, regAddr); |
---|
412 | newRegData = ((curRegData & ~regDataMask) | (regData & regDataMask)); |
---|
413 | radio_controller_SPI_write(ba, RC_RFD, regAddr, newRegData); |
---|
414 | } |
---|
415 | |
---|
416 | return 0; |
---|
417 | } |
---|
418 | |
---|
419 | /** |
---|
420 | \brief Sets state of RXHP pin on selected MAX2829s. This function only affects state if the RXHP control |
---|
421 | source is set to software on the selected RF interfaces. |
---|
422 | \param ba Base memory address of radio_controller pcore |
---|
423 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
424 | \param mode RXHP is asserted if mode=RC_RXHP_ON, else RXHP is deasserted |
---|
425 | \return Returns non-zero if input parameters are invalid; otherwise returns 0 |
---|
426 | */ |
---|
427 | int radio_controller_setRxHP(u32 ba, u32 rfSel, u8 mode) { |
---|
428 | //Sanity check inputs |
---|
429 | if((rfSel & RC_ANY_RF) == 0) |
---|
430 | return RC_INVALID_RFSEL; |
---|
431 | |
---|
432 | if(mode > 1) |
---|
433 | return RC_INVALID_PARAM; |
---|
434 | |
---|
435 | u32 rfCtrlMask = 0; |
---|
436 | |
---|
437 | //Convert the user-supplied masks to the masks for the control registers |
---|
438 | if(rfSel & RC_RFA) rfCtrlMask |= RC_CTRLREGMASK_RFA; |
---|
439 | if(rfSel & RC_RFB) rfCtrlMask |= RC_CTRLREGMASK_RFB; |
---|
440 | if(rfSel & RC_RFC) rfCtrlMask |= RC_CTRLREGMASK_RFC; |
---|
441 | if(rfSel & RC_RFD) rfCtrlMask |= RC_CTRLREGMASK_RFD; |
---|
442 | |
---|
443 | u32 curRegVal, newRegVal; |
---|
444 | |
---|
445 | curRegVal = Xil_In32(ba+RC_SLV_REG0_OFFSET); |
---|
446 | |
---|
447 | if(mode == RC_RXHP_ON) { |
---|
448 | //Assert RxHP bits in reg0; drives 1 to corresponding RxHP pin on MAX2829 |
---|
449 | newRegVal = curRegVal | (RC_REG0_RXHP & rfCtrlMask); |
---|
450 | } else { |
---|
451 | newRegVal = curRegVal & (~(RC_REG0_RXHP & rfCtrlMask)); |
---|
452 | } |
---|
453 | |
---|
454 | Xil_Out32(ba+RC_SLV_REG0_OFFSET, newRegVal); |
---|
455 | |
---|
456 | return 0; |
---|
457 | } |
---|
458 | |
---|
459 | /** |
---|
460 | \brief Selects between register or hardware control for the various radio control signals on the selected RF interfaces. |
---|
461 | \param ba Base memory address of radio_controller pcore |
---|
462 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
463 | \param ctrlSrcMask Specifies which control signals should have new control source; OR'd combination of [RC_REG0_TXEN_CTRLSRC, RC_REG0_RXEN_CTRLSRC, RC_REG0_RXHP_CTRLSRC, RC_REG0_SHDN_CTRLSRC] |
---|
464 | \param ctrlSrc Selects register (from C code) or hardware (usr_ ports) control; must be RC_CTRLSRC_REG or RC_CTRLSRC_HW |
---|
465 | \return Returns non-zero if input parameters are invalid; otherwise returns 0 |
---|
466 | */ |
---|
467 | int radio_controller_setCtrlSource(u32 ba, u32 rfSel, u32 ctrlSrcMask, u8 ctrlSrc) { |
---|
468 | |
---|
469 | //Sanity check inputs |
---|
470 | if((rfSel & RC_ANY_RF) == 0) |
---|
471 | return RC_INVALID_RFSEL; |
---|
472 | |
---|
473 | if((ctrlSrcMask & RC_REG0_ALL_CTRLSRC) == 0) |
---|
474 | return RC_INVALID_PARAM; |
---|
475 | |
---|
476 | u32 rfCtrlMask = 0; |
---|
477 | |
---|
478 | //Convert the user-supplied masks to the masks for the control registers |
---|
479 | if(rfSel & RC_RFA) rfCtrlMask |= RC_CTRLREGMASK_RFA; |
---|
480 | if(rfSel & RC_RFB) rfCtrlMask |= RC_CTRLREGMASK_RFB; |
---|
481 | if(rfSel & RC_RFC) rfCtrlMask |= RC_CTRLREGMASK_RFC; |
---|
482 | if(rfSel & RC_RFD) rfCtrlMask |= RC_CTRLREGMASK_RFD; |
---|
483 | |
---|
484 | u32 curRegVal, newRegVal; |
---|
485 | |
---|
486 | curRegVal = Xil_In32(ba+RC_SLV_REG0_OFFSET); |
---|
487 | |
---|
488 | if(ctrlSrc == RC_CTRLSRC_HW) { |
---|
489 | //Hardware control via usr_* ports enabled by 1 in reg0 ctrlSrc bits |
---|
490 | newRegVal = curRegVal | (ctrlSrcMask & rfCtrlMask & RC_REG0_ALL_CTRLSRC); |
---|
491 | } else { |
---|
492 | //Software control via writes to reg0 (RC_REG0_TXEN, RC_REG0_RXEN, etc.) |
---|
493 | newRegVal = curRegVal & (~(ctrlSrcMask & rfCtrlMask & RC_REG0_ALL_CTRLSRC)); |
---|
494 | } |
---|
495 | |
---|
496 | Xil_Out32(ba+RC_SLV_REG0_OFFSET, newRegVal); |
---|
497 | |
---|
498 | return 0; |
---|
499 | } |
---|
500 | |
---|
501 | /** |
---|
502 | \brief Sets the final Tx VGA gain set by the Tx sequencing state machine for the selected RF interfaces |
---|
503 | \param ba Base memory address of radio_controller pcore |
---|
504 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
505 | \param gainTarget Tx VGA gain setting, in [0,63] |
---|
506 | \return Returns non-zero if input parameters are invalid; otherwise returns 0 |
---|
507 | */ |
---|
508 | int radio_controller_setTxGainTarget(u32 ba, u32 rfSel, u8 gainTarget) { |
---|
509 | //Sanity check inputs |
---|
510 | if(((rfSel & RC_ANY_RF)==0)) |
---|
511 | return RC_INVALID_RFSEL; |
---|
512 | |
---|
513 | u32 regVal; |
---|
514 | |
---|
515 | regVal = Xil_In32(ba+RC_SLV_REG2_OFFSET); |
---|
516 | |
---|
517 | if(rfSel & RC_RFA) |
---|
518 | regVal = (regVal & ~(0x0000003F)) | ((gainTarget<< 0) & 0x0000003F); |
---|
519 | if(rfSel & RC_RFB) |
---|
520 | regVal = (regVal & ~(0x00003F00)) | ((gainTarget<< 8) & 0x00003F00); |
---|
521 | if(rfSel & RC_RFC) |
---|
522 | regVal = (regVal & ~(0x003F0000)) | ((gainTarget<<16) & 0x003F0000); |
---|
523 | if(rfSel & RC_RFD) |
---|
524 | regVal = (regVal & ~(0x3F000000)) | ((gainTarget<<24) & 0x3F000000); |
---|
525 | |
---|
526 | Xil_Out32(ba+RC_SLV_REG2_OFFSET, regVal); |
---|
527 | |
---|
528 | return 0; |
---|
529 | } |
---|
530 | |
---|
531 | /** |
---|
532 | \brief Sets the control source for Tx gains in the selected RF interfaces |
---|
533 | \param ba Base memory address of radio_controller pcore |
---|
534 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
535 | \param gainSrc must be one of [RC_GAINSRC_SPI, RC_GAINSRC_REG, RC_GAINSRC_HW], for SPI control, register control or hardware (usr_RFx_TxGain port) control |
---|
536 | \return Returns non-zero if input parameters are invalid; otherwise returns 0 |
---|
537 | */ |
---|
538 | int radio_controller_setTxGainSource(u32 ba, u32 rfSel, u8 gainSrc) { |
---|
539 | |
---|
540 | //Sanity check inputs |
---|
541 | if(((rfSel & RC_ANY_RF)==0)) |
---|
542 | return RC_INVALID_RFSEL; |
---|
543 | |
---|
544 | u32 rfCtrlMask = 0; |
---|
545 | u32 curRegVal, newRegVal; |
---|
546 | |
---|
547 | //Convert the user-supplied masks to the masks for the control registers |
---|
548 | if(rfSel & RC_RFA) rfCtrlMask |= RC_CTRLREGMASK_RFA; |
---|
549 | if(rfSel & RC_RFB) rfCtrlMask |= RC_CTRLREGMASK_RFB; |
---|
550 | if(rfSel & RC_RFC) rfCtrlMask |= RC_CTRLREGMASK_RFC; |
---|
551 | if(rfSel & RC_RFD) rfCtrlMask |= RC_CTRLREGMASK_RFD; |
---|
552 | |
---|
553 | if(gainSrc == RC_GAINSRC_SPI) { |
---|
554 | //Configure MAX2829 for Tx gain control via SPI |
---|
555 | radio_controller_setRadioParam(ba, rfSel, RC_PARAMID_TXGAINS_SPI_CTRL_EN, 1); |
---|
556 | return 0; |
---|
557 | } |
---|
558 | else if(gainSrc == RC_GAINSRC_HW) { |
---|
559 | //Disable SPI Tx gain control in MAX2829 |
---|
560 | radio_controller_setRadioParam(ba, rfSel, RC_PARAMID_TXGAINS_SPI_CTRL_EN, 0); |
---|
561 | |
---|
562 | //Configure radio controller for Tx gain target from usr_ ports in logic |
---|
563 | curRegVal = Xil_In32(ba+RC_SLV_REG2_OFFSET); |
---|
564 | newRegVal = (curRegVal | (rfCtrlMask & RC_REG2_TXGAIN_CTRLSRC)); |
---|
565 | Xil_Out32(ba+RC_SLV_REG2_OFFSET, newRegVal); |
---|
566 | return 0; |
---|
567 | } |
---|
568 | else if(gainSrc == RC_GAINSRC_REG) { |
---|
569 | //Disable SPI Tx gain control in MAX2829 |
---|
570 | radio_controller_setRadioParam(ba, rfSel, RC_PARAMID_TXGAINS_SPI_CTRL_EN, 0); |
---|
571 | |
---|
572 | //Configure radio controller for Tx gain target from registers |
---|
573 | curRegVal = Xil_In32(ba+RC_SLV_REG2_OFFSET); |
---|
574 | newRegVal = (curRegVal & ~(rfCtrlMask & RC_REG2_TXGAIN_CTRLSRC)); |
---|
575 | Xil_Out32(ba+RC_SLV_REG2_OFFSET, newRegVal); |
---|
576 | return 0; |
---|
577 | } |
---|
578 | |
---|
579 | //gainSrc must have been invalid if we get here |
---|
580 | return RC_INVALID_PARAM; |
---|
581 | } |
---|
582 | |
---|
583 | /** |
---|
584 | \brief Sets the control source for Rx gains in the selected RF interfaces. Note that when hardware control is selected, the corresponding |
---|
585 | RXHP should also be set for hardware control using radio_controller_setCtrlSource(). |
---|
586 | \param ba Base memory address of radio_controller pcore |
---|
587 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
588 | \param gainSrc must be one of [RC_GAINSRC_SPI, RC_GAINSRC_REG, RC_GAINSRC_HW], for SPI control, register control or hardware (usr_RFx_TxGain port) control |
---|
589 | \return Returns non-zero if input parameters are invalid; otherwise returns 0 |
---|
590 | */ |
---|
591 | int radio_controller_setRxGainSource(u32 ba, u32 rfSel, u8 gainSrc) { |
---|
592 | //Sanity check inputs |
---|
593 | if(((rfSel & RC_ANY_RF)==0)) |
---|
594 | return RC_INVALID_RFSEL; |
---|
595 | |
---|
596 | u32 rfCtrlMask = 0; |
---|
597 | u32 curRegVal, newRegVal; |
---|
598 | |
---|
599 | //Convert the user-supplied masks to the masks for the control registers |
---|
600 | if(rfSel & RC_RFA) rfCtrlMask |= RC_CTRLREGMASK_RFA; |
---|
601 | if(rfSel & RC_RFB) rfCtrlMask |= RC_CTRLREGMASK_RFB; |
---|
602 | if(rfSel & RC_RFC) rfCtrlMask |= RC_CTRLREGMASK_RFC; |
---|
603 | if(rfSel & RC_RFD) rfCtrlMask |= RC_CTRLREGMASK_RFD; |
---|
604 | |
---|
605 | if(gainSrc == RC_GAINSRC_SPI) { |
---|
606 | //Configure MAX2829 for Tx gain control via SPI |
---|
607 | radio_controller_setRadioParam(ba, rfSel, RC_PARAMID_RXGAINS_SPI_CTRL_EN, 1); |
---|
608 | return 0; |
---|
609 | } |
---|
610 | else if(gainSrc == RC_GAINSRC_REG) { |
---|
611 | //Disable SPI Rx gain control in MAX2829 |
---|
612 | radio_controller_setRadioParam(ba, rfSel, RC_PARAMID_RXGAINS_SPI_CTRL_EN, 0); |
---|
613 | |
---|
614 | //Configure radio controller for Rx gains from registers |
---|
615 | curRegVal = Xil_In32(ba+RC_SLV_REG3_OFFSET); |
---|
616 | newRegVal = (curRegVal & ~(rfCtrlMask & RC_REG3_RXGAIN_CTRLSRC)); |
---|
617 | Xil_Out32(ba+RC_SLV_REG3_OFFSET, newRegVal); |
---|
618 | return 0; |
---|
619 | } |
---|
620 | else if(gainSrc == RC_GAINSRC_HW) { |
---|
621 | //Disable SPI Rx gain control in MAX2829 |
---|
622 | radio_controller_setRadioParam(ba, rfSel, RC_PARAMID_RXGAINS_SPI_CTRL_EN, 0); |
---|
623 | |
---|
624 | //Configure radio controller for Tx gains from usr_ ports in logic |
---|
625 | curRegVal = Xil_In32(ba+RC_SLV_REG3_OFFSET); |
---|
626 | newRegVal = (curRegVal | (rfCtrlMask & RC_REG3_RXGAIN_CTRLSRC)); |
---|
627 | Xil_Out32(ba+RC_SLV_REG3_OFFSET, newRegVal); |
---|
628 | return 0; |
---|
629 | } |
---|
630 | |
---|
631 | //gainSrc must have been invalid if we get here |
---|
632 | return RC_INVALID_PARAM; |
---|
633 | |
---|
634 | } |
---|
635 | |
---|
636 | /** |
---|
637 | \brief Sets a MAX2829 parameter via a SPI register write. |
---|
638 | \param ba Base memory address of radio_controller pcore |
---|
639 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
640 | \param paramID Parameter ID to update. Must be valid RC_PARAMID_* (see table below) |
---|
641 | \param paramVal Parameter value to set. Valid values depend on the selected parameter (see table below) |
---|
642 | \return Returns non-zero if input parameters are invalid; otherwise returns 0 |
---|
643 | |
---|
644 | Parameter ID | Description | Parameter Values |
---|
645 | ------------ | ----------- | ---------------- |
---|
646 | RC_PARAMID_RXGAIN_RF | Rx RF gain value | 1: 0dB<br>2: 15dB<br>3: 30dB |
---|
647 | RC_PARAMID_RXGAIN_BB | Rx baseband gain value | [0,31]: approx [0,63]dB |
---|
648 | RC_PARAMID_TXGAIN_RF | Tx RF gain value | [0,63]: approx [0,31]dB |
---|
649 | RC_PARAMID_TXGAIN_BB | Tx baseband gain value | 0: 0<br>1: -1.5dB<br>2: -3dB<br>3: -5dB |
---|
650 | RC_PARAMID_TXLPF_BW | Tx low pass filter corner frequency<br> (Tx bandwidth is 2x corner frequency) | 1: 12MHz<br>2: 18MHz<br>3: 24MHz |
---|
651 | RC_PARAMID_RXLPF_BW | Rx low pass filter corner frequency<br> (Rx bandwidth is 2x corner frequency) | 0: 7.5MHz<br>1: 9.5MHz<br>2: 14MHz<br>3: 18MHz |
---|
652 | RC_PARAMID_RXLPF_BW_FINE | Rx low pass filter corner fine adjustment | 0: 90%<br>1: 95%<br>2: 100%<br>3: 105%<br>4: 110% |
---|
653 | RC_PARAMID_RXHPF_HIGH_CUTOFF_EN | Set corner frequency for Rx high pass filter when RXHP=0| 0: Low corner (100Hz)<br>1: High corner (30kHz) |
---|
654 | RC_PARAMID_RSSI_HIGH_BW_EN | En/disable high bandwidth RSSI signal | 0: Disable high bandwidth RSSI<br>1: Enable high bandwidth RSSI |
---|
655 | RC_PARAMID_TXLINEARITY_PADRIVER | Linearity of Tx PA driver circuit | [0,3]: [min,max] linearity |
---|
656 | RC_PARAMID_TXLINEARITY_VGA | Linearity of Tx VGA circuit | [0,3]: [min,max] linearity |
---|
657 | RC_PARAMID_TXLINEARITY_UPCONV | Linearity of Tx upconverter circuit | [0,3]: [min,max] linearity |
---|
658 | RC_PARAMID_TXGAINS_SPI_CTRL_EN | En/disable SPI control of Tx gains | 0: Disable SPI control<br>1: Enable SPI control |
---|
659 | RC_PARAMID_RXGAINS_SPI_CTRL_EN | En/disable SPI control of Rx gains | 0: Disable SPI control<br>1: Enable SPI control |
---|
660 | |
---|
661 | */ |
---|
662 | int radio_controller_setRadioParam(u32 ba, u32 rfSel, u32 paramID, u32 paramVal) { |
---|
663 | u16 curRegData; |
---|
664 | u16 newRegData; |
---|
665 | |
---|
666 | u16 x, y; |
---|
667 | |
---|
668 | //Sanity check inputs |
---|
669 | if(((rfSel & RC_ANY_RF)==0)) |
---|
670 | return RC_INVALID_RFSEL; |
---|
671 | |
---|
672 | |
---|
673 | switch(paramID) { |
---|
674 | #ifdef RC_INCLUDED_PARAMS_GAIN_CTRL |
---|
675 | case RC_PARAMID_TXGAINS_SPI_CTRL_EN: |
---|
676 | //reg9[10]: 0=B port controls Tx VGA gain, 1=SPI regC[5:0] controls Tx VGA gain |
---|
677 | if(paramVal > 1) return RC_INVALID_PARAM; |
---|
678 | x = paramVal ? 0x0400 : 0x0000; |
---|
679 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x9, 0x0400, x); |
---|
680 | break; |
---|
681 | case RC_PARAMID_RXGAINS_SPI_CTRL_EN: |
---|
682 | //reg8[12]: 0=B port controls Rx gains, 1=SPI regB[6:0] controls Rx gains |
---|
683 | if(paramVal > 1) return RC_INVALID_PARAM; |
---|
684 | x = paramVal ? 0x1000 : 0x0000; |
---|
685 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x8, 0x1000, x); |
---|
686 | break; |
---|
687 | case RC_PARAMID_RXGAIN_RF: |
---|
688 | //regB[6:5] sets LNA gain (but only if SPI control for Rx gains is enabled) |
---|
689 | if(paramVal > 3) return RC_INVALID_PARAM; |
---|
690 | x = (paramVal & 0x3)<<5; |
---|
691 | return radio_controller_SPI_setRegBits(ba, rfSel, 0xB, 0x0060, x); |
---|
692 | case RC_PARAMID_RXGAIN_BB: |
---|
693 | //regB[4:0] sets Rx VGA gain (but only if SPI control for Rx gains is enabled) |
---|
694 | if(paramVal > 31) return RC_INVALID_PARAM; |
---|
695 | x = (paramVal & 0x1F); |
---|
696 | return radio_controller_SPI_setRegBits(ba, rfSel, 0xB, 0x001F, x); |
---|
697 | break; |
---|
698 | case RC_PARAMID_TXGAIN_RF: |
---|
699 | //regC[5:0] sets Tx RF VGA gain (but only if SPI control for Tx gains is enabled) |
---|
700 | if(paramVal > 63) return RC_INVALID_PARAM; |
---|
701 | x = (paramVal & 0x3F); |
---|
702 | return radio_controller_SPI_setRegBits(ba, rfSel, 0xC, 0x003F, x); |
---|
703 | break; |
---|
704 | case RC_PARAMID_TXGAIN_BB: |
---|
705 | //reg9[1:0] sets Tx BB gain (Tx BB gain always set via SPI) |
---|
706 | if(paramVal > 3) return RC_INVALID_PARAM; |
---|
707 | x = (paramVal & 0x3); |
---|
708 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x9, 0x0003, x); |
---|
709 | break; |
---|
710 | #endif //RC_INCLUDED_PARAMS_GAIN_CTRL |
---|
711 | |
---|
712 | #ifdef RC_INCLUDED_PARAMS_FILTS |
---|
713 | case RC_PARAMID_TXLPF_BW: |
---|
714 | //reg7[6:5]: 00=undefined, 01=12MHz, 10=18MHz, 11=24MHz |
---|
715 | if(paramVal == 0 || paramVal > 3) return RC_INVALID_PARAM; |
---|
716 | x = (paramVal&0x3)<<5; |
---|
717 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x7, 0x0060, x); |
---|
718 | break; |
---|
719 | case RC_PARAMID_RXLPF_BW: |
---|
720 | //reg7[4:3]: 00=7.5MHz, 01=9.5MHz, 10=14MHz, 11=18MHz |
---|
721 | if(paramVal > 3) return RC_INVALID_PARAM; |
---|
722 | x = (paramVal&0x3)<<3; |
---|
723 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x7, 0x0018, x); |
---|
724 | break; |
---|
725 | case RC_PARAMID_RXLPF_BW_FINE: |
---|
726 | //reg7[2:0]: 000=90%, 001=95%, 010=100%, 011=105%, 100=110% |
---|
727 | if(paramVal > 4) return RC_INVALID_PARAM; |
---|
728 | x = (paramVal&0x7); |
---|
729 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x7, 0x0007, x); |
---|
730 | break; |
---|
731 | case RC_PARAMID_RXHPF_HIGH_CUTOFF_EN: |
---|
732 | //reg8[2]: HPF corner freq when RxHP=0; 0=100Hz, 1=30kHz |
---|
733 | if(paramVal > 1) return RC_INVALID_PARAM; |
---|
734 | x = paramVal ? 0x0004 : 0x0000; |
---|
735 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x8, 0x0004, x); |
---|
736 | break; |
---|
737 | #endif //RC_INCLUDED_PARAMS_FILTS |
---|
738 | |
---|
739 | #ifdef RC_INCLUDED_PARAMS_MISC |
---|
740 | case RC_PARAMID_RSSI_HIGH_BW_EN: |
---|
741 | //reg7[11]: 0=2MHz RSSI BW, 1=6MHZ RSSI BW |
---|
742 | if(paramVal > 1) return RC_INVALID_PARAM; |
---|
743 | x = paramVal ? 0x0800 : 0x0000; |
---|
744 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x7, 0x0800, x); |
---|
745 | break; |
---|
746 | case RC_PARAMID_TXLINEARITY_PADRIVER: |
---|
747 | //reg9[9:8]: [0,1,2,3]=[50%,63%,78%,100%] current; higher current -> more linear |
---|
748 | if(paramVal > 3) return RC_INVALID_PARAM; |
---|
749 | x = (paramVal&0x3)<<8; |
---|
750 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x9, 0x0300, x); |
---|
751 | break; |
---|
752 | case RC_PARAMID_TXLINEARITY_VGA: |
---|
753 | //reg9[7:6]: [0,1,2,3]=[50%,63%,78%,100%] current; higher current -> more linear |
---|
754 | if(paramVal > 3) return RC_INVALID_PARAM; |
---|
755 | x = (paramVal&0x3)<<6; |
---|
756 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x9, 0x00C0, x); |
---|
757 | break; |
---|
758 | case RC_PARAMID_TXLINEARITY_UPCONV: |
---|
759 | //reg9[3:2]: [0,1,2,3]=[50%,63%,78%,100%] current; higher current -> more linear |
---|
760 | if(paramVal > 3) return RC_INVALID_PARAM; |
---|
761 | x = (paramVal&0x3)<<2; |
---|
762 | return radio_controller_SPI_setRegBits(ba, rfSel, 0x9, 0x000C, x); |
---|
763 | break; |
---|
764 | #endif //RC_INCLUDED_PARAMS_MISC |
---|
765 | default: |
---|
766 | //Either no paramters were #ifdef'd in, or user supplied invalid paramID |
---|
767 | return RC_INVALID_PARAMID; |
---|
768 | break; |
---|
769 | } |
---|
770 | |
---|
771 | return 0; |
---|
772 | } |
---|
773 | |
---|
774 | /** |
---|
775 | \brief Reads the TxDCO calibration values from the EEPROM and writes the values to the DACs of the selected RF interface. This function |
---|
776 | requires the eeprom_onewire core. |
---|
777 | \param rc_ba Base memory address of radio_controller core |
---|
778 | \param eeprom_ba Base memory address of eeprom_onewire core |
---|
779 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
780 | \return Returns non-zero if w3_ad_controller or w3_iic_eeprom core is not found; otherwise returns 0 |
---|
781 | */ |
---|
782 | int radio_controller_apply_TxDCO_calibration(u32 rc_ba, u32 eeprom_ba, u32 rfSel) { |
---|
783 | #ifdef XPAR_EEPROM_ONEWIRE_NUM_INSTANCES |
---|
784 | int i; |
---|
785 | static u32 rfSel_ALL[4] = {RC_RFA, RC_RFB, RC_RFC, RC_RFD}; |
---|
786 | u32 cur_rfSel; |
---|
787 | |
---|
788 | int eepromStatus = 0; |
---|
789 | short calReadback = 0; |
---|
790 | signed short best_I, best_Q; |
---|
791 | unsigned char radioNum; |
---|
792 | Xuint8 memory[8], version, revision, valid; |
---|
793 | Xuint16 serial; |
---|
794 | |
---|
795 | //rfSel will be OR'd combo of [RC_RFA, RC_RFB, RC_RFC, RC_RFD] |
---|
796 | // This function must iterate for each radio |
---|
797 | for(i=0; i<4; i++) { |
---|
798 | if(rfSel & rfSel_ALL[i]) { |
---|
799 | cur_rfSel = rfSel_ALL[i]; |
---|
800 | radioNum = i+1; |
---|
801 | } else { |
---|
802 | //Skip this radio |
---|
803 | continue; |
---|
804 | } |
---|
805 | |
---|
806 | //Select the FPGA board EEPROM during init |
---|
807 | eepromStatus = WarpEEPROM_EEPROMSelect((void*)eeprom_ba, 0); |
---|
808 | if(eepromStatus != 0) { |
---|
809 | xil_printf("WarpEEPROM_EEPROMSelect Select Failed! (%d)\n", eepromStatus); |
---|
810 | return -1; |
---|
811 | } |
---|
812 | |
---|
813 | //Initialize the EEPROM controller |
---|
814 | eepromStatus = WarpEEPROM_Initialize((void*)eeprom_ba); |
---|
815 | if(eepromStatus != 0) { |
---|
816 | xil_printf("WarpEEPROM_Initialize Failed! (%x)\n", eepromStatus); |
---|
817 | return -1; |
---|
818 | } |
---|
819 | |
---|
820 | //Select the EEPROM on the current radio board |
---|
821 | eepromStatus = WarpEEPROM_EEPROMSelect((void*)eeprom_ba, radioNum); |
---|
822 | if(eepromStatus != 0) { |
---|
823 | xil_printf("TxDCO: WarpEEPROM_EEPROMSelect error (%x)\n", eepromStatus); |
---|
824 | return -1; |
---|
825 | } |
---|
826 | |
---|
827 | //Read the first page from the EERPOM |
---|
828 | WarpEEPROM_ReadMem((void*)eeprom_ba, 0, 0, memory); |
---|
829 | version = (memory[0] & 0xE0) >> 5; |
---|
830 | revision = (memory[1] & 0xE0) >> 5; |
---|
831 | valid = memory[1] & 0x1F; |
---|
832 | |
---|
833 | //Read the Radio Board serial number |
---|
834 | serial = WarpEEPROM_ReadWARPSerial((void*)eeprom_ba); |
---|
835 | |
---|
836 | //Read the Tx DCO values |
---|
837 | calReadback = WarpEEPROM_ReadRadioCal((void*)eeprom_ba, 2, 1); |
---|
838 | |
---|
839 | //Scale the stored values |
---|
840 | best_I = (signed short)(((signed char)(calReadback & 0xFF))<<1); |
---|
841 | best_Q = (signed short)(((signed char)((calReadback>>8) & 0xFF))<<1); |
---|
842 | xil_printf(" Radio WR-a-%05d Tx DCO I/Q: %d/%d\n", serial, best_I, best_Q); |
---|
843 | |
---|
844 | //Write the Tx DCO values to the DAC offset registers |
---|
845 | radio_controller_DAC_OffsetAdj(rc_ba, cur_rfSel, 0, best_I); |
---|
846 | radio_controller_DAC_OffsetAdj(rc_ba, cur_rfSel, 1, best_Q); |
---|
847 | |
---|
848 | }//END for(each radio) |
---|
849 | |
---|
850 | return 0; |
---|
851 | #else |
---|
852 | print("eerpom_oneiwre pcore is missing! Cannot apply TxDCO correction\n"); |
---|
853 | return -1; |
---|
854 | #endif |
---|
855 | } |
---|
856 | |
---|
857 | /** |
---|
858 | \brief Writes the AD9777 offset registers for the selected DACs and channel (I/Q) |
---|
859 | \param rc_ba Base memory address of radio_controller core |
---|
860 | \param rfSel Selects RF interfaces to affect (OR'd combination of [RC_RFA, RC_RFB, RC_RFC, RC_RFD]) |
---|
861 | \param chan Selects I or Q DAC (0=I, 1=Q) |
---|
862 | \param dc_val DC Offset value to apply; must be in [-1024,1023] |
---|
863 | \return Returns non-zero for invalid inputs; retursn 0 on success |
---|
864 | */ |
---|
865 | int radio_controller_DAC_OffsetAdj(u32 rc_ba, u32 rfSel, u8 chan, short dc_val) { |
---|
866 | short value; |
---|
867 | |
---|
868 | if (dc_val > 1023 || dc_val < -1024) { // Make sure the value is in range. |
---|
869 | return -1; |
---|
870 | } |
---|
871 | |
---|
872 | short reg8; |
---|
873 | if (dc_val < 0) { // If the value is negative then store set the first bit of second register |
---|
874 | reg8 = 0x0080; // to 1 |
---|
875 | } |
---|
876 | else { |
---|
877 | reg8 = 0x0000; // Or if positive set it to 0. |
---|
878 | } |
---|
879 | |
---|
880 | value = abs(dc_val); |
---|
881 | |
---|
882 | short reg7 = ((value & 0x03FC) >> 2); // b9:b2 of the value are the 8 bits in the first register |
---|
883 | reg8 = reg8 + (value & 0x0003); // b1:b0 of the value are the last 2 bits in the second register |
---|
884 | |
---|
885 | if (chan == 0) { |
---|
886 | radio_controller_DAC_SPI_write(rc_ba, rfSel, 0x7, reg7); |
---|
887 | radio_controller_DAC_SPI_write(rc_ba, rfSel, 0x8, reg8); |
---|
888 | } else if (chan == 1) { |
---|
889 | radio_controller_DAC_SPI_write(rc_ba, rfSel, 0xB, reg7); |
---|
890 | radio_controller_DAC_SPI_write(rc_ba, rfSel, 0xC, reg8); |
---|
891 | } else { |
---|
892 | return -1; |
---|
893 | } |
---|
894 | |
---|
895 | return 0; |
---|
896 | } |
---|
897 | |
---|
898 | /** @}*/ //END group user_functions |
---|