source: PlatformSupport/CustomPeripherals/pcores/radio_controller_v3_00_b/hdl/verilog/user_logic.v

//----------------------------------------------------------------------------
// user_logic.vhd - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.            **
// **                                                                       **
// ** Xilinx, Inc.                                                          **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
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// ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
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// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
// ** FOR A PARTICULAR PURPOSE.                                             **
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// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename:          user_logic.vhd
// Version:           3.00.a
// Description:       User logic module.
// Date:              Wed Jul 04 20:55:56 2012 (by Create and Import Peripheral Wizard)
// Verilog Standard:  Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
//   active low signals:                    "*_n"
//   clock signals:                         "clk", "clk_div#", "clk_#x"
//   reset signals:                         "rst", "rst_n"
//   generics:                              "C_*"
//   user defined types:                    "*_TYPE"
//   state machine next state:              "*_ns"
//   state machine current state:           "*_cs"
//   combinatorial signals:                 "*_com"
//   pipelined or register delay signals:   "*_d#"
//   counter signals:                       "*cnt*"
//   clock enable signals:                  "*_ce"
//   internal version of output port:       "*_i"
//   device pins:                           "*_pin"
//   ports:                                 "- Names begin with Uppercase"
//   processes:                             "*_PROCESS"
//   component instantiations:              "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------

module user_logic
(
    // -- ADD USER PORTS BELOW THIS LINE ---------------

    //I/O for MAX2829 pins
    output RFA_TxEn,
    output RFB_TxEn,
    output RFC_TxEn,
    output RFD_TxEn,

    output RFA_RxEn,
    output RFB_RxEn,
    output RFC_RxEn,
    output RFD_RxEn,

    output RFA_RxHP,
    output RFB_RxHP,
    output RFC_RxHP,
    output RFD_RxHP,

    output RFA_SHDN,
    output RFB_SHDN,
    output RFC_SHDN,
    output RFD_SHDN,

    output RFA_SPI_SCLK,
    output RFB_SPI_SCLK,
    output RFC_SPI_SCLK,
    output RFD_SPI_SCLK,
    
    output RFA_SPI_MOSI,
    output RFB_SPI_MOSI,
    output RFC_SPI_MOSI,
    output RFD_SPI_MOSI,

    output RFA_SPI_CSn,
    output RFB_SPI_CSn,
    output RFC_SPI_CSn,
    output RFD_SPI_CSn,

    output [0:6] RFA_B,
    output [0:6] RFB_B,
    output [0:6] RFC_B,
    output [0:6] RFD_B,

    input RFA_LD,
    input RFB_LD,
    input RFC_LD,
    input RFD_LD,
    
    //Outputs to PA and ant switch pins
    output RFA_PAEn_24,
    output RFB_PAEn_24,
    output RFC_PAEn_24,
    output RFD_PAEn_24,

    output RFA_PAEn_5,
    output RFB_PAEn_5,
    output RFC_PAEn_5,
    output RFD_PAEn_5,

    output [0:1] RFA_AntSw,
    output [0:1] RFB_AntSw,
    output [0:1] RFC_AntSw,
    output [0:1] RFD_AntSw,
    
    //I/O for user logic to control state from hardware
    input usr_RFA_TxEn,
    input usr_RFB_TxEn,
    input usr_RFC_TxEn,
    input usr_RFD_TxEn,

    input usr_RFA_RxEn,
    input usr_RFB_RxEn,
    input usr_RFC_RxEn,
    input usr_RFD_RxEn,

    input usr_RFA_RxHP,
    input usr_RFB_RxHP,
    input usr_RFC_RxHP,
    input usr_RFD_RxHP,

    input usr_RFA_SHDN,
    input usr_RFB_SHDN,
    input usr_RFC_SHDN,
    input usr_RFD_SHDN,

    input [0:1] usr_RFA_RxGainRF,
    input [0:1] usr_RFB_RxGainRF,
    input [0:1] usr_RFC_RxGainRF,
    input [0:1] usr_RFD_RxGainRF,

    input [0:4] usr_RFA_RxGainBB,
    input [0:4] usr_RFB_RxGainBB,
    input [0:4] usr_RFC_RxGainBB,
    input [0:4] usr_RFD_RxGainBB,

    input [0:5] usr_RFA_TxGain,
    input [0:5] usr_RFB_TxGain,
    input [0:5] usr_RFC_TxGain,
    input [0:5] usr_RFD_TxGain,

    input        usr_SPI_ctrlSrc,
    input        usr_SPI_go,
    output       usr_SPI_active,
    input [0: 3] usr_SPI_rfsel,
    input [0: 3] usr_SPI_regaddr,
    input [0:13] usr_SPI_regdata,

    output usr_RFA_PHYStart,
    output usr_RFB_PHYStart,
    output usr_RFC_PHYStart,
    output usr_RFD_PHYStart,

    output usr_any_PHYStart,
    
    output usr_RFA_statLED_Tx,
    output usr_RFA_statLED_Rx,
    output usr_RFB_statLED_Tx,
    output usr_RFB_statLED_Rx,
    output usr_RFC_statLED_Tx,
    output usr_RFC_statLED_Rx,
    output usr_RFD_statLED_Tx,
    output usr_RFD_statLED_Rx,
    
    // -- ADD USER PORTS ABOVE THIS LINE ---------------

    // -- DO NOT EDIT BELOW THIS LINE ------------------
    // -- Bus protocol ports, do not add to or delete 
    input                                     Bus2IP_Clk,
    input                                     Bus2IP_Reset,
    input      [0 : C_SLV_DWIDTH-1]           Bus2IP_Data,
    input      [0 : C_SLV_DWIDTH/8-1]         Bus2IP_BE,
    input      [0 : C_NUM_REG-1]              Bus2IP_RdCE,
    input      [0 : C_NUM_REG-1]              Bus2IP_WrCE,
    output     [0 : C_SLV_DWIDTH-1]           IP2Bus_Data,
    output                                    IP2Bus_RdAck,
    output                                    IP2Bus_WrAck,
    output                                    IP2Bus_Error
    // -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic

// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here 
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------

// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_SLV_DWIDTH                   = 32;
parameter C_NUM_REG                      = 64;
// -- DO NOT EDIT ABOVE THIS LINE --------------------

// -- ADD USER PORTS BELOW THIS LINE -----------------
    // -- ADD USER PORTS ABOVE THIS LINE -----------------

// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
/*
input                                     Bus2IP_Clk;
input                                     Bus2IP_Reset;
input      [0 : C_SLV_DWIDTH-1]           Bus2IP_Data;
input      [0 : C_SLV_DWIDTH/8-1]         Bus2IP_BE;
input      [0 : C_NUM_REG-1]              Bus2IP_RdCE;
input      [0 : C_NUM_REG-1]              Bus2IP_WrCE;
output     [0 : C_SLV_DWIDTH-1]           IP2Bus_Data;
output                                    IP2Bus_RdAck;
output                                    IP2Bus_WrAck;
output                                    IP2Bus_Error;
*/
// -- DO NOT EDIT ABOVE THIS LINE --------------------

//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------

    // --USER nets declarations added here, as needed for user logic
`define MAX2829_REG0_ON_RESET   14'b01000101000000
`define MAX2829_REG1_ON_RESET   14'b00000011001010
`define MAX2829_REG2_ON_RESET   14'b01000000000111
`define MAX2829_REG3_ON_RESET   14'b11000010100010
`define MAX2829_REG4_ON_RESET   14'b01110111011101
`define MAX2829_REG5_ON_RESET   14'b01100000100100
`define MAX2829_REG6_ON_RESET   14'b01110000000000
`define MAX2829_REG7_ON_RESET   14'b00000000101010
`define MAX2829_REG8_ON_RESET   14'b00000000100101
`define MAX2829_REG9_ON_RESET   14'b00001000000000
`define MAX2829_REGA_ON_RESET   14'b00001111000000
`define MAX2829_REGB_ON_RESET   14'b00000001111111
`define MAX2829_REGC_ON_RESET   14'b00000000000000

`define TXTIMING_REG_ON_RESET   32'h401000F0 //Sane default Tx Timing values
`define TXGAINS_REG_ON_RESET    32'h32323232 //Tx Gain targets = 50
`define CLKDIV_GAINTIMING_REG_ON_RESET  32'h00004F22 //Gain step=0xF, time step=4, clk divs = 2

    // Nets for user logic slave model s/w accessible register example
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg0;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg1;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg2;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg3;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg4;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg5;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg6;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg7;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg8;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg9;
    reg        [0 : C_SLV_DWIDTH-1]           slv_reg10;

    wire       [0 : 10]                       slv_reg_write_sel;
    wire       [0 : 63]                       slv_reg_read_sel;
    reg        [0 : C_SLV_DWIDTH-1]           slv_ip2bus_data;
    wire                                      slv_read_ack;
    wire                                      slv_write_ack;
    integer                                   byte_index, bit_index;


    wire slv_write_ack_normalRegisters;

    wire [0:31] status_reg;

    //Use Verilog array-of-arrays syntax for the register banks to mirror MAX2829 internal registers
    // RFx_MAX2829_mirrorRegs[N] maps to MAX2829 reg N, for N=[0x0, 0xC]
    // All registers are 14 bits in the MAX2829
    reg [0:13] RFA_MAX2829_mirrorRegs [0:12];
    reg [0:13] RFB_MAX2829_mirrorRegs [0:12];
    reg [0:13] RFC_MAX2829_mirrorRegs [0:12];
    reg [0:13] RFD_MAX2829_mirrorRegs [0:12];

    wire RFA_TxEn_ctrlSrc, RFB_TxEn_ctrlSrc, RFC_TxEn_ctrlSrc, RFD_TxEn_ctrlSrc;
    wire RFA_RxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFD_RxEn_ctrlSrc;
    wire RFA_RxHP_ctrlSrc, RFB_RxHP_ctrlSrc, RFC_RxHP_ctrlSrc, RFD_RxHP_ctrlSrc;
    wire RFA_SHDN_ctrlSrc, RFB_SHDN_ctrlSrc, RFC_SHDN_ctrlSrc, RFD_SHDN_ctrlSrc;
    wire RFA_TxGain_ctrlSrc, RFB_TxGain_ctrlSrc, RFC_TxGain_ctrlSrc, RFD_TxGain_ctrlSrc;
    wire RFA_RxGain_ctrlSrc, RFB_RxGain_ctrlSrc, RFC_RxGain_ctrlSrc, RFD_RxGain_ctrlSrc;

    wire RFA_TxEn_sw, RFB_TxEn_sw, RFC_TxEn_sw, RFD_TxEn_sw;
    wire RFA_RxEn_sw, RFB_RxEn_sw, RFC_RxEn_sw, RFD_RxEn_sw;
    wire RFA_RxHP_sw, RFB_RxHP_sw, RFC_RxHP_sw, RFD_RxHP_sw;
    wire RFA_SHDN_sw, RFB_SHDN_sw, RFC_SHDN_sw, RFD_SHDN_sw;

    wire RFA_PAEn, RFB_PAEn, RFC_PAEn, RFD_PAEn;

    wire [0:7] TxTiming_dly_TxGainRamp, TxTiming_dly_PowerAmpEn, TxTiming_dly_TxEn, TxTiming_dly_startPHY;

    wire [0:3] TxGainRamp_gainStep, TxGainRamp_timeStep;
    
    wire [0:5] RFA_TxGain_sw, RFB_TxGain_sw, RFC_TxGain_sw, RFD_TxGain_sw;
    wire [0:4] RFA_RxGainBB_sw, RFB_RxGainBB_sw, RFC_RxGainBB_sw, RFD_RxGainBB_sw;
    wire [0:1] RFA_RxGainRF_sw, RFB_RxGainRF_sw, RFC_RxGainRF_sw, RFD_RxGainRF_sw;

    wire [0:5] RFA_TxGain_target, RFB_TxGain_target, RFC_TxGain_target, RFD_TxGain_target;
    wire [0:5] RFA_TxGain_ramped, RFB_TxGain_ramped, RFC_TxGain_ramped, RFD_TxGain_ramped;

    wire [0:4] RFA_RxGainBB, RFB_RxGainBB, RFC_RxGainBB, RFD_RxGainBB;
    wire [0:1] RFA_RxGainRF, RFB_RxGainRF, RFC_RxGainRF, RFD_RxGainRF;

    wire [0:2] spi_clk_div_sel;
    wire [0:1] txTiming_clk_div_sel;

    wire [0: 3] spi_rfsel_mask_sw;
    wire [0: 3] spi_rfsel_mask;
    wire [0:13] spi_tx_regdata;
    wire [0: 3] spi_tx_regaddr;
    wire spi_go;

    wire spi_tx_reg_write;
    wire spi_xfer_done;

    wire RFA_txStart, RFB_txStart, RFC_txStart, RFD_txStart;

    wire RFA_MAX2829_Reset, RFB_MAX2829_Reset, RFC_MAX2829_Reset, RFD_MAX2829_Reset;

    // Slave register write process; only implemented for RW and WO registers
    always @( posedge Bus2IP_Clk )
        begin: SLAVE_REG_WRITE_PROC
            if ( Bus2IP_Reset == 1 )
                begin
                    slv_reg0 <= 0; //All zeros on reset- Tx/Rx disabled, SHDN (active low) enabled
                    slv_reg1 <= `TXTIMING_REG_ON_RESET;
                    slv_reg2 <= `TXGAINS_REG_ON_RESET;
                    slv_reg3 <= 0;
                    slv_reg4 <= `CLKDIV_GAINTIMING_REG_ON_RESET;
                    slv_reg5 <= 0;
                    slv_reg6 <= 0;
                    slv_reg7 <= 0;
                    slv_reg8 <= 0;
                    slv_reg9 <= 0;
                    slv_reg10 <= 0;
                end
            else
                case ( slv_reg_write_sel )
                    11'b10000000000 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
                    11'b01000000000 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00100000000 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00010000000 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00001000000 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00000100000 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00000010000 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00000001000 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00000000100 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg8[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00000000010 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg9[bit_index] <= Bus2IP_Data[bit_index];
                    11'b00000000001 :
                        for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                            if ( Bus2IP_BE[byte_index] == 1 )
                                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
                                    slv_reg10[bit_index] <= Bus2IP_Data[bit_index];
                    default : ;
                endcase

        end // SLAVE_REG_WRITE_PROC

    // Slave model register read mux
    // All registers can be read
    always @*
        begin: SLAVE_REG_READ_PROC
            case ( slv_reg_read_sel )
                64'b1000000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg0;
                64'b0100000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg1;
                64'b0010000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg2;
                64'b0001000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg3;
                64'b0000100000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg4;
                64'b0000010000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg5;
                64'b0000001000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg6;
                64'b0000000100000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg7;
                64'b0000000010000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg8;
                64'b0000000001000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg9;
                64'b0000000000100000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg10;
                64'b0000000000010000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= status_reg;
                64'b0000000000001000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[0]};
                64'b0000000000000100000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[1]};
                64'b0000000000000010000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[2]};
                64'b0000000000000001000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[3]};
                64'b0000000000000000100000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[4]};
                64'b0000000000000000010000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[5]};
                64'b0000000000000000001000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[6]};
                64'b0000000000000000000100000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[7]};
                64'b0000000000000000000010000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[8]};
                64'b0000000000000000000001000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[9]};
                64'b0000000000000000000000100000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[10]};
                64'b0000000000000000000000010000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[11]};
                64'b0000000000000000000000001000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[12]};
                64'b0000000000000000000000000100000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[0]};
                64'b0000000000000000000000000010000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[1]};
                64'b0000000000000000000000000001000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[2]};
                64'b0000000000000000000000000000100000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[3]};
                64'b0000000000000000000000000000010000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[4]};
                64'b0000000000000000000000000000001000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[5]};
                64'b0000000000000000000000000000000100000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[6]};
                64'b0000000000000000000000000000000010000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[7]};
                64'b0000000000000000000000000000000001000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[8]};
                64'b0000000000000000000000000000000000100000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[9]};
                64'b0000000000000000000000000000000000010000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[10]};
                64'b0000000000000000000000000000000000001000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[11]};
                64'b0000000000000000000000000000000000000100000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[12]};
                64'b0000000000000000000000000000000000000010000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[0]};
                64'b0000000000000000000000000000000000000001000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[1]};
                64'b0000000000000000000000000000000000000000100000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[2]};
                64'b0000000000000000000000000000000000000000010000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[3]};
                64'b0000000000000000000000000000000000000000001000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[4]};
                64'b0000000000000000000000000000000000000000000100000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[5]};
                64'b0000000000000000000000000000000000000000000010000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[6]};
                64'b0000000000000000000000000000000000000000000001000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[7]};
                64'b0000000000000000000000000000000000000000000000100000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[8]};
                64'b0000000000000000000000000000000000000000000000010000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[9]};
                64'b0000000000000000000000000000000000000000000000001000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[10]};
                64'b0000000000000000000000000000000000000000000000000100000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[11]};
                64'b0000000000000000000000000000000000000000000000000010000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[12]};
                64'b0000000000000000000000000000000000000000000000000001000000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[0]};
                64'b0000000000000000000000000000000000000000000000000000100000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[1]};
                64'b0000000000000000000000000000000000000000000000000000010000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[2]};
                64'b0000000000000000000000000000000000000000000000000000001000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[3]};
                64'b0000000000000000000000000000000000000000000000000000000100000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[4]};
                64'b0000000000000000000000000000000000000000000000000000000010000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[5]};
                64'b0000000000000000000000000000000000000000000000000000000001000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[6]};
                64'b0000000000000000000000000000000000000000000000000000000000100000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[7]};
                64'b0000000000000000000000000000000000000000000000000000000000010000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[8]};
                64'b0000000000000000000000000000000000000000000000000000000000001000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[9]};
                64'b0000000000000000000000000000000000000000000000000000000000000100 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[10]};
                64'b0000000000000000000000000000000000000000000000000000000000000010 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[11]};
                64'b0000000000000000000000000000000000000000000000000000000000000001 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[12]};
                default : slv_ip2bus_data <= 0;
            endcase

        end // SLAVE_REG_READ_PROC

    /* Address map:
        HDL is coded [MSB:LSB] = [0:31]
        regX[ 0] maps to 0x80000000 in C driver
        regX[31] maps to 0x00000001 in C driver

    0: RW: MAX2829 control signals and control source (sw vs. hw)
        Mask for RFA: 0x000000FF
        Mask for RFB: 0x0000FF00
        Mask for RFC: 0x00FF0000
        Mask for RFD: 0xFF000000
        [ 0: 3] = RFD Control: {TxEn, RxEn, RxHP, SHDN}
        [ 4: 7] = RFD Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port)
        [ 8:11] = RFC Control: {TxEn, RxEn, RxHP, SHDN}
        [12:15] = RFC Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port)
        [16:19] = RFB Control: {TxEn, RxEn, RxHP, SHDN}
        [20:23] = RFB Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port)
        [24:27] = RFA Control: {TxEn, RxEn, RxHP, SHDN}
        [28:31] = RFA Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port)
        
    1: RW: Tx Timing
        Shared by all RF interfaces
        [ 0: 7] = Delay before Tx VGA ramp start        0xFF000000
        [ 8:15] = Delay before PA enable                0x00FF0000
        [16:23] = Delay before MAX2829 TxEn assertion   0x0000FF00
        [24:31] = Delay before usr_startPHY assertion   0x000000FF

    2: RW: Tx Gains
        [    0] = RF D Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x80000000
        [    1] = Reserved
        [ 2: 7] = RF D Tx Gain                                       0x3F000000
        [    8] = RF C Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00800000
        [    9] = Reserved
        [10:15] = RF C Tx Gain                                       0x003F0000
        [   16] = RF B Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00008000
        [   17] = Reserved
        [18:23] = RF B Tx Gain                                       0x00003F00
        [   24] = RF A Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00000080
        [   25] = Reserved
        [26:31] = RF A Tx Gain                                       0x0000003F

    3: RW: Rx gains
        [    0] = RFD Rx gain ctrl source (0=register values, 1=usr_ ports)
        [ 1: 2] = RFD Rx RF Gain
        [ 3: 7] = RFD Rx BB Gain
        [    8] = RFC Rx gain ctrl source (0=register values, 1=usr_ ports)
        [ 9:10] = RFC Rx RF Gain
        [11:15] = RFC Rx BB Gain
        [   16] = RFB Rx gain ctrl source (0=register values, 1=usr_ ports)
        [17:18] = RFB Rx RF Gain
        [19:23] = RFB Rx BB Gain
        [   24] = RFA Rx gain ctrl source (0=register values, 1=usr_ ports)
        [25:26] = RFA Rx RF Gain
        [27:31] = RFA Rx BB Gain

    4: RW: Clock dividers & Tx gain ramp config
        [16:19] = Tx VGA ramp time step  0x0000F000
        [20:23] = Tx VGA ramp gain step  0x00000F00
        [   24] = Reserved               0x00000080
        [25:27] = SPI clock divider      0x00000070
        [28:29] = Reserved               0x0000000C
        [30:31] = TxTiming clock divider 0x00000003

    5: WO: SPI write register
    Special register:
     * Write from software triggers SPI transaction
     * IPIF WrACK delayed until SPI is done (i.e. software doesn't have to poll; Xil_Out32 blocks until SPI is done)
     * Reads of this register return last SPI word transferred by software (might be stale, if usr_ SPI ports are also used)
        [ 0: 3] SPI chip select mask RF[D:A]    0x80000000=RFD, 0x40000000=RFC, 0x20000000=RFB, 0x10000000=RFA
        [ 4:11] Reserved                        0x0FF00000
        [12:15] Register address to write       0x000F0000
        [16:17] Reserved                        0x0000C000
        [18:31] Register value to write         0x00003FFF



    6 to 10: Reserved (RW 32-bit registers implemented; no connection to external hardware)

    11: RO: Status bits
        Same per-RF masks as reg[0], same control signal masks as reg[0]
        [ 0: 3] = RFD control status {TxEn, RxEn, RxHP, SHDN}
        [    4] = RFD MAX2829 PLL locked (1=locked)
        [    5] = RFD SPI transfer in progress
        [ 6: 7] = Reserved

        [ 8:11] = RFC control status {TxEn, RxEn, RxHP, SHDN}
        [   12] = RFC MAX2829 PLL locked (1=locked)
        [   13] = RFC SPI transfer in progress
        [14:15] = Reserved

        [16:19] = RFB control status {TxEn, RxEn, RxHP, SHDN}
        [   20] = RFB MAX2829 PLL locked (1=locked)
        [   21] = RFB SPI transfer in progress
        [22:23] = Reserved

        [24:27] = RFA control status {TxEn, RxEn, RxHP, SHDN}
        [   28] = RFA MAX2829 PLL locked (1=locked)
        [   29] = RFA SPI transfer in progress
        [30:31] = Reserved

    12 to 63: RO: Read-only registers which mirror state of MAX2829 internal registers (since MAX2829 SPI is write-only)
     * Registers are initialized (on FPGA config and MAX2829 reset) to MAX2829 defaults, to match MAX2829 reset state
     * Register values are updated automatically by SPI writes (via reg4 or via usr_ SPI port use)
     * Every register is:
        [ 0:17] Reserved; returns 0 on read
        [18:31] Register value (14 bits)

    12...24: RO: Local copies of MAX2829 registers for RFA
        12: RFA MAX2829 reg0
        ...
        24: RFA MAX2829 regC

    25...37: RO: Local copies of MAX2829 registers for RFB
        25: RFB MAX2829 reg0
        ...
        37: RFB MAX2829 regC

    38...50: RO: Local copies of MAX2829 registers for RFC
        38: RFC MAX2829 reg0
        ...
        50: RFC MAX2829 regC

    51...63: RO: Local copies of MAX2829 registers for RFD
        51: RFD MAX2829 reg0
        ...
        63: RFD MAX2829 regC

    */

    //User logic -> IPIF signals
    assign IP2Bus_Data    = slv_ip2bus_data;
    assign IP2Bus_RdAck   = slv_read_ack;
    assign IP2Bus_Error   = 0;

    //spi_tx_reg_write (Bus2IP_WrCE[x]) de-asserts as soon as transaction is ACK'd
    // so this mux switches back to the generic ACK as soon as the SPI xfer is done
    //Thus, the duration of assertion for spi_xfer_done doesn't really matter
    //A bit fast-n-loose, but works ok
    assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack_normalRegisters;

    //Original definitions (wizard assumes all registers are RW)
    //slv_reg_write_sel = Bus2IP_WrCE[0:63],
    //slv_reg_read_sel  = Bus2IP_RdCE[0:63],
    //slv_read_ack      = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15] || Bus2IP_RdCE[16] || Bus2IP_RdCE[17] || Bus2IP_RdCE[18] || Bus2IP_RdCE[19] || Bus2IP_RdCE[20] || Bus2IP_RdCE[21] || Bus2IP_RdCE[22] || Bus2IP_RdCE[23] || Bus2IP_RdCE[24] || Bus2IP_RdCE[25] || Bus2IP_RdCE[26] || Bus2IP_RdCE[27] || Bus2IP_RdCE[28] || Bus2IP_RdCE[29] || Bus2IP_RdCE[30] || Bus2IP_RdCE[31] || Bus2IP_RdCE[32] || Bus2IP_RdCE[33] || Bus2IP_RdCE[34] || Bus2IP_RdCE[35] || Bus2IP_RdCE[36] || Bus2IP_RdCE[37] || Bus2IP_RdCE[38] || Bus2IP_RdCE[39] || Bus2IP_RdCE[40] || Bus2IP_RdCE[41] || Bus2IP_RdCE[42] || Bus2IP_RdCE[43] || Bus2IP_RdCE[44] || Bus2IP_RdCE[45] || Bus2IP_RdCE[46] || Bus2IP_RdCE[47] || Bus2IP_RdCE[48] || Bus2IP_RdCE[49] || Bus2IP_RdCE[50] || Bus2IP_RdCE[51] || Bus2IP_RdCE[52] || Bus2IP_RdCE[53] || Bus2IP_RdCE[54] || Bus2IP_RdCE[55] || Bus2IP_RdCE[56] || Bus2IP_RdCE[57] || Bus2IP_RdCE[58] || Bus2IP_RdCE[59] || Bus2IP_RdCE[60] || Bus2IP_RdCE[61] || Bus2IP_RdCE[62] || Bus2IP_RdCE[63];
    //slv_write_ack     = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15] || Bus2IP_WrCE[16] || Bus2IP_WrCE[17] || Bus2IP_WrCE[18] || Bus2IP_WrCE[19] || Bus2IP_WrCE[20] || Bus2IP_WrCE[21] || Bus2IP_WrCE[22] || Bus2IP_WrCE[23] || Bus2IP_WrCE[24] || Bus2IP_WrCE[25] || Bus2IP_WrCE[26] || Bus2IP_WrCE[27] || Bus2IP_WrCE[28] || Bus2IP_WrCE[29] || Bus2IP_WrCE[30] || Bus2IP_WrCE[31] || Bus2IP_WrCE[32] || Bus2IP_WrCE[33] || Bus2IP_WrCE[34] || Bus2IP_WrCE[35] || Bus2IP_WrCE[36] || Bus2IP_WrCE[37] || Bus2IP_WrCE[38] || Bus2IP_WrCE[39] || Bus2IP_WrCE[40] || Bus2IP_WrCE[41] || Bus2IP_WrCE[42] || Bus2IP_WrCE[43] || Bus2IP_WrCE[44] || Bus2IP_WrCE[45] || Bus2IP_WrCE[46] || Bus2IP_WrCE[47] || Bus2IP_WrCE[48] || Bus2IP_WrCE[49] || Bus2IP_WrCE[50] || Bus2IP_WrCE[51] || Bus2IP_WrCE[52] || Bus2IP_WrCE[53] || Bus2IP_WrCE[54] || Bus2IP_WrCE[55] || Bus2IP_WrCE[56] || Bus2IP_WrCE[57] || Bus2IP_WrCE[58] || Bus2IP_WrCE[59] || Bus2IP_WrCE[60] || Bus2IP_WrCE[61] || Bus2IP_WrCE[62] || Bus2IP_WrCE[63],

    //All registers can be read
    assign slv_reg_read_sel  = Bus2IP_RdCE[0:63];
    assign slv_read_ack      = |Bus2IP_RdCE[0:63];

    //Only regs 0 to 10 can be written; 12 to 63 are RO
    assign slv_reg_write_sel = Bus2IP_WrCE[0:10];

    //Write ack for reg5 is delayed by SPI transfer
    assign slv_write_ack_normalRegisters = |{Bus2IP_WrCE[0:4], Bus2IP_WrCE[6:10]};

    
    //Register 0: MAX2829 control
    assign RFD_TxEn_sw = slv_reg0[ 0];
    assign RFC_TxEn_sw = slv_reg0[ 8];
    assign RFB_TxEn_sw = slv_reg0[16];
    assign RFA_TxEn_sw = slv_reg0[24];

    assign RFD_RxEn_sw = slv_reg0[ 1];
    assign RFC_RxEn_sw = slv_reg0[ 9];
    assign RFB_RxEn_sw = slv_reg0[17];
    assign RFA_RxEn_sw = slv_reg0[25];

    assign RFD_RxHP_sw = slv_reg0[ 2];
    assign RFC_RxHP_sw = slv_reg0[10];
    assign RFB_RxHP_sw = slv_reg0[18];
    assign RFA_RxHP_sw = slv_reg0[26];

    assign RFD_SHDN_sw = slv_reg0[ 3];
    assign RFC_SHDN_sw = slv_reg0[11];
    assign RFB_SHDN_sw = slv_reg0[19];
    assign RFA_SHDN_sw = slv_reg0[27];

    assign RFD_TxEn_ctrlSrc = slv_reg0[ 4];
    assign RFC_TxEn_ctrlSrc = slv_reg0[12];
    assign RFB_TxEn_ctrlSrc = slv_reg0[20];
    assign RFA_TxEn_ctrlSrc = slv_reg0[28];

    assign RFD_RxEn_ctrlSrc = slv_reg0[ 5];
    assign RFC_RxEn_ctrlSrc = slv_reg0[13];
    assign RFB_RxEn_ctrlSrc = slv_reg0[21];
    assign RFA_RxEn_ctrlSrc = slv_reg0[29];

    assign RFD_RxHP_ctrlSrc = slv_reg0[ 6];
    assign RFC_RxHP_ctrlSrc = slv_reg0[14];
    assign RFB_RxHP_ctrlSrc = slv_reg0[22];
    assign RFA_RxHP_ctrlSrc = slv_reg0[30];

    assign RFD_SHDN_ctrlSrc = slv_reg0[ 7];
    assign RFC_SHDN_ctrlSrc = slv_reg0[15];
    assign RFB_SHDN_ctrlSrc = slv_reg0[23];
    assign RFA_SHDN_ctrlSrc = slv_reg0[31];

    //Register 1: Tx timing
    assign TxTiming_dly_TxGainRamp  = slv_reg1[ 0: 7];
    assign TxTiming_dly_PowerAmpEn  = slv_reg1[ 8:15];
    assign TxTiming_dly_TxEn        = slv_reg1[16:23];
    assign TxTiming_dly_startPHY    = slv_reg1[24:31];
    
    //Register 2: Tx gains
    assign RFD_TxGain_sw =      slv_reg2[ 2: 7];
    assign RFC_TxGain_sw =      slv_reg2[10:15];
    assign RFB_TxGain_sw =      slv_reg2[18:23];
    assign RFA_TxGain_sw =      slv_reg2[26:31];

    assign RFD_TxGain_ctrlSrc = slv_reg2[ 0];
    assign RFC_TxGain_ctrlSrc = slv_reg2[ 8];
    assign RFB_TxGain_ctrlSrc = slv_reg2[16];
    assign RFA_TxGain_ctrlSrc = slv_reg2[24];

    //Register 3: Rx gains
    assign RFD_RxGainBB_sw =    slv_reg3[ 3: 7];
    assign RFC_RxGainBB_sw =    slv_reg3[11:15];
    assign RFB_RxGainBB_sw =    slv_reg3[19:23];
    assign RFA_RxGainBB_sw =    slv_reg3[27:31];

    assign RFD_RxGainRF_sw =    slv_reg3[ 1: 2];
    assign RFC_RxGainRF_sw =    slv_reg3[ 9:10];
    assign RFB_RxGainRF_sw =    slv_reg3[17:18];
    assign RFA_RxGainRF_sw =    slv_reg3[25:26];
    
    assign RFD_RxGain_ctrlSrc = slv_reg3[ 0];
    assign RFC_RxGain_ctrlSrc = slv_reg3[ 8];
    assign RFB_RxGain_ctrlSrc = slv_reg3[16];
    assign RFA_RxGain_ctrlSrc = slv_reg3[24];
    
    //Register 4: Clock dividers & Tx gain ramp config
    assign TxGainRamp_timeStep =    slv_reg4[16:19];
    assign TxGainRamp_gainStep =    slv_reg4[20:23];
    assign spi_clk_div_sel =        slv_reg4[25:27];
    assign txTiming_clk_div_sel =   slv_reg4[30:31];

    //Register 5: SPI write
    assign spi_rfsel_mask_sw = slv_reg5[0:3];
    assign spi_tx_regdata = slv_reg5[18:31];
    assign spi_tx_regaddr = slv_reg5[12:15];

    //Use the IPIF write-enable for the SPI Tx register as the SPI go
    // The bus will be paused until the SPI transfer is finished
    assign spi_tx_reg_write = Bus2IP_WrCE[5];

    //Register 11: Read-only status bits
    assign status_reg[ 0: 3] = {RFD_TxEn, RFD_RxEn, RFD_RxHP, RFD_SHDN};
    assign status_reg[ 4: 7] = {RFD_LD, ~RFD_SPI_CSn, RFD_PAEn_24, RFD_PAEn_5};

    assign status_reg[ 8:11] = {RFC_TxEn, RFC_RxEn, RFC_RxHP, RFC_SHDN};
    assign status_reg[12:15] = {RFC_LD, ~RFC_SPI_CSn, RFC_PAEn_24, RFC_PAEn_5};

    assign status_reg[16:19] = {RFB_TxEn, RFB_RxEn, RFB_RxHP, RFB_SHDN};
    assign status_reg[20:23] = {RFB_LD, ~RFB_SPI_CSn, RFB_PAEn_24, RFB_PAEn_5};

    assign status_reg[24:27] = {RFA_TxEn, RFA_RxEn, RFA_RxHP, RFA_SHDN};
    assign status_reg[28:31] = {RFA_LD, ~RFA_SPI_CSn, RFA_PAEn_24, RFA_PAEn_5};

    //Mux the various control signals between software and hardware control
    assign RFA_txStart = RFA_TxEn_ctrlSrc ? usr_RFA_TxEn : RFA_TxEn_sw;
    assign RFB_txStart = RFB_TxEn_ctrlSrc ? usr_RFB_TxEn : RFB_TxEn_sw;
    assign RFC_txStart = RFC_TxEn_ctrlSrc ? usr_RFC_TxEn : RFC_TxEn_sw;
    assign RFD_txStart = RFD_TxEn_ctrlSrc ? usr_RFD_TxEn : RFD_TxEn_sw;

    assign RFA_RxEn = RFA_RxEn_ctrlSrc ? usr_RFA_RxEn : RFA_RxEn_sw;
    assign RFB_RxEn = RFB_RxEn_ctrlSrc ? usr_RFB_RxEn : RFB_RxEn_sw;
    assign RFC_RxEn = RFC_RxEn_ctrlSrc ? usr_RFC_RxEn : RFC_RxEn_sw;
    assign RFD_RxEn = RFD_RxEn_ctrlSrc ? usr_RFD_RxEn : RFD_RxEn_sw;

    assign RFA_RxHP = RFA_RxHP_ctrlSrc ? usr_RFA_RxHP : RFA_RxHP_sw;
    assign RFB_RxHP = RFB_RxHP_ctrlSrc ? usr_RFB_RxHP : RFB_RxHP_sw;
    assign RFC_RxHP = RFC_RxHP_ctrlSrc ? usr_RFC_RxHP : RFC_RxHP_sw;
    assign RFD_RxHP = RFD_RxHP_ctrlSrc ? usr_RFD_RxHP : RFD_RxHP_sw;

    assign RFA_SHDN = RFA_SHDN_ctrlSrc ? usr_RFA_SHDN : RFA_SHDN_sw;
    assign RFB_SHDN = RFB_SHDN_ctrlSrc ? usr_RFB_SHDN : RFB_SHDN_sw;
    assign RFC_SHDN = RFC_SHDN_ctrlSrc ? usr_RFC_SHDN : RFC_SHDN_sw;
    assign RFD_SHDN = RFD_SHDN_ctrlSrc ? usr_RFD_SHDN : RFD_SHDN_sw;

    assign RFA_TxGain_target = RFA_TxGain_ctrlSrc ? usr_RFA_TxGain : RFA_TxGain_sw;
    assign RFB_TxGain_target = RFB_TxGain_ctrlSrc ? usr_RFB_TxGain : RFB_TxGain_sw;
    assign RFC_TxGain_target = RFC_TxGain_ctrlSrc ? usr_RFC_TxGain : RFC_TxGain_sw;
    assign RFD_TxGain_target = RFD_TxGain_ctrlSrc ? usr_RFD_TxGain : RFD_TxGain_sw;

    assign RFA_RxGainBB = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainBB : RFA_RxGainBB_sw;
    assign RFB_RxGainBB = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainBB : RFB_RxGainBB_sw;
    assign RFC_RxGainBB = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainBB : RFC_RxGainBB_sw;
    assign RFD_RxGainBB = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainBB : RFD_RxGainBB_sw;

    assign RFA_RxGainRF = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainRF : RFA_RxGainRF_sw;
    assign RFB_RxGainRF = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainRF : RFB_RxGainRF_sw;
    assign RFC_RxGainRF = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainRF : RFC_RxGainRF_sw;
    assign RFD_RxGainRF = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainRF : RFD_RxGainRF_sw;

    
    //Output OR'd PHYStart signal (most PHYs use this, so any TxEnable will start the PHY)
    // Individual PHYStarts are provided in case user has multiple PHYs connected to different RF paths
    assign usr_any_PHYStart = usr_RFA_PHYStart || usr_RFB_PHYStart || usr_RFC_PHYStart || usr_RFD_PHYStart;
    
    //SKY13370 needs 100-250nsec to settle, so make the switch as soon as we know Tx process is starting
    //2-bit control signal in hardware, but only two valid states:
    //   [V1 V2] = [1 0] => Rx path connected to SMA, Tx path terminated to 50 ohms (PA must be off!)
    //   [V1 V2] = [0 1] => Tx path connected to SMA, Rx path terminated to 50 ohms
    //RFx_AntSw[0] = SKY13370.V1, RFx_AntSw[1] = SKY13370.V2
    assign RFA_AntSw[0:1] = {~RFA_txStart, RFA_txStart};
    assign RFB_AntSw[0:1] = {~RFB_txStart, RFB_txStart};
    assign RFC_AntSw[0:1] = {~RFC_txStart, RFC_txStart};
    assign RFD_AntSw[0:1] = {~RFD_txStart, RFD_txStart};

    //PAs are enabled by single wire per band
    // One path's 2.4 and 5GHz PAs should never be enabled simultaneously
    //2.4GHz PA is on when:
    // TxTiming state machine asserts PAEn AND
    // MAX2829.reg5[0] == 0 (indicating MAX2829 is tuned to 2.4GHz band)
    //5GHz PA is on when:
    // TxTiming state machine asserts PAEn AND
    // MAX2829.reg5[0] == 1 (indicating MAX2829 is tuned to 5GHz band)
    //RFx_MAX2829_mirrorRegs are indexed [MSB:LSB]=[0:13] to match other busses in this core,
    // so the LSB (bit [0] in MAX2829 datasheet) is RFA_MAX2829_mirrorRegs[x][13] here
    assign RFA_PAEn_24 = (RFA_PAEn & ~(RFA_MAX2829_mirrorRegs[5][13]));
    assign RFB_PAEn_24 = (RFB_PAEn & ~(RFB_MAX2829_mirrorRegs[5][13]));
    assign RFC_PAEn_24 = (RFC_PAEn & ~(RFC_MAX2829_mirrorRegs[5][13]));
    assign RFD_PAEn_24 = (RFD_PAEn & ~(RFD_MAX2829_mirrorRegs[5][13]));

    assign RFA_PAEn_5 = (RFA_PAEn & (RFA_MAX2829_mirrorRegs[5][13]));
    assign RFB_PAEn_5 = (RFB_PAEn & (RFB_MAX2829_mirrorRegs[5][13]));
    assign RFC_PAEn_5 = (RFC_PAEn & (RFC_MAX2829_mirrorRegs[5][13]));
    assign RFD_PAEn_5 = (RFD_PAEn & (RFD_MAX2829_mirrorRegs[5][13]));
        

    //MAX2829 gain control bus
    // radio_controller.RFx_B[6:0] maps to MAX2829.B[7:1]
    //   radio_controller.RFx_B[6] is MSB, radio_controller.RFx_B[0] is LSB
    //   MAX2829.B7 is MSB, MAX2829.B1 is LSB
    //  Note the RFx_B port is endian swapped relative to other busses in this core
    //   to match the MAX2829 B port
    //When SPI gain control is disabled:
    // In Tx mode:
    //   MAX2829.B[7] is don't care
    //   MAX2829.B[6:1] = Tx RF VGA (6'd63 is max gain, 6'd0 is min gain (approx max-30dB))
    // In Rx mode:
    //   MAX2829.B[7:6] = Rx RF LNA (2'd3 is max gain (30dB), 2'd1 is min gain (0dB), 2'd0 is invalid)
    //   MAX2829.B[5:1] = Rx BB VGA (5'd31 is max gain (approx 62dB), 5'd0 is min gain (approx 0dB)
    assign {RFA_B[6], RFA_B[5], RFA_B[4], RFA_B[3], RFA_B[2], RFA_B[1], RFA_B[0]} = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB};
    assign {RFB_B[6], RFB_B[5], RFB_B[4], RFB_B[3], RFB_B[2], RFB_B[1], RFB_B[0]} = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB};
    assign {RFC_B[6], RFC_B[5], RFC_B[4], RFC_B[3], RFC_B[2], RFC_B[1], RFC_B[0]} = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB};
    assign {RFD_B[6], RFD_B[5], RFD_B[4], RFD_B[3], RFD_B[2], RFD_B[1], RFD_B[0]} = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB};

    
    //Simple state machines for fixed timing of Tx events (MAX2829 TxEn, PA enable and PHY start)
    // One per RF path, to handle case of user designs which do Tx/Rx asychronously across paths
    // All use same timing values, as these are really tuned to the hardware, not the Tx signal
    radio_controller_TxTiming RFA_txTiming (
        .clk(Bus2IP_Clk),
        .reset(Bus2IP_Reset),

        .clk_div(txTiming_clk_div_sel),

        .sw_start(RFA_txStart),

        .dly_GainRamp(TxTiming_dly_TxGainRamp),
        .dly_TxEn(TxTiming_dly_TxEn),
        .dly_PHYStart(TxTiming_dly_startPHY),
        .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn),

        .gainRamp_TxGainTarget(RFA_TxGain_target),
        .gainRamp_GainStep(TxGainRamp_gainStep),
        .gainRamp_TimeStep(TxGainRamp_timeStep),
        .gainRamp_TxGainOut(RFA_TxGain_ramped),

        .TxEn(RFA_TxEn),
        .PAEn(RFA_PAEn),
        .PHYStart(usr_RFA_PHYStart)
    );
    radio_controller_TxTiming RFB_txTiming (
        .clk(Bus2IP_Clk),
        .reset(Bus2IP_Reset),

        .clk_div(txTiming_clk_div_sel),

        .sw_start(RFB_txStart),

        .dly_GainRamp(TxTiming_dly_TxGainRamp),
        .dly_TxEn(TxTiming_dly_TxEn),
        .dly_PHYStart(TxTiming_dly_startPHY),
        .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn),

        .gainRamp_TxGainTarget(RFB_TxGain_target),
        .gainRamp_GainStep(TxGainRamp_gainStep),
        .gainRamp_TimeStep(TxGainRamp_timeStep),
        .gainRamp_TxGainOut(RFB_TxGain_ramped),

        .TxEn(RFB_TxEn),
        .PAEn(RFB_PAEn),
        .PHYStart(usr_RFB_PHYStart)
    );
    radio_controller_TxTiming RFC_txTiming (
        .clk(Bus2IP_Clk),
        .reset(Bus2IP_Reset),

        .clk_div(txTiming_clk_div_sel),

        .sw_start(RFC_txStart),

        .dly_GainRamp(TxTiming_dly_TxGainRamp),
        .dly_TxEn(TxTiming_dly_TxEn),
        .dly_PHYStart(TxTiming_dly_startPHY),
        .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn),

        .gainRamp_TxGainTarget(RFC_TxGain_target),
        .gainRamp_GainStep(TxGainRamp_gainStep),
        .gainRamp_TimeStep(TxGainRamp_timeStep),
        .gainRamp_TxGainOut(RFC_TxGain_ramped),

        .TxEn(RFC_TxEn),
        .PAEn(RFC_PAEn),
        .PHYStart(usr_RFC_PHYStart)
    );
    radio_controller_TxTiming RFD_txTiming (
        .clk(Bus2IP_Clk),
        .reset(Bus2IP_Reset),

        .clk_div(txTiming_clk_div_sel),

        .sw_start(RFD_txStart),

        .dly_GainRamp(TxTiming_dly_TxGainRamp),
        .dly_TxEn(TxTiming_dly_TxEn),
        .dly_PHYStart(TxTiming_dly_startPHY),
        .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn),

        .gainRamp_TxGainTarget(RFD_TxGain_target),
        .gainRamp_GainStep(TxGainRamp_gainStep),
        .gainRamp_TimeStep(TxGainRamp_timeStep),
        .gainRamp_TxGainOut(RFD_TxGain_ramped),

        .TxEn(RFD_TxEn),
        .PAEn(RFD_PAEn),
        .PHYStart(usr_RFD_PHYStart)
    );

    //Signals to detect when MAX2829 hardware reset occurs (TxEn=1, RxEn=1, SHDN=0)
    // Reset can be triggered by hardware or software, depending on the user config
    assign RFA_MAX2829_Reset = (RFA_TxEn & RFA_RxEn & ~RFA_SHDN);
    assign RFB_MAX2829_Reset = (RFB_TxEn & RFB_RxEn & ~RFB_SHDN);
    assign RFC_MAX2829_Reset = (RFC_TxEn & RFC_RxEn & ~RFC_SHDN);
    assign RFD_MAX2829_Reset = (RFD_TxEn & RFD_RxEn & ~RFD_SHDN);
    
    //Use a counter to generate a blinking error signal to indicate a radio in standby that hasn't yet locked
    reg [23:0] error_blink_counter = 24'b0;
    always @(posedge Bus2IP_Clk)
        error_blink_counter <= error_blink_counter + 1;

    assign usr_RFA_statLED_Tx = RFA_SHDN ? (RFA_TxEn | ((~RFA_LD) & error_blink_counter[23])) : 1'b0;
    assign usr_RFA_statLED_Rx = RFA_SHDN ? (RFA_RxEn | ((~RFA_LD) & error_blink_counter[23])) : 1'b0;;

    assign usr_RFB_statLED_Tx = RFB_SHDN ? (RFB_TxEn | ((~RFB_LD) & error_blink_counter[23])) : 1'b0;
    assign usr_RFB_statLED_Rx = RFB_SHDN ? (RFB_RxEn | ((~RFB_LD) & error_blink_counter[23])) : 1'b0;;

    assign usr_RFC_statLED_Tx = RFC_SHDN ? (RFC_TxEn | ((~RFC_LD) & error_blink_counter[23])) : 1'b0;
    assign usr_RFC_statLED_Rx = RFC_SHDN ? (RFC_RxEn | ((~RFC_LD) & error_blink_counter[23])) : 1'b0;;

    assign usr_RFD_statLED_Tx = RFD_SHDN ? (RFD_TxEn | ((~RFD_LD) & error_blink_counter[23])) : 1'b0;
    assign usr_RFD_statLED_Rx = RFD_SHDN ? (RFD_RxEn | ((~RFD_LD) & error_blink_counter[23])) : 1'b0;;
    
    
    //Mask per-RF path to enable SPI transactions
    // Driven by register for software control, usr_ port for hardware control
    assign spi_rfsel_mask = usr_SPI_ctrlSrc ? usr_SPI_rfsel : spi_rfsel_mask_sw;
    

    //Processes to update mirror registers following SPI write
    // Note these registers are *not* changed by a software reset
    // The only reset condition is the MAX2829 hardware reset (TxEn=1, RxEn=1, SHDN=0)
    always @(posedge Bus2IP_Clk)
    begin
        if(RFA_MAX2829_Reset)
        begin
            RFA_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET;
            RFA_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET;
            RFA_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET;
            RFA_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET;
            RFA_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET;
            RFA_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET;
            RFA_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET;
            RFA_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET;
            RFA_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET;
            RFA_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET;
            RFA_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET;
            RFA_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET;
            RFA_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET;
        end
        else if(spi_go)
        begin
            if(spi_rfsel_mask & 4'b0001) //RFA selected
                RFA_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata;
        end
    end

    always @(posedge Bus2IP_Clk)
    begin
        if(RFB_MAX2829_Reset)
        begin
            RFB_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET;
            RFB_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET;
            RFB_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET;
            RFB_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET;
            RFB_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET;
            RFB_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET;
            RFB_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET;
            RFB_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET;
            RFB_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET;
            RFB_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET;
            RFB_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET;
            RFB_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET;
            RFB_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET;
        end
        else if(spi_go)
        begin
            if(spi_rfsel_mask & 4'b0010) //RFB selected
                RFB_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata;
        end
    end

    always @(posedge Bus2IP_Clk)
    begin
        if(RFC_MAX2829_Reset)
        begin
            RFC_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET;
            RFC_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET;
            RFC_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET;
            RFC_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET;
            RFC_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET;
            RFC_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET;
            RFC_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET;
            RFC_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET;
            RFC_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET;
            RFC_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET;
            RFC_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET;
            RFC_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET;
            RFC_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET;
        end
        else if(spi_go)
        begin
            if(spi_rfsel_mask & 4'b0100) //RFC selected
                RFC_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata;
        end
    end

    always @(posedge Bus2IP_Clk)
    begin
        if(RFD_MAX2829_Reset)
        begin
            RFD_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET;
            RFD_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET;
            RFD_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET;
            RFD_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET;
            RFD_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET;
            RFD_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET;
            RFD_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET;
            RFD_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET;
            RFD_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET;
            RFD_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET;
            RFD_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET;
            RFD_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET;
            RFD_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET;
        end
        else if(spi_go)
        begin
            if(spi_rfsel_mask & 4'b1000) //RFD selected
                RFD_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata;
        end
    end
    
    //MAX2829 CS is active-low; warp_spi_io.spi_cs is active high
    assign RFA_SPI_CSn = ~(spi_rfsel_mask[3] & spi_cs);
    assign RFB_SPI_CSn = ~(spi_rfsel_mask[2] & spi_cs);
    assign RFC_SPI_CSn = ~(spi_rfsel_mask[1] & spi_cs);
    assign RFD_SPI_CSn = ~(spi_rfsel_mask[0] & spi_cs);
    
    assign RFA_SPI_MOSI = spi_mosi;
    assign RFB_SPI_MOSI = spi_mosi;
    assign RFC_SPI_MOSI = spi_mosi;
    assign RFD_SPI_MOSI = spi_mosi;

    //Mask each SCLK output by the corresponding CS
    // No point toggling SCLKs that will be ignored
    assign RFA_SPI_SCLK = (spi_sclk & spi_rfsel_mask[3]);
    assign RFB_SPI_SCLK = (spi_sclk & spi_rfsel_mask[2]);
    assign RFC_SPI_SCLK = (spi_sclk & spi_rfsel_mask[1]);
    assign RFD_SPI_SCLK = (spi_sclk & spi_rfsel_mask[0]);
        
    //MAX2829 SPI uses 18-bit transfers, formatted as {regData[0:13] regAddr[0:3]}, data and addr both transfer MSB first
    wire [0:17] spi_tx_data_word;
    assign spi_tx_data_word[0:17] = usr_SPI_ctrlSrc ? {usr_SPI_regdata, usr_SPI_regaddr} : {spi_tx_regdata, spi_tx_regaddr};

    assign spi_go = usr_SPI_ctrlSrc ? usr_SPI_go : spi_tx_reg_write;
    
    assign usr_SPI_active = spi_cs;
    
    warp_spi_io #(.SPI_XFER_LEN(18)) spi_io (
        .sys_clk(Bus2IP_Clk),
        .reset(Bus2IP_Reset),
        .go(spi_go),
        .done(spi_xfer_done),
        .clkDiv(spi_clk_div_sel),

        .currBitNum(),

        .txData({14'b0, spi_tx_data_word}),

        .rxData1(),
        .rxData2(),
        .rxData3(),
        .rxData4(),
        
        .spi_cs(spi_cs),
        .spi_sclk(spi_sclk),

        .spi_mosi(spi_mosi),
        
        .spi_miso1(1'b0),
        .spi_miso2(1'b0),
        .spi_miso3(1'b0),
        .spi_miso4(1'b0)
    );  
endmodule