Context Navigation

radio_controller.vhd

Last change on this file was 1766, checked in by murphpo, 12 years ago

File size: 32.8 KB

Line
1	------------------------------------------------------------------------------
2	-- radio_controller.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: radio_controller.vhd
36	-- Version: 3.00.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Wed Jul 04 20:55:56 2012 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68
69	library plbv46_slave_single_v1_01_a;
70	use plbv46_slave_single_v1_01_a.plbv46_slave_single;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_BASEADDR -- PLBv46 slave: base address
77	-- C_HIGHADDR -- PLBv46 slave: high address
78	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
79	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
80	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
81	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
82	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
83	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
84	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
85	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
86	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
87	-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
88	-- C_FAMILY -- Xilinx FPGA family
89	--
90	-- Definition of Ports:
91	-- SPLB_Clk -- PLB main bus clock
92	-- SPLB_Rst -- PLB main bus reset
93	-- PLB_ABus -- PLB address bus
94	-- PLB_UABus -- PLB upper address bus
95	-- PLB_PAValid -- PLB primary address valid indicator
96	-- PLB_SAValid -- PLB secondary address valid indicator
97	-- PLB_rdPrim -- PLB secondary to primary read request indicator
98	-- PLB_wrPrim -- PLB secondary to primary write request indicator
99	-- PLB_masterID -- PLB current master identifier
100	-- PLB_abort -- PLB abort request indicator
101	-- PLB_busLock -- PLB bus lock
102	-- PLB_RNW -- PLB read/not write
103	-- PLB_BE -- PLB byte enables
104	-- PLB_MSize -- PLB master data bus size
105	-- PLB_size -- PLB transfer size
106	-- PLB_type -- PLB transfer type
107	-- PLB_lockErr -- PLB lock error indicator
108	-- PLB_wrDBus -- PLB write data bus
109	-- PLB_wrBurst -- PLB burst write transfer indicator
110	-- PLB_rdBurst -- PLB burst read transfer indicator
111	-- PLB_wrPendReq -- PLB write pending bus request indicator
112	-- PLB_rdPendReq -- PLB read pending bus request indicator
113	-- PLB_wrPendPri -- PLB write pending request priority
114	-- PLB_rdPendPri -- PLB read pending request priority
115	-- PLB_reqPri -- PLB current request priority
116	-- PLB_TAttribute -- PLB transfer attribute
117	-- Sl_addrAck -- Slave address acknowledge
118	-- Sl_SSize -- Slave data bus size
119	-- Sl_wait -- Slave wait indicator
120	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
121	-- Sl_wrDAck -- Slave write data acknowledge
122	-- Sl_wrComp -- Slave write transfer complete indicator
123	-- Sl_wrBTerm -- Slave terminate write burst transfer
124	-- Sl_rdDBus -- Slave read data bus
125	-- Sl_rdWdAddr -- Slave read word address
126	-- Sl_rdDAck -- Slave read data acknowledge
127	-- Sl_rdComp -- Slave read transfer complete indicator
128	-- Sl_rdBTerm -- Slave terminate read burst transfer
129	-- Sl_MBusy -- Slave busy indicator
130	-- Sl_MWrErr -- Slave write error indicator
131	-- Sl_MRdErr -- Slave read error indicator
132	-- Sl_MIRQ -- Slave interrupt indicator
133	------------------------------------------------------------------------------
134
135	entity radio_controller is
136	generic
137	(
138	-- ADD USER GENERICS BELOW THIS LINE ---------------
139	--USER generics added here
140	-- ADD USER GENERICS ABOVE THIS LINE ---------------
141
142	-- DO NOT EDIT BELOW THIS LINE ---------------------
143	-- Bus protocol parameters, do not add to or delete
144	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
145	C_HIGHADDR : std_logic_vector := X"00000000";
146	C_SPLB_AWIDTH : integer := 32;
147	C_SPLB_DWIDTH : integer := 128;
148	C_SPLB_NUM_MASTERS : integer := 8;
149	C_SPLB_MID_WIDTH : integer := 3;
150	C_SPLB_NATIVE_DWIDTH : integer := 32;
151	C_SPLB_P2P : integer := 0;
152	C_SPLB_SUPPORT_BURSTS : integer := 0;
153	C_SPLB_SMALLEST_MASTER : integer := 32;
154	C_SPLB_CLK_PERIOD_PS : integer := 10000;
155	C_INCLUDE_DPHASE_TIMER : integer := 0;
156	C_FAMILY : string := "virtex6"
157	-- DO NOT EDIT ABOVE THIS LINE ---------------------
158	);
159	port
160	(
161	-- ADD USER PORTS BELOW THIS LINE ------------------
162	RFA_TxEn : out std_logic;
163	RFB_TxEn : out std_logic;
164	RFC_TxEn : out std_logic;
165	RFD_TxEn : out std_logic;
166
167	RFA_RxEn : out std_logic;
168	RFB_RxEn : out std_logic;
169	RFC_RxEn : out std_logic;
170	RFD_RxEn : out std_logic;
171
172	RFA_RxHP : out std_logic;
173	RFB_RxHP : out std_logic;
174	RFC_RxHP : out std_logic;
175	RFD_RxHP : out std_logic;
176
177	RFA_SHDN : out std_logic;
178	RFB_SHDN : out std_logic;
179	RFC_SHDN : out std_logic;
180	RFD_SHDN : out std_logic;
181
182	RFA_SPI_SCLK : out std_logic;
183	RFB_SPI_SCLK : out std_logic;
184	RFC_SPI_SCLK : out std_logic;
185	RFD_SPI_SCLK : out std_logic;
186
187	RFA_SPI_MOSI : out std_logic;
188	RFB_SPI_MOSI : out std_logic;
189	RFC_SPI_MOSI : out std_logic;
190	RFD_SPI_MOSI : out std_logic;
191
192	RFA_SPI_CSn : out std_logic;
193	RFB_SPI_CSn : out std_logic;
194	RFC_SPI_CSn : out std_logic;
195	RFD_SPI_CSn : out std_logic;
196
197	RFA_B : out std_logic_vector(0 to 6);
198	RFB_B : out std_logic_vector(0 to 6);
199	RFC_B : out std_logic_vector(0 to 6);
200	RFD_B : out std_logic_vector(0 to 6);
201
202	RFA_LD : in std_logic;
203	RFB_LD : in std_logic;
204	RFC_LD : in std_logic;
205	RFD_LD : in std_logic;
206
207	RFA_PAEn_24 : out std_logic;
208	RFB_PAEn_24 : out std_logic;
209	RFC_PAEn_24 : out std_logic;
210	RFD_PAEn_24 : out std_logic;
211
212	RFA_PAEn_5 : out std_logic;
213	RFB_PAEn_5 : out std_logic;
214	RFC_PAEn_5 : out std_logic;
215	RFD_PAEn_5 : out std_logic;
216
217	RFA_AntSw : out std_logic_vector(0 to 1);
218	RFB_AntSw : out std_logic_vector(0 to 1);
219	RFC_AntSw : out std_logic_vector(0 to 1);
220	RFD_AntSw : out std_logic_vector(0 to 1);
221
222	usr_RFA_TxEn : in std_logic;
223	usr_RFB_TxEn : in std_logic;
224	usr_RFC_TxEn : in std_logic;
225	usr_RFD_TxEn : in std_logic;
226
227	usr_RFA_RxEn : in std_logic;
228	usr_RFB_RxEn : in std_logic;
229	usr_RFC_RxEn : in std_logic;
230	usr_RFD_RxEn : in std_logic;
231
232	usr_RFA_RxHP : in std_logic;
233	usr_RFB_RxHP : in std_logic;
234	usr_RFC_RxHP : in std_logic;
235	usr_RFD_RxHP : in std_logic;
236
237	usr_RFA_SHDN : in std_logic;
238	usr_RFB_SHDN : in std_logic;
239	usr_RFC_SHDN : in std_logic;
240	usr_RFD_SHDN : in std_logic;
241
242	usr_RFA_RxGainRF : in std_logic_vector(0 to 1);
243	usr_RFB_RxGainRF : in std_logic_vector(0 to 1);
244	usr_RFC_RxGainRF : in std_logic_vector(0 to 1);
245	usr_RFD_RxGainRF : in std_logic_vector(0 to 1);
246
247	usr_RFA_RxGainBB : in std_logic_vector(0 to 4);
248	usr_RFB_RxGainBB : in std_logic_vector(0 to 4);
249	usr_RFC_RxGainBB : in std_logic_vector(0 to 4);
250	usr_RFD_RxGainBB : in std_logic_vector(0 to 4);
251
252	usr_RFA_TxGain : in std_logic_vector(0 to 5);
253	usr_RFB_TxGain : in std_logic_vector(0 to 5);
254	usr_RFC_TxGain : in std_logic_vector(0 to 5);
255	usr_RFD_TxGain : in std_logic_vector(0 to 5);
256
257	usr_SPI_ctrlSrc : in std_logic;
258	usr_SPI_go : in std_logic;
259	usr_SPI_active : out std_logic;
260	usr_SPI_rfsel : in std_logic_vector(0 to 3);
261	usr_SPI_regaddr : in std_logic_vector(0 to 3);
262	usr_SPI_regdata : in std_logic_vector(0 to 13);
263
264	usr_RFA_PHYStart : out std_logic;
265	usr_RFB_PHYStart : out std_logic;
266	usr_RFC_PHYStart : out std_logic;
267	usr_RFD_PHYStart : out std_logic;
268
269	usr_any_PHYStart : out std_logic;
270
271	usr_RFA_statLED_Tx : out std_logic;
272	usr_RFA_statLED_Rx : out std_logic;
273	usr_RFB_statLED_Tx : out std_logic;
274	usr_RFB_statLED_Rx : out std_logic;
275	usr_RFC_statLED_Tx : out std_logic;
276	usr_RFC_statLED_Rx : out std_logic;
277	usr_RFD_statLED_Tx : out std_logic;
278	usr_RFD_statLED_Rx : out std_logic;
279
280	-- ADD USER PORTS ABOVE THIS LINE ------------------
281
282	-- DO NOT EDIT BELOW THIS LINE ---------------------
283	-- Bus protocol ports, do not add to or delete
284	SPLB_Clk : in std_logic;
285	SPLB_Rst : in std_logic;
286	PLB_ABus : in std_logic_vector(0 to 31);
287	PLB_UABus : in std_logic_vector(0 to 31);
288	PLB_PAValid : in std_logic;
289	PLB_SAValid : in std_logic;
290	PLB_rdPrim : in std_logic;
291	PLB_wrPrim : in std_logic;
292	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
293	PLB_abort : in std_logic;
294	PLB_busLock : in std_logic;
295	PLB_RNW : in std_logic;
296	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
297	PLB_MSize : in std_logic_vector(0 to 1);
298	PLB_size : in std_logic_vector(0 to 3);
299	PLB_type : in std_logic_vector(0 to 2);
300	PLB_lockErr : in std_logic;
301	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
302	PLB_wrBurst : in std_logic;
303	PLB_rdBurst : in std_logic;
304	PLB_wrPendReq : in std_logic;
305	PLB_rdPendReq : in std_logic;
306	PLB_wrPendPri : in std_logic_vector(0 to 1);
307	PLB_rdPendPri : in std_logic_vector(0 to 1);
308	PLB_reqPri : in std_logic_vector(0 to 1);
309	PLB_TAttribute : in std_logic_vector(0 to 15);
310	Sl_addrAck : out std_logic;
311	Sl_SSize : out std_logic_vector(0 to 1);
312	Sl_wait : out std_logic;
313	Sl_rearbitrate : out std_logic;
314	Sl_wrDAck : out std_logic;
315	Sl_wrComp : out std_logic;
316	Sl_wrBTerm : out std_logic;
317	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
318	Sl_rdWdAddr : out std_logic_vector(0 to 3);
319	Sl_rdDAck : out std_logic;
320	Sl_rdComp : out std_logic;
321	Sl_rdBTerm : out std_logic;
322	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
323	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
324	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
325	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
326	-- DO NOT EDIT ABOVE THIS LINE ---------------------
327	);
328
329	attribute MAX_FANOUT : string;
330	attribute SIGIS : string;
331
332	attribute SIGIS of SPLB_Clk : signal is "CLK";
333	attribute SIGIS of SPLB_Rst : signal is "RST";
334
335	end entity radio_controller;
336
337	------------------------------------------------------------------------------
338	-- Architecture section
339	------------------------------------------------------------------------------
340
341	architecture IMP of radio_controller is
342
343	------------------------------------------
344	-- Array of base/high address pairs for each address range
345	------------------------------------------
346	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
347	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
348	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
349
350	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
351	(
352	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
353	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
354	);
355
356	------------------------------------------
357	-- Array of desired number of chip enables for each address range
358	------------------------------------------
359	constant USER_SLV_NUM_REG : integer := 64;
360	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
361
362	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
363	(
364	0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
365	);
366
367	------------------------------------------
368	-- Ratio of bus clock to core clock (for use in dual clock systems)
369	-- 1 = ratio is 1:1
370	-- 2 = ratio is 2:1
371	------------------------------------------
372	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
373
374	------------------------------------------
375	-- Width of the slave data bus (32 only)
376	------------------------------------------
377	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
378
379	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
380
381	------------------------------------------
382	-- Index for CS/CE
383	------------------------------------------
384	constant USER_SLV_CS_INDEX : integer := 0;
385	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
386
387	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
388
389	------------------------------------------
390	-- IP Interconnect (IPIC) signal declarations
391	------------------------------------------
392	signal ipif_Bus2IP_Clk : std_logic;
393	signal ipif_Bus2IP_Reset : std_logic;
394	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
395	signal ipif_IP2Bus_WrAck : std_logic;
396	signal ipif_IP2Bus_RdAck : std_logic;
397	signal ipif_IP2Bus_Error : std_logic;
398	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
399	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
400	signal ipif_Bus2IP_RNW : std_logic;
401	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
402	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
403	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
404	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
405	signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
406	signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
407	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
408	signal user_IP2Bus_RdAck : std_logic;
409	signal user_IP2Bus_WrAck : std_logic;
410	signal user_IP2Bus_Error : std_logic;
411
412	------------------------------------------
413	-- Component declaration for verilog user logic
414	------------------------------------------
415	component user_logic is
416	generic
417	(
418	-- ADD USER GENERICS BELOW THIS LINE ---------------
419	--USER generics added here
420	-- ADD USER GENERICS ABOVE THIS LINE ---------------
421
422	-- DO NOT EDIT BELOW THIS LINE ---------------------
423	-- Bus protocol parameters, do not add to or delete
424	C_SLV_DWIDTH : integer := 32;
425	C_NUM_REG : integer := 64
426	-- DO NOT EDIT ABOVE THIS LINE ---------------------
427	);
428	port
429	(
430	-- ADD USER PORTS BELOW THIS LINE ------------------
431	RFA_TxEn : out std_logic;
432	RFB_TxEn : out std_logic;
433	RFC_TxEn : out std_logic;
434	RFD_TxEn : out std_logic;
435
436	RFA_RxEn : out std_logic;
437	RFB_RxEn : out std_logic;
438	RFC_RxEn : out std_logic;
439	RFD_RxEn : out std_logic;
440
441	RFA_RxHP : out std_logic;
442	RFB_RxHP : out std_logic;
443	RFC_RxHP : out std_logic;
444	RFD_RxHP : out std_logic;
445
446	RFA_SHDN : out std_logic;
447	RFB_SHDN : out std_logic;
448	RFC_SHDN : out std_logic;
449	RFD_SHDN : out std_logic;
450
451	RFA_SPI_SCLK : out std_logic;
452	RFB_SPI_SCLK : out std_logic;
453	RFC_SPI_SCLK : out std_logic;
454	RFD_SPI_SCLK : out std_logic;
455
456	RFA_SPI_MOSI : out std_logic;
457	RFB_SPI_MOSI : out std_logic;
458	RFC_SPI_MOSI : out std_logic;
459	RFD_SPI_MOSI : out std_logic;
460
461	RFA_SPI_CSn : out std_logic;
462	RFB_SPI_CSn : out std_logic;
463	RFC_SPI_CSn : out std_logic;
464	RFD_SPI_CSn : out std_logic;
465
466	RFA_B : out std_logic_vector(0 to 6);
467	RFB_B : out std_logic_vector(0 to 6);
468	RFC_B : out std_logic_vector(0 to 6);
469	RFD_B : out std_logic_vector(0 to 6);
470
471	RFA_LD : in std_logic;
472	RFB_LD : in std_logic;
473	RFC_LD : in std_logic;
474	RFD_LD : in std_logic;
475
476	RFA_PAEn_24 : out std_logic;
477	RFB_PAEn_24 : out std_logic;
478	RFC_PAEn_24 : out std_logic;
479	RFD_PAEn_24 : out std_logic;
480
481	RFA_PAEn_5 : out std_logic;
482	RFB_PAEn_5 : out std_logic;
483	RFC_PAEn_5 : out std_logic;
484	RFD_PAEn_5 : out std_logic;
485
486	RFA_AntSw : out std_logic_vector(0 to 1);
487	RFB_AntSw : out std_logic_vector(0 to 1);
488	RFC_AntSw : out std_logic_vector(0 to 1);
489	RFD_AntSw : out std_logic_vector(0 to 1);
490
491	usr_RFA_TxEn : in std_logic;
492	usr_RFB_TxEn : in std_logic;
493	usr_RFC_TxEn : in std_logic;
494	usr_RFD_TxEn : in std_logic;
495
496	usr_RFA_RxEn : in std_logic;
497	usr_RFB_RxEn : in std_logic;
498	usr_RFC_RxEn : in std_logic;
499	usr_RFD_RxEn : in std_logic;
500
501	usr_RFA_RxHP : in std_logic;
502	usr_RFB_RxHP : in std_logic;
503	usr_RFC_RxHP : in std_logic;
504	usr_RFD_RxHP : in std_logic;
505
506	usr_RFA_SHDN : in std_logic;
507	usr_RFB_SHDN : in std_logic;
508	usr_RFC_SHDN : in std_logic;
509	usr_RFD_SHDN : in std_logic;
510
511	usr_RFA_RxGainRF : in std_logic_vector(0 to 1);
512	usr_RFB_RxGainRF : in std_logic_vector(0 to 1);
513	usr_RFC_RxGainRF : in std_logic_vector(0 to 1);
514	usr_RFD_RxGainRF : in std_logic_vector(0 to 1);
515
516	usr_RFA_RxGainBB : in std_logic_vector(0 to 4);
517	usr_RFB_RxGainBB : in std_logic_vector(0 to 4);
518	usr_RFC_RxGainBB : in std_logic_vector(0 to 4);
519	usr_RFD_RxGainBB : in std_logic_vector(0 to 4);
520
521	usr_RFA_TxGain : in std_logic_vector(0 to 5);
522	usr_RFB_TxGain : in std_logic_vector(0 to 5);
523	usr_RFC_TxGain : in std_logic_vector(0 to 5);
524	usr_RFD_TxGain : in std_logic_vector(0 to 5);
525
526	usr_SPI_ctrlSrc : in std_logic;
527	usr_SPI_go : in std_logic;
528	usr_SPI_active : out std_logic;
529	usr_SPI_rfsel : in std_logic_vector(0 to 3);
530	usr_SPI_regaddr : in std_logic_vector(0 to 3);
531	usr_SPI_regdata : in std_logic_vector(0 to 13);
532
533	usr_RFA_PHYStart : out std_logic;
534	usr_RFB_PHYStart : out std_logic;
535	usr_RFC_PHYStart : out std_logic;
536	usr_RFD_PHYStart : out std_logic;
537
538	usr_any_PHYStart : out std_logic;
539
540	usr_RFA_statLED_Tx : out std_logic;
541	usr_RFA_statLED_Rx : out std_logic;
542	usr_RFB_statLED_Tx : out std_logic;
543	usr_RFB_statLED_Rx : out std_logic;
544	usr_RFC_statLED_Tx : out std_logic;
545	usr_RFC_statLED_Rx : out std_logic;
546	usr_RFD_statLED_Tx : out std_logic;
547	usr_RFD_statLED_Rx : out std_logic;
548
549	-- ADD USER PORTS ABOVE THIS LINE ------------------
550
551	-- DO NOT EDIT BELOW THIS LINE ---------------------
552	-- Bus protocol ports, do not add to or delete
553	Bus2IP_Clk : in std_logic;
554	Bus2IP_Reset : in std_logic;
555	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
556	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
557	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
558	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
559	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
560	IP2Bus_RdAck : out std_logic;
561	IP2Bus_WrAck : out std_logic;
562	IP2Bus_Error : out std_logic
563	-- DO NOT EDIT ABOVE THIS LINE ---------------------
564	);
565	end component user_logic;
566
567	begin
568
569	------------------------------------------
570	-- instantiate plbv46_slave_single
571	------------------------------------------
572	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
573	generic map
574	(
575	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
576	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
577	C_SPLB_P2P => C_SPLB_P2P,
578	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
579	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
580	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
581	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
582	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
583	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
584	C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
585	C_FAMILY => C_FAMILY
586	)
587	port map
588	(
589	SPLB_Clk => SPLB_Clk,
590	SPLB_Rst => SPLB_Rst,
591	PLB_ABus => PLB_ABus,
592	PLB_UABus => PLB_UABus,
593	PLB_PAValid => PLB_PAValid,
594	PLB_SAValid => PLB_SAValid,
595	PLB_rdPrim => PLB_rdPrim,
596	PLB_wrPrim => PLB_wrPrim,
597	PLB_masterID => PLB_masterID,
598	PLB_abort => PLB_abort,
599	PLB_busLock => PLB_busLock,
600	PLB_RNW => PLB_RNW,
601	PLB_BE => PLB_BE,
602	PLB_MSize => PLB_MSize,
603	PLB_size => PLB_size,
604	PLB_type => PLB_type,
605	PLB_lockErr => PLB_lockErr,
606	PLB_wrDBus => PLB_wrDBus,
607	PLB_wrBurst => PLB_wrBurst,
608	PLB_rdBurst => PLB_rdBurst,
609	PLB_wrPendReq => PLB_wrPendReq,
610	PLB_rdPendReq => PLB_rdPendReq,
611	PLB_wrPendPri => PLB_wrPendPri,
612	PLB_rdPendPri => PLB_rdPendPri,
613	PLB_reqPri => PLB_reqPri,
614	PLB_TAttribute => PLB_TAttribute,
615	Sl_addrAck => Sl_addrAck,
616	Sl_SSize => Sl_SSize,
617	Sl_wait => Sl_wait,
618	Sl_rearbitrate => Sl_rearbitrate,
619	Sl_wrDAck => Sl_wrDAck,
620	Sl_wrComp => Sl_wrComp,
621	Sl_wrBTerm => Sl_wrBTerm,
622	Sl_rdDBus => Sl_rdDBus,
623	Sl_rdWdAddr => Sl_rdWdAddr,
624	Sl_rdDAck => Sl_rdDAck,
625	Sl_rdComp => Sl_rdComp,
626	Sl_rdBTerm => Sl_rdBTerm,
627	Sl_MBusy => Sl_MBusy,
628	Sl_MWrErr => Sl_MWrErr,
629	Sl_MRdErr => Sl_MRdErr,
630	Sl_MIRQ => Sl_MIRQ,
631	Bus2IP_Clk => ipif_Bus2IP_Clk,
632	Bus2IP_Reset => ipif_Bus2IP_Reset,
633	IP2Bus_Data => ipif_IP2Bus_Data,
634	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
635	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
636	IP2Bus_Error => ipif_IP2Bus_Error,
637	Bus2IP_Addr => ipif_Bus2IP_Addr,
638	Bus2IP_Data => ipif_Bus2IP_Data,
639	Bus2IP_RNW => ipif_Bus2IP_RNW,
640	Bus2IP_BE => ipif_Bus2IP_BE,
641	Bus2IP_CS => ipif_Bus2IP_CS,
642	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
643	Bus2IP_WrCE => ipif_Bus2IP_WrCE
644	);
645
646	------------------------------------------
647	-- instantiate User Logic
648	------------------------------------------
649	USER_LOGIC_I : component user_logic
650	generic map
651	(
652	-- MAP USER GENERICS BELOW THIS LINE ---------------
653	--USER generics mapped here
654	-- MAP USER GENERICS ABOVE THIS LINE ---------------
655
656	C_SLV_DWIDTH => USER_SLV_DWIDTH,
657	C_NUM_REG => USER_NUM_REG
658	)
659	port map
660	(
661	-- MAP USER PORTS BELOW THIS LINE ------------------
662	RFA_TxEn => RFA_TxEn,
663	RFB_TxEn => RFB_TxEn,
664	RFC_TxEn => RFC_TxEn,
665	RFD_TxEn => RFD_TxEn,
666
667	RFA_RxEn => RFA_RxEn,
668	RFB_RxEn => RFB_RxEn,
669	RFC_RxEn => RFC_RxEn,
670	RFD_RxEn => RFD_RxEn,
671
672	RFA_RxHP => RFA_RxHP,
673	RFB_RxHP => RFB_RxHP,
674	RFC_RxHP => RFC_RxHP,
675	RFD_RxHP => RFD_RxHP,
676
677	RFA_SHDN => RFA_SHDN,
678	RFB_SHDN => RFB_SHDN,
679	RFC_SHDN => RFC_SHDN,
680	RFD_SHDN => RFD_SHDN,
681
682	RFA_SPI_SCLK => RFA_SPI_SCLK,
683	RFB_SPI_SCLK => RFB_SPI_SCLK,
684	RFC_SPI_SCLK => RFC_SPI_SCLK,
685	RFD_SPI_SCLK => RFD_SPI_SCLK,
686
687	RFA_SPI_MOSI => RFA_SPI_MOSI,
688	RFB_SPI_MOSI => RFB_SPI_MOSI,
689	RFC_SPI_MOSI => RFC_SPI_MOSI,
690	RFD_SPI_MOSI => RFD_SPI_MOSI,
691
692	RFA_SPI_CSn => RFA_SPI_CSn,
693	RFB_SPI_CSn => RFB_SPI_CSn,
694	RFC_SPI_CSn => RFC_SPI_CSn,
695	RFD_SPI_CSn => RFD_SPI_CSn,
696
697	RFA_B => RFA_B,
698	RFB_B => RFB_B,
699	RFC_B => RFC_B,
700	RFD_B => RFD_B,
701
702	RFA_LD => RFA_LD,
703	RFB_LD => RFB_LD,
704	RFC_LD => RFC_LD,
705	RFD_LD => RFD_LD,
706
707	RFA_PAEn_24 => RFA_PAEn_24,
708	RFB_PAEn_24 => RFB_PAEn_24,
709	RFC_PAEn_24 => RFC_PAEn_24,
710	RFD_PAEn_24 => RFD_PAEn_24,
711
712	RFA_PAEn_5 => RFA_PAEn_5,
713	RFB_PAEn_5 => RFB_PAEn_5,
714	RFC_PAEn_5 => RFC_PAEn_5,
715	RFD_PAEn_5 => RFD_PAEn_5,
716
717	RFA_AntSw => RFA_AntSw,
718	RFB_AntSw => RFB_AntSw,
719	RFC_AntSw => RFC_AntSw,
720	RFD_AntSw => RFD_AntSw,
721
722	usr_RFA_TxEn => usr_RFA_TxEn,
723	usr_RFB_TxEn => usr_RFB_TxEn,
724	usr_RFC_TxEn => usr_RFC_TxEn,
725	usr_RFD_TxEn => usr_RFD_TxEn,
726
727	usr_RFA_RxEn => usr_RFA_RxEn,
728	usr_RFB_RxEn => usr_RFB_RxEn,
729	usr_RFC_RxEn => usr_RFC_RxEn,
730	usr_RFD_RxEn => usr_RFD_RxEn,
731
732	usr_RFA_RxHP => usr_RFA_RxHP,
733	usr_RFB_RxHP => usr_RFB_RxHP,
734	usr_RFC_RxHP => usr_RFC_RxHP,
735	usr_RFD_RxHP => usr_RFD_RxHP,
736
737	usr_RFA_SHDN => usr_RFA_SHDN,
738	usr_RFB_SHDN => usr_RFB_SHDN,
739	usr_RFC_SHDN => usr_RFC_SHDN,
740	usr_RFD_SHDN => usr_RFD_SHDN,
741
742	usr_RFA_RxGainRF => usr_RFA_RxGainRF,
743	usr_RFB_RxGainRF => usr_RFB_RxGainRF,
744	usr_RFC_RxGainRF => usr_RFC_RxGainRF,
745	usr_RFD_RxGainRF => usr_RFD_RxGainRF,
746
747	usr_RFA_RxGainBB => usr_RFA_RxGainBB,
748	usr_RFB_RxGainBB => usr_RFB_RxGainBB,
749	usr_RFC_RxGainBB => usr_RFC_RxGainBB,
750	usr_RFD_RxGainBB => usr_RFD_RxGainBB,
751
752	usr_RFA_TxGain => usr_RFA_TxGain,
753	usr_RFB_TxGain => usr_RFB_TxGain,
754	usr_RFC_TxGain => usr_RFC_TxGain,
755	usr_RFD_TxGain => usr_RFD_TxGain,
756
757	usr_SPI_ctrlSrc => usr_SPI_ctrlSrc,
758	usr_SPI_go => usr_SPI_go,
759	usr_SPI_active => usr_SPI_active,
760	usr_SPI_rfsel => usr_SPI_rfsel,
761	usr_SPI_regaddr => usr_SPI_regaddr,
762	usr_SPI_regdata => usr_SPI_regdata,
763
764	usr_RFA_PHYStart => usr_RFA_PHYStart,
765	usr_RFB_PHYStart => usr_RFB_PHYStart,
766	usr_RFC_PHYStart => usr_RFC_PHYStart,
767	usr_RFD_PHYStart => usr_RFD_PHYStart,
768
769	usr_any_PHYStart => usr_any_PHYStart,
770
771	usr_RFA_statLED_Tx => usr_RFA_statLED_Tx,
772	usr_RFA_statLED_Rx => usr_RFA_statLED_Rx,
773	usr_RFB_statLED_Tx => usr_RFB_statLED_Tx,
774	usr_RFB_statLED_Rx => usr_RFB_statLED_Rx,
775	usr_RFC_statLED_Tx => usr_RFC_statLED_Tx,
776	usr_RFC_statLED_Rx => usr_RFC_statLED_Rx,
777	usr_RFD_statLED_Tx => usr_RFD_statLED_Tx,
778	usr_RFD_statLED_Rx => usr_RFD_statLED_Rx,
779
780	-- MAP USER PORTS ABOVE THIS LINE ------------------
781
782	Bus2IP_Clk => ipif_Bus2IP_Clk,
783	Bus2IP_Reset => ipif_Bus2IP_Reset,
784	Bus2IP_Data => ipif_Bus2IP_Data,
785	Bus2IP_BE => ipif_Bus2IP_BE,
786	Bus2IP_RdCE => user_Bus2IP_RdCE,
787	Bus2IP_WrCE => user_Bus2IP_WrCE,
788	IP2Bus_Data => user_IP2Bus_Data,
789	IP2Bus_RdAck => user_IP2Bus_RdAck,
790	IP2Bus_WrAck => user_IP2Bus_WrAck,
791	IP2Bus_Error => user_IP2Bus_Error
792	);
793
794	------------------------------------------
795	-- connect internal signals
796	------------------------------------------
797	ipif_IP2Bus_Data <= user_IP2Bus_Data;
798	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
799	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
800	ipif_IP2Bus_Error <= user_IP2Bus_Error;
801
802	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
803	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
804
805	end IMP;

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: PlatformSupport/CustomPeripherals/pcores/radio_controller_v3_00_b/hdl/vhdl/radio_controller.vhd

Download in other formats: