source: PlatformSupport/CustomPeripherals/pcores/simple_spi_v1_00_a/hdl/verilog/user_logic.v

//----------------------------------------------------------------------------
// user_logic.v - module
//----------------------------------------------------------------------------
// ***************************************************************************
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// **                                                                       **
// ** Xilinx, Inc.                                                          **
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// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename:          user_logic.v
// Version:           3.01.a
// Description:       User logic module.
// Date:              Sat Feb 23 21:53:35 2013 (by Create and Import Peripheral Wizard)
// Verilog Standard:  Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
//   active low signals:                    "*_n"
//   clock signals:                         "clk", "clk_div#", "clk_#x"
//   reset signals:                         "rst", "rst_n"
//   generics:                              "C_*"
//   user defined types:                    "*_TYPE"
//   state machine next state:              "*_ns"
//   state machine current state:           "*_cs"
//   combinatorial signals:                 "*_com"
//   pipelined or register delay signals:   "*_d#"
//   counter signals:                       "*cnt*"
//   clock enable signals:                  "*_ce"
//   internal version of output port:       "*_i"
//   device pins:                           "*_pin"
//   ports:                                 "- Names begin with Uppercase"
//   processes:                             "*_PROCESS"
//   component instantiations:              "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------

`uselib lib=unisims_ver
`uselib lib=proc_common_v3_00_a

module user_logic
(
  // -- ADD USER PORTS BELOW THIS LINE ---------------
    spi_sclk,
    spi_mosi,
    spi_miso,
    spi_cs_n,
    
    spi_enable_n,
    cfg_req_n,
    cfg_sel,
    
  // -- ADD USER PORTS ABOVE THIS LINE ---------------

  // -- DO NOT EDIT BELOW THIS LINE ------------------
  // -- Bus protocol ports, do not add to or delete 
  Bus2IP_Clk,                     // Bus to IP clock
  Bus2IP_Resetn,                  // Bus to IP reset
  Bus2IP_Data,                    // Bus to IP data bus
  Bus2IP_BE,                      // Bus to IP byte enables
  Bus2IP_RdCE,                    // Bus to IP read chip enable
  Bus2IP_WrCE,                    // Bus to IP write chip enable
  IP2Bus_Data,                    // IP to Bus data bus
  IP2Bus_RdAck,                   // IP to Bus read transfer acknowledgement
  IP2Bus_WrAck,                   // IP to Bus write transfer acknowledgement
  IP2Bus_Error                    // IP to Bus error response
  // -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic

// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here 
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------

// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_NUM_REG                      = 8;
parameter C_SLV_DWIDTH                   = 32;
// -- DO NOT EDIT ABOVE THIS LINE --------------------

// -- ADD USER PORTS BELOW THIS LINE -----------------

output  spi_sclk;
output  spi_mosi;
input   spi_miso;
output  spi_cs_n;
output  spi_enable_n;
output  cfg_req_n;
output [2:0] cfg_sel;

// -- ADD USER PORTS ABOVE THIS LINE -----------------

// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input                                     Bus2IP_Clk;
input                                     Bus2IP_Resetn;
input      [C_SLV_DWIDTH-1 : 0]           Bus2IP_Data;
input      [C_SLV_DWIDTH/8-1 : 0]         Bus2IP_BE;
input      [C_NUM_REG-1 : 0]              Bus2IP_RdCE;
input      [C_NUM_REG-1 : 0]              Bus2IP_WrCE;
output     [C_SLV_DWIDTH-1 : 0]           IP2Bus_Data;
output                                    IP2Bus_RdAck;
output                                    IP2Bus_WrAck;
output                                    IP2Bus_Error;
// -- DO NOT EDIT ABOVE THIS LINE --------------------

//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------

  // --USER nets declarations added here, as needed for user logic

  // Nets for user logic slave model s/w accessible register example
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg0;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg1;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg2;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg3;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg4;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg5;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg6;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg7;
  wire       [7 : 0]                        slv_reg_write_sel;
  wire       [7 : 0]                        slv_reg_read_sel;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_ip2bus_data;
  wire                                      slv_read_ack;
  wire                                      slv_write_ack;
  integer                                   byte_index, bit_index;

  // USER logic implementation added here

  // ------------------------------------------------------
  // Example code to read/write user logic slave model s/w accessible registers
  // 
  // Note:
  // The example code presented here is to show you one way of reading/writing
  // software accessible registers implemented in the user logic slave model.
  // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  // to one software accessible register by the top level template. For example,
  // if you have four 32 bit software accessible registers in the user logic,
  // you are basically operating on the following memory mapped registers:
  // 
  //    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  //                     "1000"   C_BASEADDR + 0x0
  //                     "0100"   C_BASEADDR + 0x4
  //                     "0010"   C_BASEADDR + 0x8
  //                     "0001"   C_BASEADDR + 0xC
  // 
  // ------------------------------------------------------

    wire [7:0] spi_rx_byte;

    assign slv_reg_write_sel = Bus2IP_WrCE[7:0];
    assign slv_reg_read_sel  = Bus2IP_RdCE[7:0];

    //Removed [6] from _ack list, so slv_reg1 ack can be delayed following write to SPI Tx register
    assign slv_write_ack     = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[7];
    assign slv_read_ack      = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7];

  // implement slave model register(s)
  always @( posedge Bus2IP_Clk )
    begin

      if ( Bus2IP_Resetn == 1'b0 )
        begin
          slv_reg0 <= 0;
          slv_reg1 <= 0;
          slv_reg2 <= 0;
          slv_reg3 <= 0;
          slv_reg4 <= 0;
          slv_reg5 <= 0;
          slv_reg6 <= 0;
          slv_reg7 <= 0;
        end
      else
        case ( slv_reg_write_sel )
          8'b10000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          8'b01000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          8'b00100000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          8'b00010000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          8'b00001000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          8'b00000100 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          8'b00000010 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          8'b00000001 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          default : begin
            slv_reg0 <= slv_reg0;
            slv_reg1 <= slv_reg1;
            slv_reg2 <= slv_reg2;
            slv_reg3 <= slv_reg3;
            slv_reg4 <= slv_reg4;
            slv_reg5 <= slv_reg5;
            slv_reg6 <= slv_reg6;
            slv_reg7 <= slv_reg7;
                    end
        endcase

    end // SLAVE_REG_WRITE_PROC

  // implement slave model register read mux
  always @*
    begin 

      case ( slv_reg_read_sel )
        8'b10000000 : slv_ip2bus_data <= slv_reg0;
        8'b01000000 : slv_ip2bus_data <= slv_reg1;
        8'b00100000 : slv_ip2bus_data <= spi_rxData;
        8'b00010000 : slv_ip2bus_data <= slv_reg3;
        8'b00001000 : slv_ip2bus_data <= slv_reg4;
        8'b00000100 : slv_ip2bus_data <= slv_reg5;
        8'b00000010 : slv_ip2bus_data <= slv_reg6;
        8'b00000001 : slv_ip2bus_data <= slv_reg7;
        default : slv_ip2bus_data <= 0;
      endcase

    end // SLAVE_REG_READ_PROC

  // ------------------------------------------------------------
  // Example code to drive IP to Bus signals
  // ------------------------------------------------------------

  assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data :  0 ;
//  assign IP2Bus_WrAck   = slv_write_ack; //Overridden below
  assign IP2Bus_RdAck = slv_read_ack;
  assign IP2Bus_Error = 0;

    /* Address map:
        HDL is coded [MSB:LSB] = [31:0]
        regX[31]  maps to 0x80000000 in C driver
        regX[0] maps to 0x00000001 in C driver

    0: Config:
        [ 3: 0] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x0000000F
        [30:10] Reserved 
        [   31] Chip select

    1: SPI Tx
        [ 7: 0] Tx data byte
        [31: 8] Reserved
    
    2: SPI Rx: {samp_rxByte, 24'b0}
        [ 7: 0] SPI Rx byte
        [31: 8] Reserved 0xFFFFFF00

    3: FPGA config control:
        [    0] SPI Enable (inverted below - reg active high, output active low) - gives FPGA SPI master control of SD card
        [    1] Config request (inverted below - reg active high, output active low) - asserting this bit will reconfigure FPGA!
        [ 7: 2] Reserved
        [10: 8] Bitstream selection (slot on SD card, [0 to 7])
        [31:11] Reserved
    
    4-15: Reserved
    */
    `define SIMPLE_SPI_XFER_LEN 5'd8

    wire spi_tx_reg_write;
    wire [3:0] clk_div_sel;
    wire spi_xfer_done;

    wire [31:0] spi_rxData;
    
    //SPI clock divider selection
    assign clk_div_sel = slv_reg0[3:0]; //0x3 from driver

    //SPI device chip selects (active high; inverted before use below)
    assign spi_cs_n = ~slv_reg0[31]; //0x80000000 from driver
    
    //Use the IPIC write-enable for the SPI Tx register as the SPI go
    // The bus will be paused until this core ACKs the write
    assign spi_tx_reg_write = Bus2IP_WrCE[6];//WrCE/RdCE busses are addressed CE[7:0]=slv_reg[0:7]

    //spi_tx_reg_write (Bus2IP_WrCE[6]) de-asserts as soon as transaction is ACK'd
    // so this mux switches back to the generic ACK as soon as the SPI xfer is done
    //Thus, the duration of assertion for spi_xfer_done doesn't really matter
    //A bit fast-n-loose, but works ok
    assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack;

    //FPGA config control bits, driven to CPLD
    //Active low ctrl sigs here allow PULLUP in CoolRunner-II CPLD to help avoid accidental reconfigs
    //  (no CPLD PULLDOWN available in C2 parts)
    assign spi_enable_n = ~slv_reg3[0];
    assign cfg_req_n = ~slv_reg3[1];
    assign cfg_sel[2:0] = slv_reg3[10:8];
    
    warp_spi_io #(.SPI_XFER_LEN(`SIMPLE_SPI_XFER_LEN)) spi_io
    (
        .sys_clk(Bus2IP_Clk),
        .reset(~Bus2IP_Resetn), //warp_spi_io reset is active high
        .go(spi_tx_reg_write),
        .done(spi_xfer_done),
        .clkDiv(clk_div_sel),

        .currBitNum(),

        .txData(slv_reg1),

        .rxData1(spi_rxData),
        .rxData2(),
        .rxData3(),
        .rxData4(),
        
        .spi_cs(),
        .spi_sclk(spi_sclk),

        .spi_mosi(spi_mosi),
        
        .spi_miso1(spi_miso),
        .spi_miso2(1'b0),
        .spi_miso3(1'b0),
        .spi_miso4(1'b0)
    );
    
endmodule