#ifndef WARP_SIMPLE_SPI_H
#define WARP_SIMPLE_SPI_H

#include "xbasic_types.h"
#include "xstatus.h"
#include "xil_io.h"

#define WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET (0x00000000)
#define WARP_SIMPLE_SPI_SLV_REG0_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000000)
#define WARP_SIMPLE_SPI_SLV_REG1_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000004)
#define WARP_SIMPLE_SPI_SLV_REG2_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000008)
#define WARP_SIMPLE_SPI_SLV_REG3_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x0000000C)
#define WARP_SIMPLE_SPI_SLV_REG4_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000010)
#define WARP_SIMPLE_SPI_SLV_REG5_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000014)
#define WARP_SIMPLE_SPI_SLV_REG6_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000018)
#define WARP_SIMPLE_SPI_SLV_REG7_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x0000001C)
#define WARP_SIMPLE_SPI_SLV_REG8_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000020)
#define WARP_SIMPLE_SPI_SLV_REG9_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000024)
#define WARP_SIMPLE_SPI_SLV_REG10_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000028)
#define WARP_SIMPLE_SPI_SLV_REG11_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x0000002C)
#define WARP_SIMPLE_SPI_SLV_REG12_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000030)
#define WARP_SIMPLE_SPI_SLV_REG13_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000034)
#define WARP_SIMPLE_SPI_SLV_REG14_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000038)
#define WARP_SIMPLE_SPI_SLV_REG15_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x0000003C)


  	/* Address map:
		HDL is coded [MSB:LSB] = [31:0]
		regX[31]  maps to 0x80000000 in C driver
		regX[0] maps to 0x00000001 in C driver

	0: Config:
		[ 3: 0] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x0000000F
		[30:10] Reserved 
		[   31] Chip select

	1: SPI Tx
		[ 7: 0] Tx data byte
		[31: 8] Reserved
	
	2: SPI Rx: {samp_rxByte, 24'b0}
		[ 7: 0] SPI Rx byte
		[31: 8] Reserved 0xFFFFFF00
		
	3: FPGA config control:
		[    0] SPI Enable (inverted below - reg active high, output active low) - gives FPGA SPI master control of SD card
		[    1] Config request (inverted below - reg active high, output active low) - asserting this bit will reconfigure FPGA!
		[ 7: 2] Reserved
		[10: 8] Bitstream selection (slot on SD card, [0 to 7])
		[31:11] Reserved
	
	4-15: Reserved
	*/

#define SSPI_REG_CONFIG 		WARP_SIMPLE_SPI_SLV_REG0_OFFSET
#define SSPI_REG_SPITX 			WARP_SIMPLE_SPI_SLV_REG1_OFFSET
#define SSPI_REG_SPIRX 			WARP_SIMPLE_SPI_SLV_REG2_OFFSET
#define SSPI_REG_FPGA_CFG_CTRL	WARP_SIMPLE_SPI_SLV_REG3_OFFSET

#define SSPI_REG_CONFIG_MASK_CLKDIV	 0x0000000F
#define SSPI_REG_CONFIG_MASK_CS		 0x80000000

#define SSPI_REG_FPGA_CFG_MASK_EN	0x00000001
#define SSPI_REG_FPGA_CFG_MASK_GO	0x00000002
#define SSPI_REG_FPGA_CFG_MASK_SLOT	0x00000F00

#define sd_fpga_ctrl_en(ba) Xil_Out32((ba+SSPI_REG_FPGA_CFG_CTRL), (Xil_In32((ba+SSPI_REG_FPGA_CFG_CTRL)) | SSPI_REG_FPGA_CFG_MASK_EN))
#define sd_fpga_ctrl_dis(ba) Xil_Out32((ba+SSPI_REG_FPGA_CFG_CTRL), (Xil_In32((ba+SSPI_REG_FPGA_CFG_CTRL)) & ~SSPI_REG_FPGA_CFG_MASK_EN))

#define sd_config_req(ba) Xil_Out32((ba+SSPI_REG_FPGA_CFG_CTRL), (Xil_In32((ba+SSPI_REG_FPGA_CFG_CTRL)) | SSPI_REG_FPGA_CFG_MASK_GO))
#define sd_config_set_slot(ba, slot) Xil_Out32((ba+SSPI_REG_FPGA_CFG_CTRL), ((Xil_In32((ba+SSPI_REG_FPGA_CFG_CTRL)) & ~SSPI_REG_FPGA_CFG_MASK_SLOT) | (slot&0xF)<<8))

#define simple_spi_set_clkDiv(ba, div) (Xil_Out32((ba+SSPI_REG_CONFIG), \
		(Xil_In32((ba+SSPI_REG_CONFIG)) & ~SSPI_REG_CONFIG_MASK_CLKDIV) | (div & SSPI_REG_CONFIG_MASK_CLKDIV)))

#define simple_spi_set_cs(ba, cs) (Xil_Out32((ba+SSPI_REG_CONFIG), \
		(Xil_In32((ba+SSPI_REG_CONFIG)) & ~SSPI_REG_CONFIG_MASK_CS) | (cs ? SSPI_REG_CONFIG_MASK_CS:0)))
		
//Functions
u8 simple_spi_read(u32 baseaddr);
void simple_spi_write(u32 baseaddr, u8 txByte);
void sd_send_cmd(u32 ba, u8 cmd, u32 args, u8 last_byte);
int sd_read_block(u32 ba, u32 blk_offset, u8* buf, u32 blk_size);
int sd_write_block(u32 ba, u32 blk_offset, u8* buf, u32 blk_size);
int sd_rw_init(u32 ba);

#define SD_BLK_SIZE		512
#define SD_BLKS_PER_IMG 18404 //LX240 bitstrem = 9.2MB

//From http://www.mars.dti.ne.jp/~m7030/pic_room/rec/mmc.c
/* MMC/SD command (in SPI) */
#define CMD0	(0x40+0)	/* GO_IDLE_STATE */
#define CMD1	(0x40+1)	/* SEND_OP_COND (MMC) */
#define	ACMD41	(0x40+41)	/* SEND_OP_COND (SDC) */
#define CMD8	(0x40+8)	/* SEND_IF_COND */
#define CMD9	(0x40+9)	/* SEND_CSD */
#define CMD10	(0x40+10)	/* SEND_CID */
#define CMD12	(0x40+12)	/* STOP_TRANSMISSION */
#define ACMD13	(0x40+13)	/* SD_STATUS (SDC) */
#define CMD16	(0x40+16)	/* SET_BLOCKLEN */
#define CMD17	(0x40+17)	/* READ_SINGLE_BLOCK */
#define CMD18	(0x40+18)	/* READ_MULTIPLE_BLOCK */
#define CMD23	(0x40+23)	/* SET_BLOCK_COUNT (MMC) */
#define	ACMD23	(0x40+23)	/* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24	(0x40+24)	/* WRITE_BLOCK */
#define CMD25	(0x40+25)	/* WRITE_MULTIPLE_BLOCK */
#define CMD55	(0x40+55)	/* APP_CMD */
#define CMD58	(0x40+58)	/* READ_OCR */

#define DATA_TOKEN_RD			0xFE
#define DATA_TOKEN_WR_SINGLE	0xFE
#define DATA_TOKEN_WR_MULTI		0xFC
#define DATA_TOKEN_STOP_TRAN	0xFD

#endif /** WARP_SIMPLE_SPI_H */