source: PlatformSupport/CustomPeripherals/pcores/uart_mux_v1_00_a/hdl/verilog/uart_mux.v

module uart_mux
(
    input uart_sel,
    
    input uart_0_tx,
    input uart_1_tx,
    
    output uart_0_rx,
    output uart_1_rx,
    
    output uart_tx,
    input uart_rx
);

parameter MIRROR_UART_RX = 0;

parameter C_FAMILY = "virtex6";

assign uart_0_rx = ((MIRROR_UART_RX == 1) || (uart_sel == 0)) ? uart_rx : 1'b0;
assign uart_1_rx = ((MIRROR_UART_RX == 1) || (uart_sel == 1)) ? uart_rx : 1'b0;

assign uart_tx = (uart_sel == 0) ? uart_0_tx : uart_1_tx;

endmodule