[1766] | 1 | module w3_ad_bridge |
---|
| 2 | ( |
---|
| 3 | //Ref clk for IDELAYCTRL |
---|
| 4 | input clk200, |
---|
| 5 | |
---|
[1782] | 6 | //Input sampling clocks - User design must provide these clock signals |
---|
[1766] | 7 | |
---|
[1782] | 8 | // sys_samp_clk_Tx requirements: |
---|
| 9 | // -Synchronous to and valid for capturing user_RFx_TXD ports |
---|
| 10 | // -Frequency must match AD9963 input data rate configuration (DAC clock / interpolation rate) |
---|
| 11 | input sys_samp_clk_Tx, |
---|
| 12 | |
---|
| 13 | // sys_samp_clk_Tx_90 must be 90 degree phase shift of sys_samp_clk_Tx (used to generate TXCLK output) |
---|
| 14 | input sys_samp_clk_Tx_90, |
---|
| 15 | |
---|
| 16 | // sys_samp_clk_Rx requirements: |
---|
| 17 | // -Synchronous to AD9963 ADC clock |
---|
| 18 | // -Frequency must match AD9963 output data rate configuration (ADC clock / decimation rate) |
---|
| 19 | // user_RFx_RXD outputs are synchronous to sys_samp_clk_Rx |
---|
| 20 | input sys_samp_clk_Rx, |
---|
| 21 | |
---|
[1766] | 22 | //RF Path A User Ports |
---|
| 23 | output [0:11] user_RFA_RXD_I, |
---|
| 24 | output [0:11] user_RFA_RXD_Q, |
---|
| 25 | |
---|
| 26 | input [0:11] user_RFA_TXD_I, |
---|
| 27 | input [0:11] user_RFA_TXD_Q, |
---|
| 28 | |
---|
| 29 | input user_RFA_TXIQ, |
---|
| 30 | |
---|
| 31 | //RF Path B User Ports |
---|
| 32 | output [0:11] user_RFB_RXD_I, |
---|
| 33 | output [0:11] user_RFB_RXD_Q, |
---|
| 34 | |
---|
| 35 | input [0:11] user_RFB_TXD_I, |
---|
| 36 | input [0:11] user_RFB_TXD_Q, |
---|
| 37 | |
---|
| 38 | input user_RFB_TXIQ, |
---|
| 39 | |
---|
| 40 | //RF Path A AD ports |
---|
| 41 | output [0:11] ad_RFA_TXD, |
---|
| 42 | output ad_RFA_TXIQ, |
---|
| 43 | output ad_RFA_TXCLK, |
---|
| 44 | |
---|
| 45 | input [0:11] ad_RFA_TRXD, |
---|
| 46 | input ad_RFA_TRXIQ, |
---|
| 47 | input ad_RFA_TRXCLK, |
---|
| 48 | |
---|
| 49 | //RF Path B AD ports |
---|
| 50 | output [0:11] ad_RFB_TXD, |
---|
| 51 | output ad_RFB_TXIQ, |
---|
| 52 | output ad_RFB_TXCLK, |
---|
| 53 | |
---|
| 54 | input [0:11] ad_RFB_TRXD, |
---|
| 55 | input ad_RFB_TRXIQ, |
---|
| 56 | input ad_RFB_TRXCLK |
---|
| 57 | ); |
---|
| 58 | |
---|
| 59 | parameter C_FAMILY = "virtex6"; |
---|
| 60 | parameter INCLUDE_IDELAYCTRL = 1; |
---|
| 61 | |
---|
| 62 | |
---|
| 63 | assign ad_RFA_TXIQ = user_RFA_TXIQ; |
---|
| 64 | assign ad_RFB_TXIQ = user_RFB_TXIQ; |
---|
| 65 | |
---|
| 66 | generate |
---|
| 67 | if(INCLUDE_IDELAYCTRL==1) begin |
---|
| 68 | IDELAYCTRL IDELAYCTRL_inst ( |
---|
| 69 | .RDY(), // 1-bit Ready output |
---|
| 70 | .REFCLK(clk200), // 1-bit Reference clock input |
---|
| 71 | .RST(1'b0) // 1-bit Reset input |
---|
| 72 | ); |
---|
| 73 | end |
---|
| 74 | endgenerate |
---|
| 75 | |
---|
| 76 | //Use DDR primitives for cleanest output clock |
---|
| 77 | ODDR #( |
---|
| 78 | .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
---|
| 79 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
---|
| 80 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
---|
| 81 | ) OBUFDDR_RFA_TXCLK ( |
---|
| 82 | .Q(ad_RFA_TXCLK), // 1-bit DDR output |
---|
[1782] | 83 | .C(sys_samp_clk_Tx_90), // 1-bit clock input |
---|
[1766] | 84 | .CE(1'b1), // 1-bit clock enable input |
---|
| 85 | .D1(1'b1), // 1-bit data input (positive edge) |
---|
| 86 | .D2(1'b0), // 1-bit data input (negative edge) |
---|
| 87 | .R(1'b0), // 1-bit reset |
---|
| 88 | .S(1'b0) // 1-bit set |
---|
| 89 | ); |
---|
| 90 | |
---|
| 91 | ODDR #( |
---|
| 92 | .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
---|
| 93 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
---|
| 94 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
---|
| 95 | ) OBUFDDR_RFB_TXCLK ( |
---|
| 96 | .Q(ad_RFB_TXCLK), // 1-bit DDR output |
---|
[1782] | 97 | .C(sys_samp_clk_Tx_90), // 1-bit clock input |
---|
[1766] | 98 | .CE(1'b1), // 1-bit clock enable input |
---|
| 99 | .D1(1'b1), // 1-bit data input (positive edge) |
---|
| 100 | .D2(1'b0), // 1-bit data input (negative edge) |
---|
| 101 | .R(1'b0), // 1-bit reset |
---|
| 102 | .S(1'b0) // 1-bit set |
---|
| 103 | ); |
---|
| 104 | |
---|
| 105 | |
---|
| 106 | wire ad_RFA_TRXCLK_buf, ad_RFB_TRXCLK_buf; |
---|
| 107 | wire ad_RFA_TRXCLK_dly, ad_RFB_TRXCLK_dly; |
---|
| 108 | |
---|
| 109 | //Delay AD9963-generated TRXCLK, then drive BUFIO for latching TRXD DDR inputs |
---|
| 110 | IODELAYE1 #( |
---|
| 111 | .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE") |
---|
| 112 | .DELAY_SRC("I"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O") |
---|
| 113 | .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") |
---|
| 114 | .IDELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE" |
---|
| 115 | .IDELAY_VALUE(31), // Output delay tap setting (0-32) |
---|
| 116 | .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz |
---|
| 117 | .SIGNAL_PATTERN("CLOCK") // "DATA" or "CLOCK" input signal |
---|
| 118 | ) IDELAY_RFA_TRXCLK ( |
---|
| 119 | .IDATAIN(ad_RFA_TRXCLK), |
---|
| 120 | .DATAOUT(ad_RFA_TRXCLK_dly), |
---|
| 121 | .T(1'b0) // 1-bit input - 3-state input control. Tie high for input-only or internal delay or |
---|
| 122 | ); |
---|
| 123 | |
---|
| 124 | IODELAYE1 #( |
---|
| 125 | .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE") |
---|
| 126 | .DELAY_SRC("I"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O") |
---|
| 127 | .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") |
---|
| 128 | .IDELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE" |
---|
| 129 | .IDELAY_VALUE(31), // Output delay tap setting (0-32) |
---|
| 130 | .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz |
---|
| 131 | .SIGNAL_PATTERN("CLOCK") // "DATA" or "CLOCK" input signal |
---|
| 132 | ) IDELAY_RFB_TRXCLK ( |
---|
| 133 | .IDATAIN(ad_RFB_TRXCLK), |
---|
| 134 | .DATAOUT(ad_RFB_TRXCLK_dly), |
---|
| 135 | .T(1'b0) // 1-bit input - 3-state input control. Tie high for input-only or internal delay or |
---|
| 136 | ); |
---|
| 137 | |
---|
| 138 | BUFIO BUFIO_RFA_TRXCLK ( |
---|
| 139 | .O(ad_RFA_TRXCLK_buf), // Clock buffer output |
---|
| 140 | .I(ad_RFA_TRXCLK_dly) // Clock buffer input |
---|
| 141 | ); |
---|
| 142 | |
---|
| 143 | BUFIO BUFIO_RFB_TRXCLK ( |
---|
| 144 | .O(ad_RFB_TRXCLK_buf), // Clock buffer output |
---|
| 145 | .I(ad_RFB_TRXCLK_dly) // Clock buffer input |
---|
| 146 | ); |
---|
| 147 | |
---|
| 148 | wire [0:11] user_RFA_RXD_I_src; |
---|
| 149 | wire [0:11] user_RFA_RXD_Q_src; |
---|
| 150 | wire [0:11] user_RFB_RXD_I_src; |
---|
| 151 | wire [0:11] user_RFB_RXD_Q_src; |
---|
| 152 | |
---|
| 153 | //Instantiate all the DDR registers for TXD and TRXD I/O |
---|
| 154 | // Only selects bits [0:11] (12MSB) of 14-bit Tx I/Q samples provided by user logic |
---|
| 155 | genvar ii; |
---|
| 156 | generate |
---|
| 157 | for(ii=0; ii<12; ii=ii+1) begin: DDR_REGS_RFA_RFB |
---|
| 158 | ODDR #( |
---|
| 159 | .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
---|
| 160 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
---|
| 161 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
---|
| 162 | ) ODDR_RFA_TXD ( |
---|
| 163 | .Q(ad_RFA_TXD[ii]), // 1-bit DDR output |
---|
[1782] | 164 | .C(sys_samp_clk_Tx), // 1-bit clock input |
---|
[1766] | 165 | .CE(1'b1), // 1-bit clock enable input |
---|
| 166 | .D1(user_RFA_TXD_I[ii]), // 1-bit data input (positive edge) |
---|
| 167 | .D2(user_RFA_TXD_Q[ii]), // 1-bit data input (negative edge) |
---|
| 168 | .R(1'b0), // 1-bit reset |
---|
| 169 | .S(1'b0) // 1-bit set |
---|
| 170 | ); |
---|
| 171 | ODDR #( |
---|
| 172 | .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
---|
| 173 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
---|
| 174 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
---|
| 175 | ) ODDR_RFB_TXD ( |
---|
| 176 | .Q(ad_RFB_TXD[ii]), // 1-bit DDR output |
---|
[1782] | 177 | .C(sys_samp_clk_Tx), // 1-bit clock input |
---|
[1766] | 178 | .CE(1'b1), // 1-bit clock enable input |
---|
| 179 | .D1(user_RFB_TXD_I[ii]), // 1-bit data input (positive edge) |
---|
| 180 | .D2(user_RFB_TXD_Q[ii]), // 1-bit data input (negative edge) |
---|
| 181 | .R(1'b0), // 1-bit reset |
---|
| 182 | .S(1'b0) // 1-bit set |
---|
| 183 | ); |
---|
| 184 | |
---|
| 185 | |
---|
| 186 | IDDR #( |
---|
| 187 | .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" |
---|
| 188 | .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1 |
---|
| 189 | .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1 |
---|
| 190 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
---|
| 191 | ) IDDR_RFA_TRXD ( |
---|
| 192 | .Q1(user_RFA_RXD_I_src[ii]), // 1-bit output for positive edge of clock |
---|
| 193 | .Q2(user_RFA_RXD_Q_src[ii]), // 1-bit output for negative edge of clock |
---|
| 194 | .C(ad_RFA_TRXCLK_buf), // 1-bit clock input |
---|
| 195 | .CE(1'b1), // 1-bit clock enable input |
---|
| 196 | .D(ad_RFA_TRXD[ii]), // 1-bit DDR data input |
---|
| 197 | .R(1'b0), // 1-bit reset |
---|
| 198 | .S(1'b0) // 1-bit set |
---|
| 199 | ); |
---|
| 200 | IDDR #( |
---|
| 201 | .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" |
---|
| 202 | .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1 |
---|
| 203 | .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1 |
---|
| 204 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
---|
| 205 | ) IDDR_RFB_TRXD ( |
---|
| 206 | .Q1(user_RFB_RXD_I_src[ii]), // 1-bit output for positive edge of clock |
---|
| 207 | .Q2(user_RFB_RXD_Q_src[ii]), // 1-bit output for negative edge of clock |
---|
| 208 | .C(ad_RFB_TRXCLK_buf), // 1-bit clock input |
---|
| 209 | .CE(1'b1), // 1-bit clock enable input |
---|
| 210 | .D(ad_RFB_TRXD[ii]), // 1-bit DDR data input |
---|
| 211 | .R(1'b0), // 1-bit reset |
---|
| 212 | .S(1'b0) // 1-bit set |
---|
| 213 | ); |
---|
| 214 | |
---|
| 215 | //D flip flops to connect source-syncronous inputs to samp_clk domain (TRXCLK and samp_clk have same rate, arbitrary phases) |
---|
[1782] | 216 | FDSE #(.INIT(1'b0)) DFF2_RFA_I (.D(user_RFA_RXD_I_src[ii]), .Q(user_RFA_RXD_I[ii]), .C(sys_samp_clk_Rx), .S(1'b0), .CE(1'b1)); |
---|
| 217 | FDSE #(.INIT(1'b0)) DFF2_RFA_Q (.D(user_RFA_RXD_Q_src[ii]), .Q(user_RFA_RXD_Q[ii]), .C(sys_samp_clk_Rx), .S(1'b0), .CE(1'b1)); |
---|
| 218 | FDSE #(.INIT(1'b0)) DFF2_RFB_I (.D(user_RFB_RXD_I_src[ii]), .Q(user_RFB_RXD_I[ii]), .C(sys_samp_clk_Rx), .S(1'b0), .CE(1'b1)); |
---|
| 219 | FDSE #(.INIT(1'b0)) DFF2_RFB_Q (.D(user_RFB_RXD_Q_src[ii]), .Q(user_RFB_RXD_Q[ii]), .C(sys_samp_clk_Rx), .S(1'b0), .CE(1'b1)); |
---|
[1766] | 220 | end |
---|
| 221 | endgenerate |
---|
| 222 | |
---|
| 223 | endmodule |
---|