[4793] | 1 | ################################################################### |
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| 2 | # Copyright (c) 2015 Mango Communications |
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| 3 | # All Rights Reserved |
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| 4 | # This code is covered by the WARP license |
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| 5 | # See http://warpproject.org/license/ for details |
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| 6 | ################################################################### |
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| 7 | |
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| 8 | BEGIN w3_ad_bridge |
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| 9 | |
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| 10 | ## Peripheral Options |
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| 11 | OPTION IPTYPE = PERIPHERAL |
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| 12 | OPTION IMP_NETLIST = TRUE |
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| 13 | OPTION HDL = VERILOG |
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| 14 | OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT) |
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| 15 | OPTION USAGE_LEVEL = BASE_USER |
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| 16 | OPTION DESC = WARP v3 AD interface |
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| 17 | OPTION IP_GROUP = USER |
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| 18 | OPTION RUN_NGCBUILD = FALSE |
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| 19 | OPTION STYLE = HDL |
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| 20 | |
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| 21 | IO_INTERFACE IO_IF = ext_ad_ports, IO_TYPE = W3_ADBRIDGE_V1 |
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| 22 | IO_INTERFACE IO_IF = user_ports, IO_TYPE = W3_ADBRIDGE_V1 |
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| 23 | |
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| 24 | PARAMETER C_FAMILY = virtex6, DT = STRING |
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| 25 | |
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| 26 | #################################################################################### |
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| 27 | ## User Ports |
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| 28 | ## The user must connect sources/sinks to these ports in XPS in order to use |
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| 29 | ## the analog interface board. The rest of the board's connections are made automatically |
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| 30 | #################################################################################### |
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| 31 | PORT sys_samp_clk_RFA_Tx = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTxA, SIGIS = CLK |
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| 32 | PORT sys_samp_clk_RFB_Tx = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTxB, SIGIS = CLK |
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| 33 | |
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| 34 | PORT sys_samp_clk_RFA_Tx_90 = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTx90A, SIGIS = CLK |
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| 35 | PORT sys_samp_clk_RFB_Tx_90 = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTx90B, SIGIS = CLK |
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| 36 | |
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| 37 | PORT sys_samp_clk_RFA_Rx = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkRxA, SIGIS = CLK |
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| 38 | PORT sys_samp_clk_RFB_Rx = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkRxB, SIGIS = CLK |
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| 39 | |
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| 40 | PORT ad_RFA_TXCLK_out_en = "RF_AD_TXCLK_out_en", DIR = I, IO_IF = user_ports, IO_IS = sampClkTxEnA |
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| 41 | PORT ad_RFB_TXCLK_out_en = "RF_AD_TXCLK_out_en", DIR = I, IO_IF = user_ports, IO_IS = sampClkTxEnB |
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| 42 | |
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| 43 | PORT user_RFA_RXD_I = "", DIR = O, VEC = [0:11], IO_IF = user_ports, IO_IS = userARXDI |
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| 44 | PORT user_RFA_RXD_Q = "", DIR = O, VEC = [0:11], IO_IF = user_ports, IO_IS = userARXDQ |
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| 45 | |
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| 46 | PORT user_RFA_TXD_I = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = userATXDI |
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| 47 | PORT user_RFA_TXD_Q = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = userATXDQ |
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| 48 | |
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| 49 | PORT user_RFA_TXIQ = "", DIR = I, IO_IF = user_ports, IO_IS = user_ATXIQ |
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| 50 | |
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| 51 | PORT user_RFB_RXD_I = "", DIR = O, VEC = [0:11], IO_IF = user_ports, IO_IS = userBRXDI |
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| 52 | PORT user_RFB_RXD_Q = "", DIR = O, VEC = [0:11], IO_IF = user_ports, IO_IS = userBRXDQ |
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| 53 | |
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| 54 | PORT user_RFB_TXD_I = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = userBTXDI |
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| 55 | PORT user_RFB_TXD_Q = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = userBTXDQ |
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| 56 | |
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| 57 | PORT user_RFB_TXIQ = "", DIR = I, IO_IF = user_ports, IO_IS = user_BTXIQ |
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| 58 | |
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| 59 | #### |
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| 60 | # Analog Bridge <-> Analog Board ports |
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| 61 | #### |
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| 62 | PORT ad_RFA_TXD = "", DIR = O, VEC = [11:0], IO_IS = adATXD, ENDIAN = LITTLE, IO_IF = ext_ad_ports |
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| 63 | PORT ad_RFA_TXIQ = "", DIR = O, IO_IS = adATXIQ, IO_IF = ext_ad_ports |
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| 64 | PORT ad_RFA_TXCLK = "", DIR = O, IO_IS = adATXCLK, IO_IF = ext_ad_ports |
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| 65 | |
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| 66 | PORT ad_RFA_TRXD = "", DIR = I, VEC = [11:0], IO_IS = adATRXD, ENDIAN = LITTLE, IO_IF = ext_ad_ports |
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| 67 | PORT ad_RFA_TRXIQ = "", DIR = I, IO_IS = adATRXIQ, IO_IF = ext_ad_ports |
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| 68 | PORT ad_RFA_TRXCLK = "", DIR = I, IO_IS = adATRXCLK, IO_IF = ext_ad_ports |
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| 69 | |
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| 70 | PORT ad_RFB_TXD = "", DIR = O, VEC = [11:0], IO_IS = adATXD, ENDIAN = LITTLE, IO_IF = ext_ad_ports |
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| 71 | PORT ad_RFB_TXIQ = "", DIR = O, IO_IS = adATXIQ, IO_IF = ext_ad_ports |
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| 72 | PORT ad_RFB_TXCLK = "", DIR = O, IO_IS = adATXCLK, IO_IF = ext_ad_ports |
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| 73 | |
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| 74 | PORT ad_RFB_TRXD = "", DIR = I, VEC = [11:0], IO_IS = adBTRXD, ENDIAN = LITTLE, IO_IF = ext_ad_ports |
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| 75 | PORT ad_RFB_TRXIQ = "", DIR = I, IO_IS = adBTRXIQ, IO_IF = ext_ad_ports |
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| 76 | PORT ad_RFB_TRXCLK = "", DIR = I, IO_IS = adBTRXCLK, IO_IF = ext_ad_ports |
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| 77 | |
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| 78 | END |
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