source: PlatformSupport/CustomPeripherals/pcores/w3_ad_bridge_v3_03_b/hdl/verilog/w3_ad_bridge.v

module w3_ad_bridge
(
    input sys_clk,
    output samp_ce,
    
    // Enable (active-high) for AD_TXCLK output
    // AD9963 TXCLK pin defaults to output, configured as input via SPI by ad_controller at boot
    input ad_TXCLK_out_en,
    
    //RF Path A User Ports
    output reg [0:11] user_RFA_RXD_I,
    output reg [0:11] user_RFA_RXD_Q,

    input [0:11] user_RFA_TXD_I,
    input [0:11] user_RFA_TXD_Q,

    input user_RFA_TXIQ,

    //RF Path B User Ports
    output reg [0:11] user_RFB_RXD_I,
    output reg [0:11] user_RFB_RXD_Q,

    input [0:11] user_RFB_TXD_I,
    input [0:11] user_RFB_TXD_Q,

    input user_RFB_TXIQ,

    //RF Path A AD ports
    output reg [0:11] ad_RFA_TXD,
    output ad_RFA_TXIQ,
    output ad_RFA_TXCLK,

    input [0:11] ad_RFA_TRXD,
    input ad_RFA_TRXIQ,
    input ad_RFA_TRXCLK,

    //RF Path B AD ports
    output reg [0:11] ad_RFB_TXD,
    output ad_RFB_TXIQ,
    output ad_RFB_TXCLK,

    input [0:11] ad_RFB_TRXD,
    input ad_RFB_TRXIQ,
    input ad_RFB_TRXCLK
);

parameter C_FAMILY = "virtex6";

//Unsued in ref designs - pass through here
assign ad_RFA_TXIQ = user_RFA_TXIQ;
assign ad_RFB_TXIQ = user_RFB_TXIQ;

reg ad_RFA_TRXCLK_d1, ad_RFA_TRXCLK_d2;
reg ad_RFB_TRXCLK_d1, ad_RFB_TRXCLK_d2;

reg ad_RFA_TRXCLK_pos, ad_RFA_TRXCLK_neg, ad_RFA_TRXCLK_neg_d1;
reg ad_RFB_TRXCLK_pos, ad_RFB_TRXCLK_neg, ad_RFB_TRXCLK_neg_d1;

reg [0:11] user_RFA_TXD_I_d;
reg [0:11] user_RFA_TXD_Q_d;

reg [0:11] user_RFB_TXD_I_d;
reg [0:11] user_RFB_TXD_Q_d;

reg [0:11] user_RFA_RXD_I_d, user_RFA_RXD_Q_d;
reg [0:11] user_RFB_RXD_I_d, user_RFB_RXD_Q_d;

wire rx_samp_reg_en_A, rx_samp_reg_en_B;

always @(posedge sys_clk)
begin
    ad_RFA_TRXCLK_d1 <= ad_RFA_TRXCLK;
    ad_RFA_TRXCLK_d2 <= ad_RFA_TRXCLK_d1;

    ad_RFB_TRXCLK_d1 <= ad_RFB_TRXCLK;
    ad_RFB_TRXCLK_d2 <= ad_RFB_TRXCLK_d1;

    ad_RFA_TRXCLK_pos <= ad_RFA_TRXCLK_d1 & ~ad_RFA_TRXCLK_d2;

    ad_RFB_TRXCLK_pos <= ad_RFB_TRXCLK_d1 & ~ad_RFB_TRXCLK_d2;
    
    ad_RFA_TRXCLK_neg <= ~ad_RFA_TRXCLK_d1 & ad_RFA_TRXCLK_d2;
    ad_RFA_TRXCLK_neg_d1 <= ad_RFA_TRXCLK_neg;

    ad_RFB_TRXCLK_neg <= ~ad_RFB_TRXCLK_d1 & ad_RFB_TRXCLK_d2;
    ad_RFB_TRXCLK_neg_d1 <= ad_RFB_TRXCLK_neg;
end

// Tx sample capture
always @(posedge sys_clk)
begin
    if(samp_ce)
    begin
        user_RFA_TXD_I_d <= user_RFA_TXD_I;
        user_RFA_TXD_Q_d <= user_RFA_TXD_Q;
        user_RFB_TXD_I_d <= user_RFB_TXD_I;
        user_RFB_TXD_Q_d <= user_RFB_TXD_Q;
    end
    else
    begin
        user_RFA_TXD_I_d <= user_RFA_TXD_I_d;
        user_RFA_TXD_Q_d <= user_RFA_TXD_Q_d;
        user_RFB_TXD_I_d <= user_RFB_TXD_I_d;
        user_RFB_TXD_Q_d <= user_RFB_TXD_Q_d;
    end
end

// Rx sample capture
always @(posedge sys_clk)
begin
    if(rx_samp_reg_en_A)
    begin
        user_RFA_RXD_I <= user_RFA_RXD_I_d;
        user_RFA_RXD_Q <= user_RFA_RXD_Q_d;
    end
    else
    begin
        user_RFA_RXD_I <= user_RFA_RXD_I;
        user_RFA_RXD_Q <= user_RFA_RXD_Q;
    end
end
always @(posedge sys_clk)
begin
    if(rx_samp_reg_en_B)
    begin
        user_RFB_RXD_I <= user_RFB_RXD_I_d;
        user_RFB_RXD_Q <= user_RFB_RXD_Q_d;
    end
    else
    begin
        user_RFB_RXD_I <= user_RFB_RXD_I;
        user_RFB_RXD_Q <= user_RFB_RXD_Q;
    end
end

// Sample enable output to PHY
assign samp_ce = ad_RFA_TRXCLK_neg_d1;

// Per-ADC sample enables
assign rx_samp_reg_en_A = ad_RFA_TRXCLK_neg_d1;
assign rx_samp_reg_en_B = ad_RFB_TRXCLK_neg_d1;

wire ad_RFA_TXCLK_o;
wire ad_RFB_TXCLK_o;

// Use RF A TRXCLK to generate both TXCLK signals
//  This allows single samp_ce to PHY Tx to generate valid
//  sample streams for both Tx interfaces even when TRXCLK
//  phases are different across interfaces
assign ad_RFA_TXCLK_o = ~ad_RFA_TRXCLK_d1;
assign ad_RFB_TXCLK_o = ~ad_RFA_TRXCLK_d1;

OBUFT OBUFT_RFA_TXCLK (
    .I(ad_RFA_TXCLK_o),
    .T(~ad_TXCLK_out_en),
    .O(ad_RFA_TXCLK)
);
OBUFT OBUFT_RFB_TXCLK (
    .I(ad_RFB_TXCLK_o),
    .T(~ad_TXCLK_out_en),
    .O(ad_RFB_TXCLK)
);


always @(posedge sys_clk)
begin
    if(ad_RFA_TRXCLK_pos || ad_RFA_TRXCLK_neg)
    begin
        if(ad_RFA_TRXIQ)
            user_RFA_RXD_I_d <= ad_RFA_TRXD;
        else
            user_RFA_RXD_Q_d <= ad_RFA_TRXD;
    end
    else
    begin
        user_RFA_RXD_I_d <= user_RFA_RXD_I_d;
        user_RFA_RXD_Q_d <= user_RFA_RXD_Q_d;
    end
end

// Tx PHY uses samp_ce to generate samples; use same source (RFA_TRXCLK) to drive those samples
//  to both DACs. This may introduce a half-sample delay between RFA and RFB but will at least
//  ensure the sequence of IQ values written to TXD is valid for both converters.
always @(posedge sys_clk)
begin
    if(ad_RFA_TRXCLK_pos)
    begin
        ad_RFA_TXD <= user_RFA_TXD_I_d;
        ad_RFB_TXD <= user_RFB_TXD_I_d;
    end
    else if(ad_RFA_TRXCLK_neg)
    begin
        ad_RFA_TXD <= user_RFA_TXD_Q_d;
        ad_RFB_TXD <= user_RFB_TXD_Q_d;
    end
    else
    begin
        ad_RFA_TXD <= ad_RFA_TXD;
        ad_RFB_TXD <= ad_RFB_TXD;
    end
end

always @(posedge sys_clk)
begin
    if(ad_RFB_TRXCLK_pos || ad_RFB_TRXCLK_neg)
    begin
        if(ad_RFB_TRXIQ)
            user_RFB_RXD_I_d <= ad_RFB_TRXD;
        else
            user_RFB_RXD_Q_d <= ad_RFB_TRXD;
    end
    else
    begin
        user_RFB_RXD_I_d <= user_RFB_RXD_I_d;
        user_RFB_RXD_Q_d <= user_RFB_RXD_Q_d;
    end
end
/*
always @(posedge sys_clk)
begin
    if(ad_RFB_TRXCLK_pos)
    begin
        ad_RFB_TXD <= user_RFB_TXD_I_d;
    end
    else if(ad_RFB_TRXCLK_neg)
    begin
        ad_RFB_TXD <= user_RFB_TXD_Q_d;
    end
    else
    begin
        ad_RFB_TXD <= ad_RFB_TXD;
    end
end
*/
endmodule