source: PlatformSupport/CustomPeripherals/pcores/w3_ad_controller_axi_v3_02_a/data/w3_ad_controller_axi_v2_1_0.mpd

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##
## Name     : w3_ad_controller_axi
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN w3_ad_controller_axi

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:USER
OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
OPTION DESC = WARP v3 AD Controller (AXI)
OPTION LONG_DESC="Implements SPI master and other logic for configuring the AD9963 ADCs/DACs on the WARP v3 board and FMC-RF-2X245 module"

IO_INTERFACE IO_IF = RFA_AD, IO_TYPE = W3_RF_AD_V1
IO_INTERFACE IO_IF = RFB_AD, IO_TYPE = W3_RF_AD_V1
IO_INTERFACE IO_IF = RFC_AD, IO_TYPE = W3_RF_AD_V1
IO_INTERFACE IO_IF = RFD_AD, IO_TYPE = W3_RF_AD_V1

## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_USE_WSTRB = 0, DT = INTEGER
PARAMETER C_DPHASE_TIMEOUT = 0, DT = INTEGER
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_NUM_REG = 1, DT = INTEGER
PARAMETER C_NUM_MEM = 1, DT = INTEGER
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
PARAMETER INCLUDE_RFC_RFD_IO = 0, DT = INTEGER, RANGE = (0:1), DESC = "Include BUFIOs for SPI control of RFC and RFD. Only enable when using FMC-RF-2X245 module.", PERMIT=BASE_USER

## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI

PORT RFA_AD_spi_sclk = "", DIR = O, IO_IF=RFA_AD, IO_IS=RFA_AD_spi_sclk
PORT RFA_AD_spi_cs_n = "", DIR = O, IO_IF=RFA_AD, IO_IS=RFA_AD_spi_cs_n
PORT RFA_AD_reset_n = "", DIR = O, IO_IF=RFA_AD, IO_IS=RFA_AD_reset_n
PORT RFA_AD_spi_sdio = "", DIR = IO, THREE_STATE = FALSE, IO_IF=RFA_AD, IO_IS=RFA_AD_spi_sdio

PORT RFB_AD_spi_sclk = "", DIR = O, IO_IF=RFB_AD, IO_IS=RFB_AD_spi_sclk
PORT RFB_AD_spi_cs_n = "", DIR = O, IO_IF=RFB_AD, IO_IS=RFB_AD_spi_cs_n
PORT RFB_AD_reset_n = "", DIR = O, IO_IF=RFB_AD, IO_IS=RFB_AD_reset_n
PORT RFB_AD_spi_sdio = "", DIR = IO, THREE_STATE = FALSE, IO_IF=RFB_AD, IO_IS=RFB_AD_spi_sdio

PORT RFC_AD_spi_sclk = "", DIR = O, IO_IF=RFC_AD, IO_IS=RFC_AD_spi_sclk
PORT RFC_AD_spi_cs_n = "", DIR = O, IO_IF=RFC_AD, IO_IS=RFC_AD_spi_cs_n
PORT RFC_AD_reset_n = "", DIR = O, IO_IF=RFC_AD, IO_IS=RFC_AD_reset_n
PORT RFC_AD_spi_sdio = "", DIR = IO, THREE_STATE = FALSE, IO_IF=RFC_AD, IO_IS=RFC_AD_spi_sdio

PORT RFD_AD_spi_sclk = "", DIR = O, IO_IF=RFD_AD, IO_IS=RFD_AD_spi_sclk
PORT RFD_AD_spi_cs_n = "", DIR = O, IO_IF=RFD_AD, IO_IS=RFD_AD_spi_cs_n
PORT RFD_AD_reset_n = "", DIR = O, IO_IF=RFD_AD, IO_IS=RFD_AD_reset_n
PORT RFD_AD_spi_sdio = "", DIR = IO, THREE_STATE = FALSE, IO_IF=RFD_AD, IO_IS=RFD_AD_spi_sdio

PORT RF_AD_TXCLK_out_en = "RF_AD_TXCLK_out_en", DIR = O, IO_IF=RFA_AD, IO_IS=RF_AD_TXCLK_out_en

END