[1927] | 1 | //---------------------------------------------------------------------------- |
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| 2 | // user_logic.v - module |
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| 3 | //---------------------------------------------------------------------------- |
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| 4 | // |
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| 5 | // *************************************************************************** |
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| 6 | // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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| 7 | // ** ** |
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| 8 | // ** Xilinx, Inc. ** |
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| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
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| 22 | // ** ** |
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| 23 | // *************************************************************************** |
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| 24 | // |
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| 25 | //---------------------------------------------------------------------------- |
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| 26 | // Filename: user_logic.v |
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| 27 | // Version: 3.01.a |
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| 28 | // Description: User logic module. |
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| 29 | // Date: Tue Feb 26 12:57:13 2013 (by Create and Import Peripheral Wizard) |
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| 30 | // Verilog Standard: Verilog-2001 |
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| 31 | //---------------------------------------------------------------------------- |
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| 32 | // Naming Conventions: |
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| 33 | // active low signals: "*_n" |
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| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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| 35 | // reset signals: "rst", "rst_n" |
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| 36 | // generics: "C_*" |
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| 37 | // user defined types: "*_TYPE" |
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| 38 | // state machine next state: "*_ns" |
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| 39 | // state machine current state: "*_cs" |
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| 40 | // combinatorial signals: "*_com" |
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| 41 | // pipelined or register delay signals: "*_d#" |
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| 42 | // counter signals: "*cnt*" |
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| 43 | // clock enable signals: "*_ce" |
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| 44 | // internal version of output port: "*_i" |
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| 45 | // device pins: "*_pin" |
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| 46 | // ports: "- Names begin with Uppercase" |
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| 47 | // processes: "*_PROCESS" |
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| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 49 | //---------------------------------------------------------------------------- |
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| 50 | |
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| 51 | `uselib lib=unisims_ver |
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| 52 | `uselib lib=proc_common_v3_00_a |
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| 53 | |
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| 54 | module user_logic |
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| 55 | ( |
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| 56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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| 57 | RFA_AD_spi_sclk, |
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| 58 | RFA_AD_spi_cs_n, |
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| 59 | RFA_AD_spi_sdio, |
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| 60 | RFA_AD_reset_n, |
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| 61 | |
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| 62 | RFB_AD_spi_sclk, |
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| 63 | RFB_AD_spi_cs_n, |
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| 64 | RFB_AD_spi_sdio, |
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| 65 | RFB_AD_reset_n, |
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| 66 | |
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| 67 | RFC_AD_spi_sclk, |
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| 68 | RFC_AD_spi_cs_n, |
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| 69 | RFC_AD_spi_sdio, |
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| 70 | RFC_AD_reset_n, |
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| 71 | |
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| 72 | RFD_AD_spi_sclk, |
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| 73 | RFD_AD_spi_cs_n, |
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| 74 | RFD_AD_spi_sdio, |
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| 75 | RFD_AD_reset_n, |
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[2908] | 76 | |
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| 77 | RF_AD_TXCLK_out_en, |
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[1927] | 78 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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| 79 | |
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| 80 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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| 81 | // -- Bus protocol ports, do not add to or delete |
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| 82 | Bus2IP_Clk, // Bus to IP clock |
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| 83 | Bus2IP_Resetn, // Bus to IP reset |
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| 84 | Bus2IP_Data, // Bus to IP data bus |
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| 85 | Bus2IP_BE, // Bus to IP byte enables |
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| 86 | Bus2IP_RdCE, // Bus to IP read chip enable |
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| 87 | Bus2IP_WrCE, // Bus to IP write chip enable |
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| 88 | IP2Bus_Data, // IP to Bus data bus |
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| 89 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
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| 90 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
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| 91 | IP2Bus_Error // IP to Bus error response |
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| 92 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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| 93 | ); // user_logic |
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| 94 | |
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| 95 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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| 96 | // --USER parameters added here |
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| 97 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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[2908] | 98 | parameter INCLUDE_RFC_RFD_IO = 0; |
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[1927] | 99 | |
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| 100 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 101 | // -- Bus protocol parameters, do not add to or delete |
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| 102 | parameter C_NUM_REG = 16; |
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| 103 | parameter C_SLV_DWIDTH = 32; |
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| 104 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 105 | |
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| 106 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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| 107 | output RFA_AD_spi_sclk; |
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| 108 | output RFA_AD_spi_cs_n; |
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| 109 | inout RFA_AD_spi_sdio; |
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| 110 | output RFA_AD_reset_n; |
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| 111 | |
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| 112 | output RFB_AD_spi_sclk; |
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| 113 | output RFB_AD_spi_cs_n; |
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| 114 | inout RFB_AD_spi_sdio; |
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| 115 | output RFB_AD_reset_n; |
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| 116 | |
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| 117 | output RFC_AD_spi_sclk; |
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| 118 | output RFC_AD_spi_cs_n; |
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| 119 | inout RFC_AD_spi_sdio; |
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| 120 | output RFC_AD_reset_n; |
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| 121 | |
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| 122 | output RFD_AD_spi_sclk; |
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| 123 | output RFD_AD_spi_cs_n; |
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| 124 | inout RFD_AD_spi_sdio; |
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| 125 | output RFD_AD_reset_n; |
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[2908] | 126 | |
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| 127 | output RF_AD_TXCLK_out_en; |
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[1927] | 128 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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| 129 | |
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| 130 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 131 | // -- Bus protocol ports, do not add to or delete |
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| 132 | input Bus2IP_Clk; |
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| 133 | input Bus2IP_Resetn; |
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| 134 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; |
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| 135 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; |
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| 136 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE; |
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| 137 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE; |
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| 138 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; |
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| 139 | output IP2Bus_RdAck; |
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| 140 | output IP2Bus_WrAck; |
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| 141 | output IP2Bus_Error; |
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| 142 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 143 | |
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| 144 | //---------------------------------------------------------------------------- |
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| 145 | // Implementation |
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| 146 | //---------------------------------------------------------------------------- |
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| 147 | |
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| 148 | // --USER nets declarations added here, as needed for user logic |
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| 149 | |
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| 150 | // Nets for user logic slave model s/w accessible register example |
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| 151 | reg [C_SLV_DWIDTH-1 : 0] slv_reg0; |
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| 152 | reg [C_SLV_DWIDTH-1 : 0] slv_reg1; |
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| 153 | reg [C_SLV_DWIDTH-1 : 0] slv_reg2; |
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| 154 | reg [C_SLV_DWIDTH-1 : 0] slv_reg3; |
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| 155 | reg [C_SLV_DWIDTH-1 : 0] slv_reg4; |
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| 156 | reg [C_SLV_DWIDTH-1 : 0] slv_reg5; |
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| 157 | reg [C_SLV_DWIDTH-1 : 0] slv_reg6; |
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| 158 | reg [C_SLV_DWIDTH-1 : 0] slv_reg7; |
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| 159 | reg [C_SLV_DWIDTH-1 : 0] slv_reg8; |
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| 160 | reg [C_SLV_DWIDTH-1 : 0] slv_reg9; |
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| 161 | reg [C_SLV_DWIDTH-1 : 0] slv_reg10; |
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| 162 | reg [C_SLV_DWIDTH-1 : 0] slv_reg11; |
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| 163 | reg [C_SLV_DWIDTH-1 : 0] slv_reg12; |
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| 164 | reg [C_SLV_DWIDTH-1 : 0] slv_reg13; |
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| 165 | reg [C_SLV_DWIDTH-1 : 0] slv_reg14; |
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| 166 | reg [C_SLV_DWIDTH-1 : 0] slv_reg15; |
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| 167 | wire [15 : 0] slv_reg_write_sel; |
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| 168 | wire [15 : 0] slv_reg_read_sel; |
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| 169 | reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; |
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| 170 | wire slv_read_ack; |
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| 171 | wire slv_write_ack; |
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| 172 | integer byte_index, bit_index; |
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| 173 | |
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| 174 | // USER logic implementation added here |
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| 175 | |
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| 176 | // ------------------------------------------------------ |
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| 177 | // Example code to read/write user logic slave model s/w accessible registers |
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| 178 | // |
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| 179 | // Note: |
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| 180 | // The example code presented here is to show you one way of reading/writing |
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| 181 | // software accessible registers implemented in the user logic slave model. |
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| 182 | // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond |
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| 183 | // to one software accessible register by the top level template. For example, |
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| 184 | // if you have four 32 bit software accessible registers in the user logic, |
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| 185 | // you are basically operating on the following memory mapped registers: |
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| 186 | // |
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| 187 | // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register |
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| 188 | // "1000" C_BASEADDR + 0x0 |
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| 189 | // "0100" C_BASEADDR + 0x4 |
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| 190 | // "0010" C_BASEADDR + 0x8 |
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| 191 | // "0001" C_BASEADDR + 0xC |
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| 192 | // |
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| 193 | // ------------------------------------------------------ |
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| 194 | |
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| 195 | assign slv_reg_write_sel = Bus2IP_WrCE[15:0]; |
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| 196 | assign slv_reg_read_sel = Bus2IP_RdCE[15:0]; |
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| 197 | |
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| 198 | //Removed [14] from write_ack, so ack can be delayed following write to SPI Tx register |
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| 199 | // WrCE/RdCE[15:0] map to slv_reg[0:15] |
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| 200 | assign slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[15]; |
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| 201 | assign slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15]; |
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| 202 | |
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| 203 | // implement slave model register(s) |
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| 204 | always @( posedge Bus2IP_Clk ) |
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| 205 | begin |
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| 206 | |
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| 207 | if ( Bus2IP_Resetn == 1'b0 ) |
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| 208 | begin |
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| 209 | slv_reg0 <= 0; |
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| 210 | slv_reg1 <= 0; |
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| 211 | slv_reg2 <= 0; |
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| 212 | slv_reg3 <= 0; |
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| 213 | slv_reg4 <= 0; |
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| 214 | slv_reg5 <= 0; |
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| 215 | slv_reg6 <= 0; |
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| 216 | slv_reg7 <= 0; |
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| 217 | slv_reg8 <= 0; |
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| 218 | slv_reg9 <= 0; |
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| 219 | slv_reg10 <= 0; |
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| 220 | slv_reg11 <= 0; |
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| 221 | slv_reg12 <= 0; |
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| 222 | slv_reg13 <= 0; |
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| 223 | slv_reg14 <= 0; |
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| 224 | slv_reg15 <= 0; |
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| 225 | end |
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| 226 | else |
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| 227 | case ( slv_reg_write_sel ) |
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| 228 | 16'b1000000000000000 : |
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| 229 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 230 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 231 | slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 232 | 16'b0100000000000000 : |
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| 233 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 234 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 235 | slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 236 | 16'b0010000000000000 : |
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| 237 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 238 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 239 | slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 240 | 16'b0001000000000000 : |
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| 241 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 242 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 243 | slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 244 | 16'b0000100000000000 : |
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| 245 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 246 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 247 | slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 248 | 16'b0000010000000000 : |
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| 249 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 250 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 251 | slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 252 | 16'b0000001000000000 : |
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| 253 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 254 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 255 | slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 256 | 16'b0000000100000000 : |
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| 257 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 258 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 259 | slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 260 | 16'b0000000010000000 : |
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| 261 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 262 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 263 | slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 264 | 16'b0000000001000000 : |
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| 265 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 266 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 267 | slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 268 | 16'b0000000000100000 : |
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| 269 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 270 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 271 | slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 272 | 16'b0000000000010000 : |
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| 273 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 274 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 275 | slv_reg11[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 276 | 16'b0000000000001000 : |
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| 277 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 278 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 279 | slv_reg12[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 280 | 16'b0000000000000100 : |
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| 281 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 282 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 283 | slv_reg13[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 284 | 16'b0000000000000010 : |
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| 285 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 286 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 287 | slv_reg14[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 288 | 16'b0000000000000001 : |
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| 289 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 290 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 291 | slv_reg15[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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| 292 | default : begin |
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| 293 | slv_reg0 <= slv_reg0; |
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| 294 | slv_reg1 <= slv_reg1; |
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| 295 | slv_reg2 <= slv_reg2; |
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| 296 | slv_reg3 <= slv_reg3; |
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| 297 | slv_reg4 <= slv_reg4; |
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| 298 | slv_reg5 <= slv_reg5; |
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| 299 | slv_reg6 <= slv_reg6; |
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| 300 | slv_reg7 <= slv_reg7; |
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| 301 | slv_reg8 <= slv_reg8; |
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| 302 | slv_reg9 <= slv_reg9; |
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| 303 | slv_reg10 <= slv_reg10; |
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| 304 | slv_reg11 <= slv_reg11; |
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| 305 | slv_reg12 <= slv_reg12; |
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| 306 | slv_reg13 <= slv_reg13; |
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| 307 | slv_reg14 <= slv_reg14; |
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| 308 | slv_reg15 <= slv_reg15; |
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| 309 | end |
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| 310 | endcase |
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| 311 | |
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| 312 | end // SLAVE_REG_WRITE_PROC |
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| 313 | |
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| 314 | wire [7:0] RFA_AD_spi_rx_byte; |
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| 315 | wire [7:0] RFB_AD_spi_rx_byte; |
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| 316 | wire [7:0] RFC_AD_spi_rx_byte; |
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| 317 | wire [7:0] RFD_AD_spi_rx_byte; |
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| 318 | |
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| 319 | |
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| 320 | // implement slave model register read mux |
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| 321 | always @*//( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 ) |
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| 322 | begin |
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| 323 | |
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| 324 | case ( slv_reg_read_sel ) |
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| 325 | 16'b1000000000000000 : slv_ip2bus_data <= slv_reg0; |
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| 326 | 16'b0100000000000000 : slv_ip2bus_data <= slv_reg1; |
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| 327 | 16'b0010000000000000 : slv_ip2bus_data <= {RFD_AD_spi_rx_byte, RFC_AD_spi_rx_byte, RFB_AD_spi_rx_byte, RFA_AD_spi_rx_byte}; |
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| 328 | 16'b0001000000000000 : slv_ip2bus_data <= slv_reg3; |
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| 329 | 16'b0000100000000000 : slv_ip2bus_data <= slv_reg4; |
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| 330 | 16'b0000010000000000 : slv_ip2bus_data <= slv_reg5; |
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| 331 | 16'b0000001000000000 : slv_ip2bus_data <= slv_reg6; |
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| 332 | 16'b0000000100000000 : slv_ip2bus_data <= slv_reg7; |
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| 333 | 16'b0000000010000000 : slv_ip2bus_data <= slv_reg8; |
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| 334 | 16'b0000000001000000 : slv_ip2bus_data <= slv_reg9; |
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| 335 | 16'b0000000000100000 : slv_ip2bus_data <= slv_reg10; |
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| 336 | 16'b0000000000010000 : slv_ip2bus_data <= slv_reg11; |
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| 337 | 16'b0000000000001000 : slv_ip2bus_data <= slv_reg12; |
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| 338 | 16'b0000000000000100 : slv_ip2bus_data <= slv_reg13; |
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| 339 | 16'b0000000000000010 : slv_ip2bus_data <= slv_reg14; |
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| 340 | 16'b0000000000000001 : slv_ip2bus_data <= slv_reg15; |
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| 341 | default : slv_ip2bus_data <= 0; |
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| 342 | endcase |
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| 343 | |
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| 344 | end // SLAVE_REG_READ_PROC |
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| 345 | |
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| 346 | // ------------------------------------------------------------ |
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| 347 | // Example code to drive IP to Bus signals |
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| 348 | // ------------------------------------------------------------ |
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| 349 | |
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| 350 | assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; |
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| 351 | // assign IP2Bus_WrAck = slv_write_ack; //Overridden below |
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| 352 | assign IP2Bus_RdAck = slv_read_ack; |
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| 353 | assign IP2Bus_Error = 0; |
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| 354 | |
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| 355 | /* Address map: |
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| 356 | HDL is coded [MSB:LSB] = [31:0], per Xilinx's convention for AXI peripherals |
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| 357 | regX[31] maps to 0x80000000 in C driver |
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| 358 | regX[0] maps to 0x00000001 in C driver |
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| 359 | |
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| 360 | 0: Config: {clk_div_sel[2:0], 1'b0, RFA_AD_rst_n, RFB_AD_rst_n, RFC_AD_rst_n, RFD_AD_rst_n, 24'b0} |
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| 361 | [ 2: 0] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x00000007 |
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| 362 | [ 3] Reserved |
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| 363 | [ 4] RFA_AD reset (active low) 0x00000010 |
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| 364 | [ 5] RFB_AD reset (active low) 0x00000020 |
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| 365 | [ 6] RFC_AD reset (active low) 0x00000040 |
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| 366 | [ 7] RFD_AD reset (active low) 0x00000080 |
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[2908] | 367 | [ 8] RF_AD_TXCLK_out_en (1 = enable TXCLK output from ad_bridge) |
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| 368 | [31: 9] Reserved |
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[1927] | 369 | |
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| 370 | 1: SPI Tx |
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| 371 | [ 7: 0] Tx data byte 0x00FF |
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| 372 | [15: 8] 8-bit register address (0x00 to 0xFF all valid) 0xFF00 |
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| 373 | [20:16] 5'b0 (always zero) |
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| 374 | [22:21] Num bytes to Tx/Rx; must be 2'b0 for 1-byte Tx/Rx |
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| 375 | [ 23] RW# 1=Read, 0=Write |
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| 376 | [ 24] RFA_AD chip select mask |
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| 377 | [ 25] RFB_AD chip select mask |
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| 378 | [ 26] RFC_AD chip select mask |
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| 379 | [ 27] RFD_AD chip select mask |
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| 380 | [31:28] Reserved |
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| 381 | |
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| 382 | 2: SPI Rx: {RFA_AD_rxByte, RFB_AD_rxByte, RFC_AD_rxByte, RFD_AD_rxByte} |
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| 383 | [ 7: 0] SPI Rx byte for RFA_AD 0x000000FF |
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| 384 | [15: 8] SPI Rx byte for RFB_AD 0x0000FF00 |
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| 385 | [23:16] SPI Rx byte for RFC_AD 0x00FF0000 |
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| 386 | [31:24] SPI Rx byte for RFD_AD 0xFF000000 |
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| 387 | |
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| 388 | 3-15: Reserved |
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| 389 | */ |
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| 390 | |
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| 391 | `define AD9963_SPI_XFER_LEN 24 //AD9963 |
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| 392 | `define AD9963_SPI_FIRST_RXBIT 5'd16 //AD9963 (16-bit instruction, 8-bit data) |
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| 393 | |
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| 394 | wire [4:0] spi_bitNum; |
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| 395 | wire spi_mosi; |
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| 396 | wire spi_sclk; |
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| 397 | wire spi_cs; |
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| 398 | wire spi_rnw; |
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| 399 | wire RFA_AD_spi_cs, RFB_AD_spi_cs, RFC_AD_spi_cs, RFD_AD_spi_cs; |
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| 400 | wire spi_tx_reg_write; |
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| 401 | wire [2:0] clk_div_sel; |
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| 402 | wire spi_xfer_done; |
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| 403 | |
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| 404 | wire [31:0] RFA_AD_spi_rxData; |
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| 405 | wire [31:0] RFB_AD_spi_rxData; |
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| 406 | wire [31:0] RFC_AD_spi_rxData; |
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| 407 | wire [31:0] RFD_AD_spi_rxData; |
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| 408 | |
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| 409 | wire RFA_AD_spi_mosi, RFA_AD_spi_miso; |
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| 410 | wire RFB_AD_spi_mosi, RFB_AD_spi_miso; |
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| 411 | wire RFC_AD_spi_mosi, RFC_AD_spi_miso; |
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| 412 | wire RFD_AD_spi_mosi, RFD_AD_spi_miso; |
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| 413 | |
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| 414 | //Extract bits from IPIF slave registers and control signals |
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| 415 | |
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| 416 | //spi_io stores 32 bits for Tx/Rx |
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| 417 | // AD9963 only outputs 8-bit words during reads, always the last 8 bits of the transfer |
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| 418 | assign RFA_AD_spi_rx_byte = RFA_AD_spi_rxData[7:0]; |
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| 419 | assign RFB_AD_spi_rx_byte = RFB_AD_spi_rxData[7:0]; |
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| 420 | assign RFC_AD_spi_rx_byte = RFC_AD_spi_rxData[7:0]; |
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| 421 | assign RFD_AD_spi_rx_byte = RFD_AD_spi_rxData[7:0]; |
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| 422 | |
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| 423 | //SPI clock divider selection |
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| 424 | assign clk_div_sel = slv_reg0[2:0]; //0x7 from driver |
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| 425 | |
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| 426 | //SPI device resets (active low) |
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[2908] | 427 | reg RFA_AD_reset_n_d, RFB_AD_reset_n_d, RFC_AD_reset_n_d, RFD_AD_reset_n_d; |
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| 428 | always @(posedge Bus2IP_Clk) |
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| 429 | begin |
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| 430 | //Pipeline regs (fewer bus -> pin routes is good) |
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| 431 | RFA_AD_reset_n_d <= slv_reg0[4]; |
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| 432 | RFB_AD_reset_n_d <= slv_reg0[5]; |
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| 433 | RFC_AD_reset_n_d <= slv_reg0[6]; |
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| 434 | RFD_AD_reset_n_d <= slv_reg0[7]; |
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| 435 | end |
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[1927] | 436 | |
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[2908] | 437 | assign RFA_AD_reset_n = RFA_AD_reset_n_d; //0x10 from driver |
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| 438 | assign RFB_AD_reset_n = RFB_AD_reset_n_d; //0x20 from driver |
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| 439 | assign RFC_AD_reset_n = RFC_AD_reset_n_d; //0x40 from driver |
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| 440 | assign RFD_AD_reset_n = RFD_AD_reset_n_d; //0x80 from driver |
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| 441 | |
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| 442 | //Output enable for ad_bridge TXCLK port (AD9963 TXCLK port is bidirectional, defaults to output from AD9963) |
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| 443 | reg RF_AD_TXCLK_out_en_d; |
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| 444 | always @(posedge Bus2IP_Clk) |
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| 445 | begin |
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| 446 | //Pipeline reg (fewer bus -> pin routes is good) |
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| 447 | RF_AD_TXCLK_out_en_d <= slv_reg0[8]; //0x100 from driver |
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| 448 | end |
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| 449 | assign RF_AD_TXCLK_out_en = RF_AD_TXCLK_out_en_d; |
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| 450 | |
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[1927] | 451 | //SPI device chip selects (active high; inverted before use below) |
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| 452 | assign RFA_AD_spi_cs = slv_reg1[24]; //0x01000000 from driver |
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| 453 | assign RFB_AD_spi_cs = slv_reg1[25]; //0x02000000 from driver |
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| 454 | assign RFC_AD_spi_cs = slv_reg1[26]; //0x04000000 from driver |
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| 455 | assign RFD_AD_spi_cs = slv_reg1[27]; //0x08000000 from driver |
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| 456 | |
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| 457 | //Internal signal for read vs. write transaction |
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| 458 | assign spi_rnw = slv_reg1[`AD9963_SPI_XFER_LEN-1]; //0x00800000 from driver |
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| 459 | |
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| 460 | //Use the IPIC write-enable for the SPI Tx register as the SPI go |
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| 461 | // The bus will be paused until this core ACKs the write |
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| 462 | assign spi_tx_reg_write = Bus2IP_WrCE[14]; //WrCE[15:0] maps to slv_reg[0:15] |
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| 463 | |
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| 464 | //spi_tx_reg_write (Bus2IP_WrCE[14]) de-asserts as soon as transaction is ACK'd |
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| 465 | // so this mux switches back to the generic ACK as soon as the SPI xfer is done |
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| 466 | //Thus, the duration of assertion for spi_xfer_done doesn't really matter |
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| 467 | //A bit fast-n-loose, but works ok |
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| 468 | assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack; |
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| 469 | |
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| 470 | //SPI device chip selects are active low |
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| 471 | assign RFA_AD_spi_cs_n = ~(RFA_AD_spi_cs & spi_cs); |
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| 472 | assign RFB_AD_spi_cs_n = ~(RFB_AD_spi_cs & spi_cs); |
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| 473 | assign RFC_AD_spi_cs_n = ~(RFC_AD_spi_cs & spi_cs); |
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| 474 | assign RFD_AD_spi_cs_n = ~(RFD_AD_spi_cs & spi_cs); |
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| 475 | |
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| 476 | //Mask each device's SPI clock output by its CS; no point toggling signals that will be ignored |
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| 477 | assign RFA_AD_spi_sclk = (spi_sclk & RFA_AD_spi_cs); |
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| 478 | assign RFB_AD_spi_sclk = (spi_sclk & RFB_AD_spi_cs); |
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| 479 | assign RFC_AD_spi_sclk = (spi_sclk & RFC_AD_spi_cs); |
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| 480 | assign RFD_AD_spi_sclk = (spi_sclk & RFD_AD_spi_cs); |
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| 481 | |
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| 482 | //All SPI devices driven by same serial data output; CS signals control who listens |
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| 483 | assign RFA_AD_spi_mosi = RFA_AD_spi_cs ? spi_mosi : 1'b0; |
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| 484 | assign RFB_AD_spi_mosi = RFB_AD_spi_cs ? spi_mosi : 1'b0; |
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| 485 | assign RFC_AD_spi_mosi = RFC_AD_spi_cs ? spi_mosi : 1'b0; |
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| 486 | assign RFD_AD_spi_mosi = RFD_AD_spi_cs ? spi_mosi : 1'b0; |
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| 487 | |
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| 488 | //AD9963 SPI data is bi-directional; IOBUFs instantiated here to switch I vs. O mid-transfer |
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| 489 | //Set spi_sdio pins as inputs except when actively driving, to avoid accidental drive fights |
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| 490 | // FPGA drives the sdio pin when: |
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| 491 | // An SPI transaction is in progress AND |
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| 492 | // The transaction is a read AND the current bit is part of the instruction bytes |
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| 493 | // OR |
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| 494 | // The transaction is a write |
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| 495 | assign RFA_AD_spi_sdio_output_en = spi_cs & ( (spi_rnw & (spi_bitNum < `AD9963_SPI_FIRST_RXBIT)) | (~spi_rnw)); |
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| 496 | assign RFB_AD_spi_sdio_output_en = spi_cs & ( (spi_rnw & (spi_bitNum < `AD9963_SPI_FIRST_RXBIT)) | (~spi_rnw)); |
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| 497 | assign RFC_AD_spi_sdio_output_en = spi_cs & ( (spi_rnw & (spi_bitNum < `AD9963_SPI_FIRST_RXBIT)) | (~spi_rnw)); |
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| 498 | assign RFD_AD_spi_sdio_output_en = spi_cs & ( (spi_rnw & (spi_bitNum < `AD9963_SPI_FIRST_RXBIT)) | (~spi_rnw)); |
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| 499 | |
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| 500 | IOBUF IOBUF_RFA_AD_sdio ( |
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| 501 | .IO(RFA_AD_spi_sdio), //Connected to actual FPGA pin |
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| 502 | .I(RFA_AD_spi_mosi), //Logic-> Pad, input to OBUFT |
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| 503 | .O(RFA_AD_spi_miso), //Pad-> Logic, output of IBUF |
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| 504 | .T(~RFA_AD_spi_sdio_output_en) |
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| 505 | ); |
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| 506 | |
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| 507 | IOBUF IOBUF_RFB_AD_sdio ( |
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| 508 | .IO(RFB_AD_spi_sdio), //Connected to actual FPGA pin |
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| 509 | .I(RFB_AD_spi_mosi), //Logic-> Pad, input to OBUFT |
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| 510 | .O(RFB_AD_spi_miso), //Pad-> Logic, output of IBUF |
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| 511 | .T(~RFB_AD_spi_sdio_output_en) |
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| 512 | ); |
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| 513 | |
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[2908] | 514 | generate |
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| 515 | if(INCLUDE_RFC_RFD_IO==1) |
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| 516 | begin |
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| 517 | IOBUF IOBUF_RFC_AD_sdio ( |
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| 518 | .IO(RFC_AD_spi_sdio), //Connected to actual FPGA pin |
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| 519 | .I(RFC_AD_spi_mosi), //Logic-> Pad, input to OBUFT |
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| 520 | .O(RFC_AD_spi_miso), //Pad-> Logic, output of IBUF |
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| 521 | .T(~RFC_AD_spi_sdio_output_en) |
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| 522 | ); |
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[1927] | 523 | |
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[2908] | 524 | IOBUF IOBUF_RFD_AD_sdio ( |
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| 525 | .IO(RFD_AD_spi_sdio), //Connected to actual FPGA pin |
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| 526 | .I(RFD_AD_spi_mosi), //Logic-> Pad, input to OBUFT |
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| 527 | .O(RFD_AD_spi_miso), //Pad-> Logic, output of IBUF |
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| 528 | .T(~RFD_AD_spi_sdio_output_en) |
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| 529 | ); |
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| 530 | end |
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| 531 | else |
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| 532 | begin |
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| 533 | assign RFC_AD_spi_miso = 1'b0; |
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| 534 | assign RFD_AD_spi_miso = 1'b0; |
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| 535 | |
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| 536 | assign RFC_AD_spi_sdio = 1'b0; |
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| 537 | assign RFD_AD_spi_sdio = 1'b0; |
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| 538 | end |
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| 539 | endgenerate |
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[1927] | 540 | |
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| 541 | warp_spi_io #(.SPI_XFER_LEN(`AD9963_SPI_XFER_LEN)) spi_io |
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| 542 | ( |
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| 543 | .sys_clk(Bus2IP_Clk), |
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| 544 | .reset(~Bus2IP_Resetn),//warp_spi_io.reset is active high |
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| 545 | .go(spi_tx_reg_write), |
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| 546 | .done(spi_xfer_done), |
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| 547 | .clkDiv(clk_div_sel), |
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| 548 | |
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| 549 | .currBitNum(spi_bitNum), |
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| 550 | |
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| 551 | .txData(slv_reg1), |
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| 552 | |
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| 553 | .rxData1(RFA_AD_spi_rxData), |
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| 554 | .rxData2(RFB_AD_spi_rxData), |
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| 555 | .rxData3(RFC_AD_spi_rxData), |
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| 556 | .rxData4(RFD_AD_spi_rxData), |
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| 557 | |
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| 558 | .spi_cs(spi_cs), |
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| 559 | .spi_sclk(spi_sclk), |
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| 560 | |
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| 561 | .spi_mosi(spi_mosi), |
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| 562 | |
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| 563 | .spi_miso1(RFA_AD_spi_miso), |
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| 564 | .spi_miso2(RFB_AD_spi_miso), |
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| 565 | .spi_miso3(RFC_AD_spi_miso), |
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| 566 | .spi_miso4(RFD_AD_spi_miso) |
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| 567 | ); |
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| 568 | |
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| 569 | endmodule |
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