------------------------------------------------------------------------------ -- w3_ad_controller_axi.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- IMPORTANT: -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. -- -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. -- -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION -- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: w3_ad_controller_axi.vhd -- Version: 3.01.a -- Description: Top level design, instantiates library components and user logic. -- Date: Tue Feb 26 12:57:13 2013 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "I_<#|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library axi_lite_ipif_v1_01_a; use axi_lite_ipif_v1_01_a.axi_lite_ipif; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width -- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width -- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size -- C_USE_WSTRB -- AXI4LITE slave: Write Strobe -- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout -- C_BASEADDR -- AXI4LITE slave: base address -- C_HIGHADDR -- AXI4LITE slave: high address -- C_FAMILY -- FPGA Family -- C_NUM_REG -- Number of software accessible registers -- C_NUM_MEM -- Number of address-ranges -- C_SLV_AWIDTH -- Slave interface address bus width -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- S_AXI_ACLK -- AXI4LITE slave: Clock -- S_AXI_ARESETN -- AXI4LITE slave: Reset -- S_AXI_AWADDR -- AXI4LITE slave: Write address -- S_AXI_AWVALID -- AXI4LITE slave: Write address valid -- S_AXI_WDATA -- AXI4LITE slave: Write data -- S_AXI_WSTRB -- AXI4LITE slave: Write strobe -- S_AXI_WVALID -- AXI4LITE slave: Write data valid -- S_AXI_BREADY -- AXI4LITE slave: Response ready -- S_AXI_ARADDR -- AXI4LITE slave: Read address -- S_AXI_ARVALID -- AXI4LITE slave: Read address valid -- S_AXI_RREADY -- AXI4LITE slave: Read data ready -- S_AXI_ARREADY -- AXI4LITE slave: read addres ready -- S_AXI_RDATA -- AXI4LITE slave: Read data -- S_AXI_RRESP -- AXI4LITE slave: Read data response -- S_AXI_RVALID -- AXI4LITE slave: Read data valid -- S_AXI_WREADY -- AXI4LITE slave: Write data ready -- S_AXI_BRESP -- AXI4LITE slave: Response -- S_AXI_BVALID -- AXI4LITE slave: Resonse valid -- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready ------------------------------------------------------------------------------ entity w3_ad_controller_axi is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- INCLUDE_RFC_RFD_IO : integer := 0; -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer := 8; C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_FAMILY : string := "virtex6"; C_NUM_REG : integer := 1; C_NUM_MEM : integer := 1; C_SLV_AWIDTH : integer := 32; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ RFA_AD_spi_sclk : out std_logic; RFA_AD_spi_cs_n : out std_logic; RFA_AD_spi_sdio : inout std_logic; RFA_AD_reset_n : out std_logic; RFB_AD_spi_sclk : out std_logic; RFB_AD_spi_cs_n : out std_logic; RFB_AD_spi_sdio : inout std_logic; RFB_AD_reset_n : out std_logic; RFC_AD_spi_sclk : out std_logic; RFC_AD_spi_cs_n : out std_logic; RFC_AD_spi_sdio : inout std_logic; RFC_AD_reset_n : out std_logic; RFD_AD_spi_sclk : out std_logic; RFD_AD_spi_cs_n : out std_logic; RFD_AD_spi_sdio : inout std_logic; RFD_AD_reset_n : out std_logic; RF_AD_TXCLK_out_en : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; attribute SIGIS of S_AXI_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; end entity w3_ad_controller_axi; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of w3_ad_controller_axi is constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address ); constant USER_SLV_NUM_REG : integer := 16; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant TOTAL_IPIF_CE : integer := USER_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space ); ------------------------------------------ -- Index for CS/CE ------------------------------------------ constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; ------------------------------------------ -- IP Interconnect (IPIC) signal declarations ------------------------------------------ signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Resetn : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0); signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; ------------------------------------------ -- Component declaration for verilog user logic ------------------------------------------ component user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- INCLUDE_RFC_RFD_IO : integer := 0; -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 16; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ RFA_AD_spi_sclk : out std_logic; RFA_AD_spi_cs_n : out std_logic; RFA_AD_spi_sdio : inout std_logic; RFA_AD_reset_n : out std_logic; RFB_AD_spi_sclk : out std_logic; RFB_AD_spi_cs_n : out std_logic; RFB_AD_spi_sdio : inout std_logic; RFB_AD_reset_n : out std_logic; RFC_AD_spi_sclk : out std_logic; RFC_AD_spi_cs_n : out std_logic; RFC_AD_spi_sdio : inout std_logic; RFC_AD_reset_n : out std_logic; RFD_AD_spi_sclk : out std_logic; RFD_AD_spi_cs_n : out std_logic; RFD_AD_spi_sdio : inout std_logic; RFD_AD_reset_n : out std_logic; RF_AD_TXCLK_out_en : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end component user_logic; begin ------------------------------------------ -- instantiate axi_lite_ipif ------------------------------------------ AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif generic map ( C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_RREADY => S_AXI_RREADY, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_AWREADY => S_AXI_AWREADY, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE, Bus2IP_Data => ipif_Bus2IP_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, IP2Bus_Data => ipif_IP2Bus_Data ); ------------------------------------------ -- instantiate User Logic ------------------------------------------ USER_LOGIC_I : component user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- INCLUDE_RFC_RFD_IO => INCLUDE_RFC_RFD_IO, -- MAP USER GENERICS ABOVE THIS LINE --------------- C_NUM_REG => USER_NUM_REG, C_SLV_DWIDTH => USER_SLV_DWIDTH ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ RFA_AD_spi_sclk => RFA_AD_spi_sclk, RFA_AD_spi_cs_n => RFA_AD_spi_cs_n, RFA_AD_spi_sdio => RFA_AD_spi_sdio, RFA_AD_reset_n => RFA_AD_reset_n, RFB_AD_spi_sclk => RFB_AD_spi_sclk, RFB_AD_spi_cs_n => RFB_AD_spi_cs_n, RFB_AD_spi_sdio => RFB_AD_spi_sdio, RFB_AD_reset_n => RFB_AD_reset_n, RFC_AD_spi_sclk => RFC_AD_spi_sclk, RFC_AD_spi_cs_n => RFC_AD_spi_cs_n, RFC_AD_spi_sdio => RFC_AD_spi_sdio, RFC_AD_reset_n => RFC_AD_reset_n, RFD_AD_spi_sclk => RFD_AD_spi_sclk, RFD_AD_spi_cs_n => RFD_AD_spi_cs_n, RFD_AD_spi_sdio => RFD_AD_spi_sdio, RFD_AD_reset_n => RFD_AD_reset_n, RF_AD_TXCLK_out_en => RF_AD_TXCLK_out_en, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error ); ------------------------------------------ -- connect internal signals ------------------------------------------ ipif_IP2Bus_Data <= user_IP2Bus_Data; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0); end IMP;