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w3_ad_controller.vhd

Last change on this file was 1766, checked in by murphpo, 12 years ago

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1	------------------------------------------------------------------------------
2	-- w3_ad_controller.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: w3_ad_controller.vhd
36	-- Version: 3.00.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Mon May 07 20:42:33 2012 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68
69	library plbv46_slave_single_v1_01_a;
70	use plbv46_slave_single_v1_01_a.plbv46_slave_single;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_BASEADDR -- PLBv46 slave: base address
77	-- C_HIGHADDR -- PLBv46 slave: high address
78	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
79	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
80	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
81	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
82	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
83	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
84	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
85	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
86	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
87	-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
88	-- C_FAMILY -- Xilinx FPGA family
89	--
90	-- Definition of Ports:
91	-- SPLB_Clk -- PLB main bus clock
92	-- SPLB_Rst -- PLB main bus reset
93	-- PLB_ABus -- PLB address bus
94	-- PLB_UABus -- PLB upper address bus
95	-- PLB_PAValid -- PLB primary address valid indicator
96	-- PLB_SAValid -- PLB secondary address valid indicator
97	-- PLB_rdPrim -- PLB secondary to primary read request indicator
98	-- PLB_wrPrim -- PLB secondary to primary write request indicator
99	-- PLB_masterID -- PLB current master identifier
100	-- PLB_abort -- PLB abort request indicator
101	-- PLB_busLock -- PLB bus lock
102	-- PLB_RNW -- PLB read/not write
103	-- PLB_BE -- PLB byte enables
104	-- PLB_MSize -- PLB master data bus size
105	-- PLB_size -- PLB transfer size
106	-- PLB_type -- PLB transfer type
107	-- PLB_lockErr -- PLB lock error indicator
108	-- PLB_wrDBus -- PLB write data bus
109	-- PLB_wrBurst -- PLB burst write transfer indicator
110	-- PLB_rdBurst -- PLB burst read transfer indicator
111	-- PLB_wrPendReq -- PLB write pending bus request indicator
112	-- PLB_rdPendReq -- PLB read pending bus request indicator
113	-- PLB_wrPendPri -- PLB write pending request priority
114	-- PLB_rdPendPri -- PLB read pending request priority
115	-- PLB_reqPri -- PLB current request priority
116	-- PLB_TAttribute -- PLB transfer attribute
117	-- Sl_addrAck -- Slave address acknowledge
118	-- Sl_SSize -- Slave data bus size
119	-- Sl_wait -- Slave wait indicator
120	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
121	-- Sl_wrDAck -- Slave write data acknowledge
122	-- Sl_wrComp -- Slave write transfer complete indicator
123	-- Sl_wrBTerm -- Slave terminate write burst transfer
124	-- Sl_rdDBus -- Slave read data bus
125	-- Sl_rdWdAddr -- Slave read word address
126	-- Sl_rdDAck -- Slave read data acknowledge
127	-- Sl_rdComp -- Slave read transfer complete indicator
128	-- Sl_rdBTerm -- Slave terminate read burst transfer
129	-- Sl_MBusy -- Slave busy indicator
130	-- Sl_MWrErr -- Slave write error indicator
131	-- Sl_MRdErr -- Slave read error indicator
132	-- Sl_MIRQ -- Slave interrupt indicator
133	------------------------------------------------------------------------------
134
135	entity w3_ad_controller is
136	generic
137	(
138	-- ADD USER GENERICS BELOW THIS LINE ---------------
139	--USER generics added here
140	-- ADD USER GENERICS ABOVE THIS LINE ---------------
141
142	-- DO NOT EDIT BELOW THIS LINE ---------------------
143	-- Bus protocol parameters, do not add to or delete
144	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
145	C_HIGHADDR : std_logic_vector := X"00000000";
146	C_SPLB_AWIDTH : integer := 32;
147	C_SPLB_DWIDTH : integer := 128;
148	C_SPLB_NUM_MASTERS : integer := 8;
149	C_SPLB_MID_WIDTH : integer := 3;
150	C_SPLB_NATIVE_DWIDTH : integer := 32;
151	C_SPLB_P2P : integer := 0;
152	C_SPLB_SUPPORT_BURSTS : integer := 0;
153	C_SPLB_SMALLEST_MASTER : integer := 32;
154	C_SPLB_CLK_PERIOD_PS : integer := 10000;
155	C_INCLUDE_DPHASE_TIMER : integer := 0;
156	C_FAMILY : string := "virtex6"
157	-- DO NOT EDIT ABOVE THIS LINE ---------------------
158	);
159	port
160	(
161	-- ADD USER PORTS BELOW THIS LINE ------------------
162	RFA_AD_spi_sclk : out std_logic;
163	RFA_AD_spi_cs_n : out std_logic;
164	RFA_AD_spi_sdio : inout std_logic;
165	RFA_AD_reset_n : out std_logic;
166
167	RFB_AD_spi_sclk : out std_logic;
168	RFB_AD_spi_cs_n : out std_logic;
169	RFB_AD_spi_sdio : inout std_logic;
170	RFB_AD_reset_n : out std_logic;
171
172	--USER ports added here
173	-- ADD USER PORTS ABOVE THIS LINE ------------------
174
175	-- DO NOT EDIT BELOW THIS LINE ---------------------
176	-- Bus protocol ports, do not add to or delete
177	SPLB_Clk : in std_logic;
178	SPLB_Rst : in std_logic;
179	PLB_ABus : in std_logic_vector(0 to 31);
180	PLB_UABus : in std_logic_vector(0 to 31);
181	PLB_PAValid : in std_logic;
182	PLB_SAValid : in std_logic;
183	PLB_rdPrim : in std_logic;
184	PLB_wrPrim : in std_logic;
185	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
186	PLB_abort : in std_logic;
187	PLB_busLock : in std_logic;
188	PLB_RNW : in std_logic;
189	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
190	PLB_MSize : in std_logic_vector(0 to 1);
191	PLB_size : in std_logic_vector(0 to 3);
192	PLB_type : in std_logic_vector(0 to 2);
193	PLB_lockErr : in std_logic;
194	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
195	PLB_wrBurst : in std_logic;
196	PLB_rdBurst : in std_logic;
197	PLB_wrPendReq : in std_logic;
198	PLB_rdPendReq : in std_logic;
199	PLB_wrPendPri : in std_logic_vector(0 to 1);
200	PLB_rdPendPri : in std_logic_vector(0 to 1);
201	PLB_reqPri : in std_logic_vector(0 to 1);
202	PLB_TAttribute : in std_logic_vector(0 to 15);
203	Sl_addrAck : out std_logic;
204	Sl_SSize : out std_logic_vector(0 to 1);
205	Sl_wait : out std_logic;
206	Sl_rearbitrate : out std_logic;
207	Sl_wrDAck : out std_logic;
208	Sl_wrComp : out std_logic;
209	Sl_wrBTerm : out std_logic;
210	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
211	Sl_rdWdAddr : out std_logic_vector(0 to 3);
212	Sl_rdDAck : out std_logic;
213	Sl_rdComp : out std_logic;
214	Sl_rdBTerm : out std_logic;
215	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
216	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
217	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
218	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
219	-- DO NOT EDIT ABOVE THIS LINE ---------------------
220	);
221
222	attribute MAX_FANOUT : string;
223	attribute SIGIS : string;
224
225	attribute SIGIS of SPLB_Clk : signal is "CLK";
226	attribute SIGIS of SPLB_Rst : signal is "RST";
227
228	end entity w3_ad_controller;
229
230	------------------------------------------------------------------------------
231	-- Architecture section
232	------------------------------------------------------------------------------
233
234	architecture IMP of w3_ad_controller is
235
236	------------------------------------------
237	-- Array of base/high address pairs for each address range
238	------------------------------------------
239	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
240	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
241	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
242
243	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
244	(
245	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
246	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
247	);
248
249	------------------------------------------
250	-- Array of desired number of chip enables for each address range
251	------------------------------------------
252	constant USER_SLV_NUM_REG : integer := 16;
253	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
254
255	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
256	(
257	0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
258	);
259
260	------------------------------------------
261	-- Ratio of bus clock to core clock (for use in dual clock systems)
262	-- 1 = ratio is 1:1
263	-- 2 = ratio is 2:1
264	------------------------------------------
265	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
266
267	------------------------------------------
268	-- Width of the slave data bus (32 only)
269	------------------------------------------
270	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
271
272	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
273
274	------------------------------------------
275	-- Index for CS/CE
276	------------------------------------------
277	constant USER_SLV_CS_INDEX : integer := 0;
278	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
279
280	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
281
282	------------------------------------------
283	-- IP Interconnect (IPIC) signal declarations
284	------------------------------------------
285	signal ipif_Bus2IP_Clk : std_logic;
286	signal ipif_Bus2IP_Reset : std_logic;
287	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
288	signal ipif_IP2Bus_WrAck : std_logic;
289	signal ipif_IP2Bus_RdAck : std_logic;
290	signal ipif_IP2Bus_Error : std_logic;
291	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
292	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
293	signal ipif_Bus2IP_RNW : std_logic;
294	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
295	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
296	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
297	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
298	signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
299	signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
300	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
301	signal user_IP2Bus_RdAck : std_logic;
302	signal user_IP2Bus_WrAck : std_logic;
303	signal user_IP2Bus_Error : std_logic;
304
305	------------------------------------------
306	-- Component declaration for verilog user logic
307	------------------------------------------
308	component user_logic is
309	generic
310	(
311	-- ADD USER GENERICS BELOW THIS LINE ---------------
312	--USER generics added here
313	-- ADD USER GENERICS ABOVE THIS LINE ---------------
314
315	-- DO NOT EDIT BELOW THIS LINE ---------------------
316	-- Bus protocol parameters, do not add to or delete
317	C_SLV_DWIDTH : integer := 32;
318	C_NUM_REG : integer := 16
319	-- DO NOT EDIT ABOVE THIS LINE ---------------------
320	);
321	port
322	(
323	-- ADD USER PORTS BELOW THIS LINE ------------------
324	RFA_AD_spi_sclk : out std_logic;
325	RFA_AD_spi_cs_n : out std_logic;
326	RFA_AD_spi_sdio : inout std_logic;
327	RFA_AD_reset_n : out std_logic;
328
329	RFB_AD_spi_sclk : out std_logic;
330	RFB_AD_spi_cs_n : out std_logic;
331	RFB_AD_spi_sdio : inout std_logic;
332	RFB_AD_reset_n : out std_logic;
333
334	-- ADD USER PORTS ABOVE THIS LINE ------------------
335
336	-- DO NOT EDIT BELOW THIS LINE ---------------------
337	-- Bus protocol ports, do not add to or delete
338	Bus2IP_Clk : in std_logic;
339	Bus2IP_Reset : in std_logic;
340	Bus2IP_Addr : in std_logic_vector(0 to 31);
341	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
342	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
343	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
344	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
345	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
346	IP2Bus_RdAck : out std_logic;
347	IP2Bus_WrAck : out std_logic;
348	IP2Bus_Error : out std_logic
349	-- DO NOT EDIT ABOVE THIS LINE ---------------------
350	);
351	end component user_logic;
352
353	begin
354
355	------------------------------------------
356	-- instantiate plbv46_slave_single
357	------------------------------------------
358	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
359	generic map
360	(
361	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
362	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
363	C_SPLB_P2P => C_SPLB_P2P,
364	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
365	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
366	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
367	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
368	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
369	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
370	C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
371	C_FAMILY => C_FAMILY
372	)
373	port map
374	(
375	SPLB_Clk => SPLB_Clk,
376	SPLB_Rst => SPLB_Rst,
377	PLB_ABus => PLB_ABus,
378	PLB_UABus => PLB_UABus,
379	PLB_PAValid => PLB_PAValid,
380	PLB_SAValid => PLB_SAValid,
381	PLB_rdPrim => PLB_rdPrim,
382	PLB_wrPrim => PLB_wrPrim,
383	PLB_masterID => PLB_masterID,
384	PLB_abort => PLB_abort,
385	PLB_busLock => PLB_busLock,
386	PLB_RNW => PLB_RNW,
387	PLB_BE => PLB_BE,
388	PLB_MSize => PLB_MSize,
389	PLB_size => PLB_size,
390	PLB_type => PLB_type,
391	PLB_lockErr => PLB_lockErr,
392	PLB_wrDBus => PLB_wrDBus,
393	PLB_wrBurst => PLB_wrBurst,
394	PLB_rdBurst => PLB_rdBurst,
395	PLB_wrPendReq => PLB_wrPendReq,
396	PLB_rdPendReq => PLB_rdPendReq,
397	PLB_wrPendPri => PLB_wrPendPri,
398	PLB_rdPendPri => PLB_rdPendPri,
399	PLB_reqPri => PLB_reqPri,
400	PLB_TAttribute => PLB_TAttribute,
401	Sl_addrAck => Sl_addrAck,
402	Sl_SSize => Sl_SSize,
403	Sl_wait => Sl_wait,
404	Sl_rearbitrate => Sl_rearbitrate,
405	Sl_wrDAck => Sl_wrDAck,
406	Sl_wrComp => Sl_wrComp,
407	Sl_wrBTerm => Sl_wrBTerm,
408	Sl_rdDBus => Sl_rdDBus,
409	Sl_rdWdAddr => Sl_rdWdAddr,
410	Sl_rdDAck => Sl_rdDAck,
411	Sl_rdComp => Sl_rdComp,
412	Sl_rdBTerm => Sl_rdBTerm,
413	Sl_MBusy => Sl_MBusy,
414	Sl_MWrErr => Sl_MWrErr,
415	Sl_MRdErr => Sl_MRdErr,
416	Sl_MIRQ => Sl_MIRQ,
417	Bus2IP_Clk => ipif_Bus2IP_Clk,
418	Bus2IP_Reset => ipif_Bus2IP_Reset,
419	IP2Bus_Data => ipif_IP2Bus_Data,
420	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
421	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
422	IP2Bus_Error => ipif_IP2Bus_Error,
423	Bus2IP_Addr => ipif_Bus2IP_Addr,
424	Bus2IP_Data => ipif_Bus2IP_Data,
425	Bus2IP_RNW => ipif_Bus2IP_RNW,
426	Bus2IP_BE => ipif_Bus2IP_BE,
427	Bus2IP_CS => ipif_Bus2IP_CS,
428	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
429	Bus2IP_WrCE => ipif_Bus2IP_WrCE
430	);
431
432	------------------------------------------
433	-- instantiate User Logic
434	------------------------------------------
435	USER_LOGIC_I : component user_logic
436	generic map
437	(
438	-- MAP USER GENERICS BELOW THIS LINE ---------------
439	--USER generics mapped here
440	-- MAP USER GENERICS ABOVE THIS LINE ---------------
441
442	C_SLV_DWIDTH => USER_SLV_DWIDTH,
443	C_NUM_REG => USER_NUM_REG
444	)
445	port map
446	(
447	-- MAP USER PORTS BELOW THIS LINE ------------------
448	RFA_AD_spi_sclk => RFA_AD_spi_sclk,
449	RFA_AD_spi_cs_n => RFA_AD_spi_cs_n,
450	RFA_AD_spi_sdio => RFA_AD_spi_sdio,
451	RFA_AD_reset_n => RFA_AD_reset_n,
452
453	RFB_AD_spi_sclk => RFB_AD_spi_sclk,
454	RFB_AD_spi_cs_n => RFB_AD_spi_cs_n,
455	RFB_AD_spi_sdio => RFB_AD_spi_sdio,
456	RFB_AD_reset_n => RFB_AD_reset_n,
457
458
459	-- MAP USER PORTS ABOVE THIS LINE ------------------
460
461	Bus2IP_Clk => ipif_Bus2IP_Clk,
462	Bus2IP_Reset => ipif_Bus2IP_Reset,
463	Bus2IP_Addr => ipif_Bus2IP_Addr,
464	Bus2IP_Data => ipif_Bus2IP_Data,
465	Bus2IP_BE => ipif_Bus2IP_BE,
466	Bus2IP_RdCE => user_Bus2IP_RdCE,
467	Bus2IP_WrCE => user_Bus2IP_WrCE,
468	IP2Bus_Data => user_IP2Bus_Data,
469	IP2Bus_RdAck => user_IP2Bus_RdAck,
470	IP2Bus_WrAck => user_IP2Bus_WrAck,
471	IP2Bus_Error => user_IP2Bus_Error
472	);
473
474	------------------------------------------
475	-- connect internal signals
476	------------------------------------------
477	ipif_IP2Bus_Data <= user_IP2Bus_Data;
478	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
479	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
480	ipif_IP2Bus_Error <= user_IP2Bus_Error;
481
482	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
483	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
484
485	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/w3_ad_controller_v3_00_b/hdl/vhdl/w3_ad_controller.vhd

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