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w3_ad_controller.vhd

Last change on this file was 1864, checked in by murphpo, 11 years ago
Adding/updating cores for FMC radio module
File size: 25.0 KB

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1	------------------------------------------------------------------------------
2	-- w3_ad_controller.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: w3_ad_controller.vhd
36	-- Version: 3.00.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Mon May 07 20:42:33 2012 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68
69	library plbv46_slave_single_v1_01_a;
70	use plbv46_slave_single_v1_01_a.plbv46_slave_single;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_BASEADDR -- PLBv46 slave: base address
77	-- C_HIGHADDR -- PLBv46 slave: high address
78	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
79	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
80	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
81	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
82	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
83	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
84	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
85	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
86	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
87	-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
88	-- C_FAMILY -- Xilinx FPGA family
89	--
90	-- Definition of Ports:
91	-- SPLB_Clk -- PLB main bus clock
92	-- SPLB_Rst -- PLB main bus reset
93	-- PLB_ABus -- PLB address bus
94	-- PLB_UABus -- PLB upper address bus
95	-- PLB_PAValid -- PLB primary address valid indicator
96	-- PLB_SAValid -- PLB secondary address valid indicator
97	-- PLB_rdPrim -- PLB secondary to primary read request indicator
98	-- PLB_wrPrim -- PLB secondary to primary write request indicator
99	-- PLB_masterID -- PLB current master identifier
100	-- PLB_abort -- PLB abort request indicator
101	-- PLB_busLock -- PLB bus lock
102	-- PLB_RNW -- PLB read/not write
103	-- PLB_BE -- PLB byte enables
104	-- PLB_MSize -- PLB master data bus size
105	-- PLB_size -- PLB transfer size
106	-- PLB_type -- PLB transfer type
107	-- PLB_lockErr -- PLB lock error indicator
108	-- PLB_wrDBus -- PLB write data bus
109	-- PLB_wrBurst -- PLB burst write transfer indicator
110	-- PLB_rdBurst -- PLB burst read transfer indicator
111	-- PLB_wrPendReq -- PLB write pending bus request indicator
112	-- PLB_rdPendReq -- PLB read pending bus request indicator
113	-- PLB_wrPendPri -- PLB write pending request priority
114	-- PLB_rdPendPri -- PLB read pending request priority
115	-- PLB_reqPri -- PLB current request priority
116	-- PLB_TAttribute -- PLB transfer attribute
117	-- Sl_addrAck -- Slave address acknowledge
118	-- Sl_SSize -- Slave data bus size
119	-- Sl_wait -- Slave wait indicator
120	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
121	-- Sl_wrDAck -- Slave write data acknowledge
122	-- Sl_wrComp -- Slave write transfer complete indicator
123	-- Sl_wrBTerm -- Slave terminate write burst transfer
124	-- Sl_rdDBus -- Slave read data bus
125	-- Sl_rdWdAddr -- Slave read word address
126	-- Sl_rdDAck -- Slave read data acknowledge
127	-- Sl_rdComp -- Slave read transfer complete indicator
128	-- Sl_rdBTerm -- Slave terminate read burst transfer
129	-- Sl_MBusy -- Slave busy indicator
130	-- Sl_MWrErr -- Slave write error indicator
131	-- Sl_MRdErr -- Slave read error indicator
132	-- Sl_MIRQ -- Slave interrupt indicator
133	------------------------------------------------------------------------------
134
135	entity w3_ad_controller is
136	generic
137	(
138	-- ADD USER GENERICS BELOW THIS LINE ---------------
139	--USER generics added here
140	-- ADD USER GENERICS ABOVE THIS LINE ---------------
141
142	-- DO NOT EDIT BELOW THIS LINE ---------------------
143	-- Bus protocol parameters, do not add to or delete
144	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
145	C_HIGHADDR : std_logic_vector := X"00000000";
146	C_SPLB_AWIDTH : integer := 32;
147	C_SPLB_DWIDTH : integer := 128;
148	C_SPLB_NUM_MASTERS : integer := 8;
149	C_SPLB_MID_WIDTH : integer := 3;
150	C_SPLB_NATIVE_DWIDTH : integer := 32;
151	C_SPLB_P2P : integer := 0;
152	C_SPLB_SUPPORT_BURSTS : integer := 0;
153	C_SPLB_SMALLEST_MASTER : integer := 32;
154	C_SPLB_CLK_PERIOD_PS : integer := 10000;
155	C_INCLUDE_DPHASE_TIMER : integer := 0;
156	C_FAMILY : string := "virtex6"
157	-- DO NOT EDIT ABOVE THIS LINE ---------------------
158	);
159	port
160	(
161	-- ADD USER PORTS BELOW THIS LINE ------------------
162	RFA_AD_spi_sclk : out std_logic;
163	RFA_AD_spi_cs_n : out std_logic;
164	RFA_AD_spi_sdio : inout std_logic;
165	RFA_AD_reset_n : out std_logic;
166
167	RFB_AD_spi_sclk : out std_logic;
168	RFB_AD_spi_cs_n : out std_logic;
169	RFB_AD_spi_sdio : inout std_logic;
170	RFB_AD_reset_n : out std_logic;
171
172	RFC_AD_spi_sclk : out std_logic;
173	RFC_AD_spi_cs_n : out std_logic;
174	RFC_AD_spi_sdio : inout std_logic;
175	RFC_AD_reset_n : out std_logic;
176
177	RFD_AD_spi_sclk : out std_logic;
178	RFD_AD_spi_cs_n : out std_logic;
179	RFD_AD_spi_sdio : inout std_logic;
180	RFD_AD_reset_n : out std_logic;
181
182	--USER ports added here
183	-- ADD USER PORTS ABOVE THIS LINE ------------------
184
185	-- DO NOT EDIT BELOW THIS LINE ---------------------
186	-- Bus protocol ports, do not add to or delete
187	SPLB_Clk : in std_logic;
188	SPLB_Rst : in std_logic;
189	PLB_ABus : in std_logic_vector(0 to 31);
190	PLB_UABus : in std_logic_vector(0 to 31);
191	PLB_PAValid : in std_logic;
192	PLB_SAValid : in std_logic;
193	PLB_rdPrim : in std_logic;
194	PLB_wrPrim : in std_logic;
195	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
196	PLB_abort : in std_logic;
197	PLB_busLock : in std_logic;
198	PLB_RNW : in std_logic;
199	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
200	PLB_MSize : in std_logic_vector(0 to 1);
201	PLB_size : in std_logic_vector(0 to 3);
202	PLB_type : in std_logic_vector(0 to 2);
203	PLB_lockErr : in std_logic;
204	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
205	PLB_wrBurst : in std_logic;
206	PLB_rdBurst : in std_logic;
207	PLB_wrPendReq : in std_logic;
208	PLB_rdPendReq : in std_logic;
209	PLB_wrPendPri : in std_logic_vector(0 to 1);
210	PLB_rdPendPri : in std_logic_vector(0 to 1);
211	PLB_reqPri : in std_logic_vector(0 to 1);
212	PLB_TAttribute : in std_logic_vector(0 to 15);
213	Sl_addrAck : out std_logic;
214	Sl_SSize : out std_logic_vector(0 to 1);
215	Sl_wait : out std_logic;
216	Sl_rearbitrate : out std_logic;
217	Sl_wrDAck : out std_logic;
218	Sl_wrComp : out std_logic;
219	Sl_wrBTerm : out std_logic;
220	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
221	Sl_rdWdAddr : out std_logic_vector(0 to 3);
222	Sl_rdDAck : out std_logic;
223	Sl_rdComp : out std_logic;
224	Sl_rdBTerm : out std_logic;
225	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
226	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
227	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
228	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
229	-- DO NOT EDIT ABOVE THIS LINE ---------------------
230	);
231
232	attribute MAX_FANOUT : string;
233	attribute SIGIS : string;
234
235	attribute SIGIS of SPLB_Clk : signal is "CLK";
236	attribute SIGIS of SPLB_Rst : signal is "RST";
237
238	end entity w3_ad_controller;
239
240	------------------------------------------------------------------------------
241	-- Architecture section
242	------------------------------------------------------------------------------
243
244	architecture IMP of w3_ad_controller is
245
246	------------------------------------------
247	-- Array of base/high address pairs for each address range
248	------------------------------------------
249	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
250	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
251	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
252
253	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
254	(
255	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
256	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
257	);
258
259	------------------------------------------
260	-- Array of desired number of chip enables for each address range
261	------------------------------------------
262	constant USER_SLV_NUM_REG : integer := 16;
263	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
264
265	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
266	(
267	0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
268	);
269
270	------------------------------------------
271	-- Ratio of bus clock to core clock (for use in dual clock systems)
272	-- 1 = ratio is 1:1
273	-- 2 = ratio is 2:1
274	------------------------------------------
275	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
276
277	------------------------------------------
278	-- Width of the slave data bus (32 only)
279	------------------------------------------
280	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
281
282	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
283
284	------------------------------------------
285	-- Index for CS/CE
286	------------------------------------------
287	constant USER_SLV_CS_INDEX : integer := 0;
288	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
289
290	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
291
292	------------------------------------------
293	-- IP Interconnect (IPIC) signal declarations
294	------------------------------------------
295	signal ipif_Bus2IP_Clk : std_logic;
296	signal ipif_Bus2IP_Reset : std_logic;
297	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
298	signal ipif_IP2Bus_WrAck : std_logic;
299	signal ipif_IP2Bus_RdAck : std_logic;
300	signal ipif_IP2Bus_Error : std_logic;
301	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
302	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
303	signal ipif_Bus2IP_RNW : std_logic;
304	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
305	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
306	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
307	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
308	signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
309	signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
310	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
311	signal user_IP2Bus_RdAck : std_logic;
312	signal user_IP2Bus_WrAck : std_logic;
313	signal user_IP2Bus_Error : std_logic;
314
315	------------------------------------------
316	-- Component declaration for verilog user logic
317	------------------------------------------
318	component user_logic is
319	generic
320	(
321	-- ADD USER GENERICS BELOW THIS LINE ---------------
322	--USER generics added here
323	-- ADD USER GENERICS ABOVE THIS LINE ---------------
324
325	-- DO NOT EDIT BELOW THIS LINE ---------------------
326	-- Bus protocol parameters, do not add to or delete
327	C_SLV_DWIDTH : integer := 32;
328	C_NUM_REG : integer := 16
329	-- DO NOT EDIT ABOVE THIS LINE ---------------------
330	);
331	port
332	(
333	-- ADD USER PORTS BELOW THIS LINE ------------------
334	RFA_AD_spi_sclk : out std_logic;
335	RFA_AD_spi_cs_n : out std_logic;
336	RFA_AD_spi_sdio : inout std_logic;
337	RFA_AD_reset_n : out std_logic;
338
339	RFB_AD_spi_sclk : out std_logic;
340	RFB_AD_spi_cs_n : out std_logic;
341	RFB_AD_spi_sdio : inout std_logic;
342	RFB_AD_reset_n : out std_logic;
343
344	RFC_AD_spi_sclk : out std_logic;
345	RFC_AD_spi_cs_n : out std_logic;
346	RFC_AD_spi_sdio : inout std_logic;
347	RFC_AD_reset_n : out std_logic;
348
349	RFD_AD_spi_sclk : out std_logic;
350	RFD_AD_spi_cs_n : out std_logic;
351	RFD_AD_spi_sdio : inout std_logic;
352	RFD_AD_reset_n : out std_logic;
353
354	-- ADD USER PORTS ABOVE THIS LINE ------------------
355
356	-- DO NOT EDIT BELOW THIS LINE ---------------------
357	-- Bus protocol ports, do not add to or delete
358	Bus2IP_Clk : in std_logic;
359	Bus2IP_Reset : in std_logic;
360	Bus2IP_Addr : in std_logic_vector(0 to 31);
361	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
362	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
363	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
364	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
365	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
366	IP2Bus_RdAck : out std_logic;
367	IP2Bus_WrAck : out std_logic;
368	IP2Bus_Error : out std_logic
369	-- DO NOT EDIT ABOVE THIS LINE ---------------------
370	);
371	end component user_logic;
372
373	begin
374
375	------------------------------------------
376	-- instantiate plbv46_slave_single
377	------------------------------------------
378	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
379	generic map
380	(
381	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
382	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
383	C_SPLB_P2P => C_SPLB_P2P,
384	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
385	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
386	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
387	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
388	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
389	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
390	C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
391	C_FAMILY => C_FAMILY
392	)
393	port map
394	(
395	SPLB_Clk => SPLB_Clk,
396	SPLB_Rst => SPLB_Rst,
397	PLB_ABus => PLB_ABus,
398	PLB_UABus => PLB_UABus,
399	PLB_PAValid => PLB_PAValid,
400	PLB_SAValid => PLB_SAValid,
401	PLB_rdPrim => PLB_rdPrim,
402	PLB_wrPrim => PLB_wrPrim,
403	PLB_masterID => PLB_masterID,
404	PLB_abort => PLB_abort,
405	PLB_busLock => PLB_busLock,
406	PLB_RNW => PLB_RNW,
407	PLB_BE => PLB_BE,
408	PLB_MSize => PLB_MSize,
409	PLB_size => PLB_size,
410	PLB_type => PLB_type,
411	PLB_lockErr => PLB_lockErr,
412	PLB_wrDBus => PLB_wrDBus,
413	PLB_wrBurst => PLB_wrBurst,
414	PLB_rdBurst => PLB_rdBurst,
415	PLB_wrPendReq => PLB_wrPendReq,
416	PLB_rdPendReq => PLB_rdPendReq,
417	PLB_wrPendPri => PLB_wrPendPri,
418	PLB_rdPendPri => PLB_rdPendPri,
419	PLB_reqPri => PLB_reqPri,
420	PLB_TAttribute => PLB_TAttribute,
421	Sl_addrAck => Sl_addrAck,
422	Sl_SSize => Sl_SSize,
423	Sl_wait => Sl_wait,
424	Sl_rearbitrate => Sl_rearbitrate,
425	Sl_wrDAck => Sl_wrDAck,
426	Sl_wrComp => Sl_wrComp,
427	Sl_wrBTerm => Sl_wrBTerm,
428	Sl_rdDBus => Sl_rdDBus,
429	Sl_rdWdAddr => Sl_rdWdAddr,
430	Sl_rdDAck => Sl_rdDAck,
431	Sl_rdComp => Sl_rdComp,
432	Sl_rdBTerm => Sl_rdBTerm,
433	Sl_MBusy => Sl_MBusy,
434	Sl_MWrErr => Sl_MWrErr,
435	Sl_MRdErr => Sl_MRdErr,
436	Sl_MIRQ => Sl_MIRQ,
437	Bus2IP_Clk => ipif_Bus2IP_Clk,
438	Bus2IP_Reset => ipif_Bus2IP_Reset,
439	IP2Bus_Data => ipif_IP2Bus_Data,
440	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
441	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
442	IP2Bus_Error => ipif_IP2Bus_Error,
443	Bus2IP_Addr => ipif_Bus2IP_Addr,
444	Bus2IP_Data => ipif_Bus2IP_Data,
445	Bus2IP_RNW => ipif_Bus2IP_RNW,
446	Bus2IP_BE => ipif_Bus2IP_BE,
447	Bus2IP_CS => ipif_Bus2IP_CS,
448	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
449	Bus2IP_WrCE => ipif_Bus2IP_WrCE
450	);
451
452	------------------------------------------
453	-- instantiate User Logic
454	------------------------------------------
455	USER_LOGIC_I : component user_logic
456	generic map
457	(
458	-- MAP USER GENERICS BELOW THIS LINE ---------------
459	--USER generics mapped here
460	-- MAP USER GENERICS ABOVE THIS LINE ---------------
461
462	C_SLV_DWIDTH => USER_SLV_DWIDTH,
463	C_NUM_REG => USER_NUM_REG
464	)
465	port map
466	(
467	-- MAP USER PORTS BELOW THIS LINE ------------------
468	RFA_AD_spi_sclk => RFA_AD_spi_sclk,
469	RFA_AD_spi_cs_n => RFA_AD_spi_cs_n,
470	RFA_AD_spi_sdio => RFA_AD_spi_sdio,
471	RFA_AD_reset_n => RFA_AD_reset_n,
472
473	RFB_AD_spi_sclk => RFB_AD_spi_sclk,
474	RFB_AD_spi_cs_n => RFB_AD_spi_cs_n,
475	RFB_AD_spi_sdio => RFB_AD_spi_sdio,
476	RFB_AD_reset_n => RFB_AD_reset_n,
477
478	RFC_AD_spi_sclk => RFC_AD_spi_sclk,
479	RFC_AD_spi_cs_n => RFC_AD_spi_cs_n,
480	RFC_AD_spi_sdio => RFC_AD_spi_sdio,
481	RFC_AD_reset_n => RFC_AD_reset_n,
482
483	RFD_AD_spi_sclk => RFD_AD_spi_sclk,
484	RFD_AD_spi_cs_n => RFD_AD_spi_cs_n,
485	RFD_AD_spi_sdio => RFD_AD_spi_sdio,
486	RFD_AD_reset_n => RFD_AD_reset_n,
487
488
489	-- MAP USER PORTS ABOVE THIS LINE ------------------
490
491	Bus2IP_Clk => ipif_Bus2IP_Clk,
492	Bus2IP_Reset => ipif_Bus2IP_Reset,
493	Bus2IP_Addr => ipif_Bus2IP_Addr,
494	Bus2IP_Data => ipif_Bus2IP_Data,
495	Bus2IP_BE => ipif_Bus2IP_BE,
496	Bus2IP_RdCE => user_Bus2IP_RdCE,
497	Bus2IP_WrCE => user_Bus2IP_WrCE,
498	IP2Bus_Data => user_IP2Bus_Data,
499	IP2Bus_RdAck => user_IP2Bus_RdAck,
500	IP2Bus_WrAck => user_IP2Bus_WrAck,
501	IP2Bus_Error => user_IP2Bus_Error
502	);
503
504	------------------------------------------
505	-- connect internal signals
506	------------------------------------------
507	ipif_IP2Bus_Data <= user_IP2Bus_Data;
508	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
509	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
510	ipif_IP2Bus_Error <= user_IP2Bus_Error;
511
512	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
513	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
514
515	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/w3_ad_controller_v3_01_a/hdl/vhdl/w3_ad_controller.vhd

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