[1766] | 1 | #ifndef WARP_AD_CONTROLLER_H |
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| 2 | #define WARP_AD_CONTROLLER_H |
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| 3 | |
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| 4 | #include "xbasic_types.h" |
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| 5 | #include "xstatus.h" |
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| 6 | #include "xil_io.h" |
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| 7 | |
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| 8 | #define WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET (0x00000000) |
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| 9 | #define WARP_AD_CONTROLLER_SLV_REG0_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000000) |
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| 10 | #define WARP_AD_CONTROLLER_SLV_REG1_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000004) |
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| 11 | #define WARP_AD_CONTROLLER_SLV_REG2_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000008) |
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| 12 | #define WARP_AD_CONTROLLER_SLV_REG3_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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| 13 | #define WARP_AD_CONTROLLER_SLV_REG4_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000010) |
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| 14 | #define WARP_AD_CONTROLLER_SLV_REG5_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000014) |
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| 15 | #define WARP_AD_CONTROLLER_SLV_REG6_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000018) |
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| 16 | #define WARP_AD_CONTROLLER_SLV_REG7_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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| 17 | #define WARP_AD_CONTROLLER_SLV_REG8_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000020) |
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| 18 | #define WARP_AD_CONTROLLER_SLV_REG9_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000024) |
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| 19 | #define WARP_AD_CONTROLLER_SLV_REG10_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000028) |
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| 20 | #define WARP_AD_CONTROLLER_SLV_REG11_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x0000002C) |
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| 21 | #define WARP_AD_CONTROLLER_SLV_REG12_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000030) |
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| 22 | #define WARP_AD_CONTROLLER_SLV_REG13_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000034) |
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| 23 | #define WARP_AD_CONTROLLER_SLV_REG14_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000038) |
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| 24 | #define WARP_AD_CONTROLLER_SLV_REG15_OFFSET (WARP_AD_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x0000003C) |
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| 25 | |
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| 26 | |
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| 27 | |
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| 28 | /* Address map: |
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| 29 | HDL is coded [MSB:LSB] = [0:31] |
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| 30 | regX[0] maps to 0x80000000 in C driver |
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| 31 | regX[31] maps to 0x00000001 in C driver |
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| 32 | |
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[1865] | 33 | 0: Config: {clk_div_sel[2:0], 1'b0, RFA_AD_rst_n, RFB_AD_rst_n, 26'b0} |
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[1766] | 34 | [29:31] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x00000003 |
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| 35 | [28 ] Reserved |
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[1865] | 36 | [ 27] RFA_AD reset (active low) 0x00000010 |
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| 37 | [ 26] RFB_AD reset (active low) 0x00000020 |
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| 38 | [ 25] RFC_AD reset (active low) 0x00000040 |
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| 39 | [ 24] RFD_AD reset (active low) 0x00000080 |
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| 40 | [0 :23] Reserved |
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[1766] | 41 | |
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| 42 | 1: SPI Tx |
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| 43 | [24:31] Tx data byte |
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| 44 | [16:23] 8-bit register address (0x00 to 0xFF all valid) |
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| 45 | [11:15] 5'b0 (always zero) |
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| 46 | [ 9:10] Num bytes to Tx/Rx; must be 2'b0 for 1-byte Tx/Rx |
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| 47 | [ 8] RW# 1=Read, 0=Write |
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[1865] | 48 | [ 7] RFA_AD chip select mask |
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| 49 | [ 6] RFB_AD chip select mask |
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| 50 | [ 5] RFC_AD chip select mask |
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| 51 | [ 4] RFD_AD chip select mask |
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| 52 | [ 0: 3] Reserved |
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[1766] | 53 | |
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[1865] | 54 | 2: SPI Rx: {RFA_AD_rxByte, RFB_AD_rxByte, RFC_AD_rxByte, RFD_AD_rxByte} |
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| 55 | [24:31] SPI Rx byte for RFA_AD 0x000000FF |
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| 56 | [16:23] SPI Rx byte for RFB_AD 0x0000FF00 |
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| 57 | [ 8:15] SPI Rx byte for RFC_AD 0x00FF0000 |
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| 58 | [ 0: 7] SPI Rx byte for RFD_AD 0xFF000000 |
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[1766] | 59 | |
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| 60 | 3-15: Reserved |
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| 61 | */ |
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| 62 | |
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[1865] | 63 | #define AD_CTRL_ALL_RF_CS (RFA_AD_CS | RFB_AD_CS | RFC_AD_CS | RFD_AD_CS) |
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| 64 | |
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[1766] | 65 | #define ADCTRL_REG_CONFIG WARP_AD_CONTROLLER_SLV_REG0_OFFSET |
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| 66 | #define ADCTRL_REG_SPITX WARP_AD_CONTROLLER_SLV_REG1_OFFSET |
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| 67 | #define ADCTRL_REG_SPIRX WARP_AD_CONTROLLER_SLV_REG2_OFFSET |
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| 68 | |
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| 69 | #define ADCTRL_REG_CONFIG_MASK_CLKDIV 0x03 |
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| 70 | #define ADCTRL_REG_CONFIG_MASK_RFA_AD_RESET 0x10 |
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| 71 | #define ADCTRL_REG_CONFIG_MASK_RFB_AD_RESET 0x20 |
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[1865] | 72 | #define ADCTRL_REG_CONFIG_MASK_RFC_AD_RESET 0x40 |
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| 73 | #define ADCTRL_REG_CONFIG_MASK_RFD_AD_RESET 0x80 |
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[1766] | 74 | |
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| 75 | #define ADCTRL_REG_SPITX_RFA_AD_CS 0x01000000 |
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| 76 | #define ADCTRL_REG_SPITX_RFB_AD_CS 0x02000000 |
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| 77 | #define ADCTRL_REG_SPITX_RFC_AD_CS 0x04000000 |
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| 78 | #define ADCTRL_REG_SPITX_RFD_AD_CS 0x08000000 |
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| 79 | #define ADCTRL_REG_SPITX_RNW 0x00800000 |
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| 80 | |
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| 81 | //Shorter versions for user code |
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| 82 | #define AD_CHAN_I 1 |
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| 83 | #define AD_CHAN_Q 2 |
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| 84 | |
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[1788] | 85 | #define AD_DACCLKSRC_DLL 0x40 |
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| 86 | #define AD_DACCLKSRC_EXT 0x00 |
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| 87 | |
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| 88 | #define AD_ADCCLKSRC_DLL 0x80 |
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| 89 | #define AD_ADCCLKSRC_EXT 0x00 |
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| 90 | |
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| 91 | #define AD_DCS_ON 0x0 |
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| 92 | #define AD_DCS_OFF 0x4 |
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| 93 | |
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[1792] | 94 | #define AD_ADCCLKDIV_1 0x1 |
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| 95 | #define AD_ADCCLKDIV_2 0x2 |
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| 96 | #define AD_ADCCLKDIV_4 0x3 |
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[1788] | 97 | |
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[1792] | 98 | #define AD_PWR_ALLOFF 1 |
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| 99 | #define AD_PWR_ALLON 2 |
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| 100 | |
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[1766] | 101 | #define RFA_AD_CS ADCTRL_REG_SPITX_RFA_AD_CS |
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| 102 | #define RFB_AD_CS ADCTRL_REG_SPITX_RFB_AD_CS |
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| 103 | #define RFC_AD_CS ADCTRL_REG_SPITX_RFC_AD_CS |
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| 104 | #define RFD_AD_CS ADCTRL_REG_SPITX_RFD_AD_CS |
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| 105 | |
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| 106 | |
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| 107 | //Functions |
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| 108 | u32 ad_spi_read(u32 baseaddr, u32 csMask, u8 regAddr); |
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| 109 | void ad_spi_write(u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte); |
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[1868] | 110 | int ad_init(u32 baseaddr, u32 adSel, u8 clkdiv); |
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[1766] | 111 | |
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[1788] | 112 | int ad_set_TxDCO(u32 baseaddr, u32 csMask, u8 iqSel, u16 dco); |
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| 113 | int ad_set_TxGain1(u32 baseaddr, u32 csMask, u8 iqSel, u8 gain); |
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| 114 | int ad_set_TxGain2(u32 baseaddr, u32 csMask, u8 iqSel, u8 gain); |
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| 115 | int ad_config_DLL(u32 baseaddr, u32 csMask, u8 DLL_En, u8 DLL_M, u8 DLL_N, u8 DLL_DIV); |
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| 116 | int ad_config_clocks(u32 baseaddr, u32 csMask, u8 DAC_clkSrc, u8 ADC_clkSrc, u8 ADC_clkDiv, u8 ADC_DCS); |
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| 117 | int ad_config_filters(u32 baseaddr, u32 csMask, u8 interpRate, u8 decimationRate); |
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[1766] | 118 | |
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| 119 | #endif /** WARP_AD_CONTROLLER_H */ |
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