| 1 | ###################################################################
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| 2 | # Copyright (c) 2015 Mango Communications
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| 3 | # All Rights Reserved
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| 4 | # This code is covered by the WARP license
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| 5 | # See http://warpproject.org/license/ for details
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| 6 | ###################################################################
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| 7 |
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| 8 | BEGIN w3_boot_io_mux
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| 9 |
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| 10 | ## Peripheral Options
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| 11 | OPTION IPTYPE = PERIPHERAL
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| 12 | OPTION IMP_NETLIST = TRUE
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| 13 | OPTION HDL = VERILOG
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| 14 | OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
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| 15 | OPTION USAGE_LEVEL = BASE_USER
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| 16 | OPTION DESC = "WARP v3 Mux for I/O at Boot"
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| 17 | OPTION IP_GROUP = USER
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| 18 | OPTION RUN_NGCBUILD = FALSE
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| 19 | OPTION STYLE = HDL
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| 20 |
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| 21 | IO_INTERFACE IO_IF = IIC, IO_TYPE = W3_BOOTIOMUX_V1
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| 22 | IO_INTERFACE IO_IF = UART, IO_TYPE = W3_BOOTIOMUX_V1
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| 23 |
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| 24 | PARAMETER C_FAMILY = virtex6, DT = STRING
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| 25 |
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| 26 | PORT iic_scl = "", DIR = IO, THREE_STATE = FALSE, IO_IF = IIC, IO_IS = IIC_SCL
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| 27 | PORT iic_sda = "", DIR = IO, THREE_STATE = FALSE, IO_IF = IIC, IO_IS = IIC_SDA
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| 28 |
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| 29 | PORT iic_scl_I_a = "", DIR = O, IO_IF = IIC, IO_IS = A_IIC_SCL_I
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| 30 | PORT iic_scl_O_a = "", DIR = I, IO_IF = IIC, IO_IS = A_IIC_SCL_O
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| 31 | PORT iic_scl_T_a = "", DIR = I, IO_IF = IIC, IO_IS = A_IIC_SCL_T
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| 32 |
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| 33 | PORT iic_scl_I_b = "", DIR = O, IO_IF = IIC, IO_IS = B_IIC_SCL_I
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| 34 | PORT iic_scl_O_b = "", DIR = I, IO_IF = IIC, IO_IS = B_IIC_SCL_O
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| 35 | PORT iic_scl_T_b = "", DIR = I, IO_IF = IIC, IO_IS = B_IIC_SCL_T
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| 36 |
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| 37 | PORT iic_sda_I_a = "", DIR = O, IO_IF = IIC, IO_IS = A_IIC_SDA_I
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| 38 | PORT iic_sda_O_a = "", DIR = I, IO_IF = IIC, IO_IS = A_IIC_SDA_O
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| 39 | PORT iic_sda_T_a = "", DIR = I, IO_IF = IIC, IO_IS = A_IIC_SDA_T
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| 40 |
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| 41 | PORT iic_sda_I_b = "", DIR = O, IO_IF = IIC, IO_IS = B_IIC_SDA_I
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| 42 | PORT iic_sda_O_b = "", DIR = I, IO_IF = IIC, IO_IS = B_IIC_SDA_O
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| 43 | PORT iic_sda_T_b = "", DIR = I, IO_IF = IIC, IO_IS = B_IIC_SDA_T
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| 44 |
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| 45 | PORT iic_sel_a = "", DIR = I, IO_IF = IIC, IO_IS = IIC_PORT_SEL
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| 46 |
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| 47 |
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| 48 | PORT uart_tx = "", DIR = O, IO_IF = UART, IO_IS = UART_TX
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| 49 |
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| 50 | PORT uart_tx_a = "", DIR = I, IO_IF = UART, IO_IS = UART_TX_A
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| 51 | PORT uart_tx_b = "", DIR = I, IO_IF = UART, IO_IS = UART_TX_B
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| 52 |
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| 53 | PORT uart_sel_a = "", DIR = I, IO_IF = UART, IO_IS = UART_PORT_SEL
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| 54 |
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| 55 | END
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