source: PlatformSupport/CustomPeripherals/pcores/w3_boot_io_mux_v1_00_a/hdl/verilog/w3_boot_io_mux.v

module w3_boot_io_mux (
    inout iic_scl,
    inout iic_sda,

    output iic_scl_I_a,
    input  iic_scl_O_a,
    input  iic_scl_T_a,

    output iic_sda_I_a,
    input  iic_sda_O_a,
    input  iic_sda_T_a,

    output iic_scl_I_b,
    input  iic_scl_O_b,
    input  iic_scl_T_b,

    output iic_sda_I_b,
    input  iic_sda_O_b,
    input  iic_sda_T_b,

    input  iic_sel_a,

    output uart_tx,

    input  uart_tx_a,
    input  uart_tx_b,

    input  uart_sel_a
);

parameter C_FAMILY = "virtex6";

wire iic_scl_I, iic_scl_O, iic_scl_T;
wire iic_sda_I, iic_sda_O, iic_sda_T;

//Hold unselected IIC IOB->logic signals high, matching idle level of actual IIC signals
assign iic_scl_I_a = (iic_sel_a == 1'b1) ? iic_scl_I : 1'b1;
assign iic_scl_I_b = (iic_sel_a == 1'b1) ? 1'b1 : iic_scl_I;

assign iic_sda_I_a = (iic_sel_a == 1'b1) ? iic_sda_I : 1'b1;
assign iic_sda_I_b = (iic_sel_a == 1'b1) ? 1'b1 : iic_sda_I;

assign iic_scl_T = (iic_sel_a == 1'b1) ? iic_scl_T_a : iic_scl_T_b;
assign iic_scl_O = (iic_sel_a == 1'b1) ? iic_scl_O_a : iic_scl_O_b;

assign iic_sda_T = (iic_sel_a == 1'b1) ? iic_sda_T_a : iic_sda_T_b;
assign iic_sda_O = (iic_sel_a == 1'b1) ? iic_sda_O_a : iic_sda_O_b;

IOBUF IOBUF_scl (
    .IO(iic_scl), //Connected to actual FPGA pin
    .I(iic_scl_O), //Logic-> Pad, input to OBUFT
    .O(iic_scl_I), //Pad-> Logic, output of IBUF
    .T(iic_scl_T)
);

IOBUF IOBUF_sda (
    .IO(iic_sda), //Connected to actual FPGA pin
    .I(iic_sda_O), //Logic-> Pad, input to OBUFT
    .O(iic_sda_I), //Pad-> Logic, output of IBUF
    .T(iic_sda_T)
);

assign uart_tx = (uart_sel_a == 1'b1) ? uart_tx_a : uart_tx_b;

endmodule