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w3_clock_controller_axi.vhd

Last change on this file was 3909, checked in by welsh, 10 years ago
Updating clock controller software.
File size: 20.3 KB

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1	------------------------------------------------------------------------------
2	-- w3_clock_controller_axi.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: w3_clock_controller_axi.vhd
36	-- Version: 3.01.b
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Sat Feb 23 21:53:35 2013 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68
69	library axi_lite_ipif_v1_01_a;
70	use axi_lite_ipif_v1_01_a.axi_lite_ipif;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
77	-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
78	-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
79	-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
80	-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
81	-- C_BASEADDR -- AXI4LITE slave: base address
82	-- C_HIGHADDR -- AXI4LITE slave: high address
83	-- C_FAMILY -- FPGA Family
84	-- C_NUM_REG -- Number of software accessible registers
85	-- C_NUM_MEM -- Number of address-ranges
86	-- C_SLV_AWIDTH -- Slave interface address bus width
87	-- C_SLV_DWIDTH -- Slave interface data bus width
88	--
89	-- Definition of Ports:
90	-- S_AXI_ACLK -- AXI4LITE slave: Clock
91	-- S_AXI_ARESETN -- AXI4LITE slave: Reset
92	-- S_AXI_AWADDR -- AXI4LITE slave: Write address
93	-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
94	-- S_AXI_WDATA -- AXI4LITE slave: Write data
95	-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
96	-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
97	-- S_AXI_BREADY -- AXI4LITE slave: Response ready
98	-- S_AXI_ARADDR -- AXI4LITE slave: Read address
99	-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
100	-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
101	-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
102	-- S_AXI_RDATA -- AXI4LITE slave: Read data
103	-- S_AXI_RRESP -- AXI4LITE slave: Read data response
104	-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
105	-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
106	-- S_AXI_BRESP -- AXI4LITE slave: Response
107	-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
108	-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
109	------------------------------------------------------------------------------
110
111	entity w3_clock_controller_axi is
112	generic
113	(
114	-- ADD USER GENERICS BELOW THIS LINE ---------------
115	--USER generics added here
116	-- ADD USER GENERICS ABOVE THIS LINE ---------------
117
118	-- DO NOT EDIT BELOW THIS LINE ---------------------
119	-- Bus protocol parameters, do not add to or delete
120	C_S_AXI_DATA_WIDTH : integer := 32;
121	C_S_AXI_ADDR_WIDTH : integer := 32;
122	C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
123	C_USE_WSTRB : integer := 0;
124	C_DPHASE_TIMEOUT : integer := 8;
125	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
126	C_HIGHADDR : std_logic_vector := X"00000000";
127	C_FAMILY : string := "virtex6";
128	C_NUM_REG : integer := 1;
129	C_NUM_MEM : integer := 1;
130	C_SLV_AWIDTH : integer := 32;
131	C_SLV_DWIDTH : integer := 32
132	-- DO NOT EDIT ABOVE THIS LINE ---------------------
133	);
134	port
135	(
136	-- ADD USER PORTS BELOW THIS LINE ------------------
137	at_boot_clk_in : in std_logic;
138	at_boot_clk_in_valid : in std_logic;
139	at_boot_config_sw : in std_logic_vector(1 downto 0);
140	at_boot_clkbuf_clocks_invalid : out std_logic;
141
142	samp_spi_sclk : out std_logic;
143	samp_spi_mosi : out std_logic;
144	samp_spi_miso : in std_logic;
145	samp_spi_cs_n : out std_logic;
146	samp_func : out std_logic;
147
148	rfref_spi_sclk : out std_logic;
149	rfref_spi_mosi : out std_logic;
150	rfref_spi_miso : in std_logic;
151	rfref_spi_cs_n : out std_logic;
152	rfref_func : out std_logic;
153
154	usr_reset0 : out std_logic;
155	usr_reset1 : out std_logic;
156	usr_reset2 : out std_logic;
157	usr_reset3 : out std_logic;
158	usr_status : in std_logic_vector(0 to 31);
159	-- ADD USER PORTS ABOVE THIS LINE ------------------
160
161	-- DO NOT EDIT BELOW THIS LINE ---------------------
162	-- Bus protocol ports, do not add to or delete
163	S_AXI_ACLK : in std_logic;
164	S_AXI_ARESETN : in std_logic;
165	S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
166	S_AXI_AWVALID : in std_logic;
167	S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
168	S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
169	S_AXI_WVALID : in std_logic;
170	S_AXI_BREADY : in std_logic;
171	S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
172	S_AXI_ARVALID : in std_logic;
173	S_AXI_RREADY : in std_logic;
174	S_AXI_ARREADY : out std_logic;
175	S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
176	S_AXI_RRESP : out std_logic_vector(1 downto 0);
177	S_AXI_RVALID : out std_logic;
178	S_AXI_WREADY : out std_logic;
179	S_AXI_BRESP : out std_logic_vector(1 downto 0);
180	S_AXI_BVALID : out std_logic;
181	S_AXI_AWREADY : out std_logic
182	-- DO NOT EDIT ABOVE THIS LINE ---------------------
183	);
184
185	attribute MAX_FANOUT : string;
186	attribute SIGIS : string;
187	attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
188	attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
189	attribute SIGIS of S_AXI_ACLK : signal is "Clk";
190	attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
191	end entity w3_clock_controller_axi;
192
193	------------------------------------------------------------------------------
194	-- Architecture section
195	------------------------------------------------------------------------------
196
197	architecture IMP of w3_clock_controller_axi is
198
199	constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
200
201	constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
202
203	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
204	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
205	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
206
207	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
208	(
209	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
210	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
211	);
212
213	constant USER_SLV_NUM_REG : integer := 8;
214	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
215	constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
216
217	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
218	(
219	0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
220	);
221
222	------------------------------------------
223	-- Index for CS/CE
224	------------------------------------------
225	constant USER_SLV_CS_INDEX : integer := 0;
226	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
227
228	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
229
230	------------------------------------------
231	-- IP Interconnect (IPIC) signal declarations
232	------------------------------------------
233	signal ipif_Bus2IP_Clk : std_logic;
234	signal ipif_Bus2IP_Resetn : std_logic;
235	signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
236	signal ipif_Bus2IP_RNW : std_logic;
237	signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
238	signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
239	signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
240	signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
241	signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
242	signal ipif_IP2Bus_WrAck : std_logic;
243	signal ipif_IP2Bus_RdAck : std_logic;
244	signal ipif_IP2Bus_Error : std_logic;
245	signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
246	signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
247	signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
248	signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
249	signal user_IP2Bus_RdAck : std_logic;
250	signal user_IP2Bus_WrAck : std_logic;
251	signal user_IP2Bus_Error : std_logic;
252
253	------------------------------------------
254	-- Component declaration for verilog user logic
255	------------------------------------------
256	component user_logic is
257	generic
258	(
259	-- ADD USER GENERICS BELOW THIS LINE ---------------
260	--USER generics added here
261	-- ADD USER GENERICS ABOVE THIS LINE ---------------
262
263	-- DO NOT EDIT BELOW THIS LINE ---------------------
264	-- Bus protocol parameters, do not add to or delete
265	C_NUM_REG : integer := 8;
266	C_SLV_DWIDTH : integer := 32
267	-- DO NOT EDIT ABOVE THIS LINE ---------------------
268	);
269	port
270	(
271	-- ADD USER PORTS BELOW THIS LINE ------------------
272	at_boot_clk_in : in std_logic;
273	at_boot_clk_in_valid : in std_logic;
274	at_boot_config_sw : in std_logic_vector(1 downto 0);
275	at_boot_clkbuf_clocks_invalid : out std_logic;
276
277	samp_spi_sclk : out std_logic;
278	samp_spi_mosi : out std_logic;
279	samp_spi_miso : in std_logic;
280	samp_spi_cs_n : out std_logic;
281	samp_func : out std_logic;
282
283	rfref_spi_sclk : out std_logic;
284	rfref_spi_mosi : out std_logic;
285	rfref_spi_miso : in std_logic;
286	rfref_spi_cs_n : out std_logic;
287	rfref_func : out std_logic;
288
289	usr_reset0 : out std_logic;
290	usr_reset1 : out std_logic;
291	usr_reset2 : out std_logic;
292	usr_reset3 : out std_logic;
293	usr_status : in std_logic_vector(31 downto 0);
294	-- ADD USER PORTS ABOVE THIS LINE ------------------
295
296	-- DO NOT EDIT BELOW THIS LINE ---------------------
297	-- Bus protocol ports, do not add to or delete
298	Bus2IP_Clk : in std_logic;
299	Bus2IP_Resetn : in std_logic;
300	Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
301	Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
302	Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
303	Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
304	IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
305	IP2Bus_RdAck : out std_logic;
306	IP2Bus_WrAck : out std_logic;
307	IP2Bus_Error : out std_logic
308	-- DO NOT EDIT ABOVE THIS LINE ---------------------
309	);
310	end component user_logic;
311
312	begin
313
314	------------------------------------------
315	-- instantiate axi_lite_ipif
316	------------------------------------------
317	AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
318	generic map
319	(
320	C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
321	C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
322	C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
323	C_USE_WSTRB => C_USE_WSTRB,
324	C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
325	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
326	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
327	C_FAMILY => C_FAMILY
328	)
329	port map
330	(
331	S_AXI_ACLK => S_AXI_ACLK,
332	S_AXI_ARESETN => S_AXI_ARESETN,
333	S_AXI_AWADDR => S_AXI_AWADDR,
334	S_AXI_AWVALID => S_AXI_AWVALID,
335	S_AXI_WDATA => S_AXI_WDATA,
336	S_AXI_WSTRB => S_AXI_WSTRB,
337	S_AXI_WVALID => S_AXI_WVALID,
338	S_AXI_BREADY => S_AXI_BREADY,
339	S_AXI_ARADDR => S_AXI_ARADDR,
340	S_AXI_ARVALID => S_AXI_ARVALID,
341	S_AXI_RREADY => S_AXI_RREADY,
342	S_AXI_ARREADY => S_AXI_ARREADY,
343	S_AXI_RDATA => S_AXI_RDATA,
344	S_AXI_RRESP => S_AXI_RRESP,
345	S_AXI_RVALID => S_AXI_RVALID,
346	S_AXI_WREADY => S_AXI_WREADY,
347	S_AXI_BRESP => S_AXI_BRESP,
348	S_AXI_BVALID => S_AXI_BVALID,
349	S_AXI_AWREADY => S_AXI_AWREADY,
350	Bus2IP_Clk => ipif_Bus2IP_Clk,
351	Bus2IP_Resetn => ipif_Bus2IP_Resetn,
352	Bus2IP_Addr => ipif_Bus2IP_Addr,
353	Bus2IP_RNW => ipif_Bus2IP_RNW,
354	Bus2IP_BE => ipif_Bus2IP_BE,
355	Bus2IP_CS => ipif_Bus2IP_CS,
356	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
357	Bus2IP_WrCE => ipif_Bus2IP_WrCE,
358	Bus2IP_Data => ipif_Bus2IP_Data,
359	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
360	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
361	IP2Bus_Error => ipif_IP2Bus_Error,
362	IP2Bus_Data => ipif_IP2Bus_Data
363	);
364
365	------------------------------------------
366	-- instantiate User Logic
367	------------------------------------------
368	USER_LOGIC_I : component user_logic
369	generic map
370	(
371	-- MAP USER GENERICS BELOW THIS LINE ---------------
372	--USER generics mapped here
373	-- MAP USER GENERICS ABOVE THIS LINE ---------------
374
375	C_NUM_REG => USER_NUM_REG,
376	C_SLV_DWIDTH => USER_SLV_DWIDTH
377	)
378	port map
379	(
380	-- MAP USER PORTS BELOW THIS LINE ------------------
381	at_boot_clk_in => at_boot_clk_in,
382	at_boot_clk_in_valid => at_boot_clk_in_valid,
383	at_boot_clkbuf_clocks_invalid => at_boot_clkbuf_clocks_invalid,
384	at_boot_config_sw => at_boot_config_sw,
385
386	samp_spi_sclk => samp_spi_sclk,
387	samp_spi_mosi => samp_spi_mosi,
388	samp_spi_miso => samp_spi_miso,
389	samp_spi_cs_n => samp_spi_cs_n,
390	samp_func => samp_func,
391
392	rfref_spi_sclk => rfref_spi_sclk,
393	rfref_spi_mosi => rfref_spi_mosi,
394	rfref_spi_miso => rfref_spi_miso,
395	rfref_spi_cs_n => rfref_spi_cs_n,
396	rfref_func => rfref_func,
397	usr_reset0 => usr_reset0,
398	usr_reset1 => usr_reset1,
399	usr_reset2 => usr_reset2,
400	usr_reset3 => usr_reset3,
401	usr_status => usr_status,
402	-- MAP USER PORTS ABOVE THIS LINE ------------------
403
404	Bus2IP_Clk => ipif_Bus2IP_Clk,
405	Bus2IP_Resetn => ipif_Bus2IP_Resetn,
406	Bus2IP_Data => ipif_Bus2IP_Data,
407	Bus2IP_BE => ipif_Bus2IP_BE,
408	Bus2IP_RdCE => user_Bus2IP_RdCE,
409	Bus2IP_WrCE => user_Bus2IP_WrCE,
410	IP2Bus_Data => user_IP2Bus_Data,
411	IP2Bus_RdAck => user_IP2Bus_RdAck,
412	IP2Bus_WrAck => user_IP2Bus_WrAck,
413	IP2Bus_Error => user_IP2Bus_Error
414	);
415
416	------------------------------------------
417	-- connect internal signals
418	------------------------------------------
419	ipif_IP2Bus_Data <= user_IP2Bus_Data;
420	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
421	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
422	ipif_IP2Bus_Error <= user_IP2Bus_Error;
423
424	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
425	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
426
427	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v3_01_b/hdl/vhdl/w3_clock_controller_axi.vhd

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