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kcpsm6.v

Last change on this file was 4287, checked in by murphpo, 9 years ago
First version of clock controller pcore with support for cm-pll module
File size: 80.9 KB

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1	//
2	///////////////////////////////////////////////////////////////////////////////////////////
3	// Copyright © 2010-2014, Xilinx, Inc.
4	// This file contains confidential and proprietary information of Xilinx, Inc. and is
5	// protected under U.S. and international copyright and other intellectual property laws.
6	///////////////////////////////////////////////////////////////////////////////////////////
7	//
8	// Disclaimer:
9	// This disclaimer is not a license and does not grant any rights to the materials
10	// distributed herewith. Except as otherwise provided in a valid license issued to
11	// you by Xilinx, and to the maximum extent permitted by applicable law: [1] THESE
12	// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
13	// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
14	// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
15	// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
16	// (whether in contract or tort, including negligence, or under any other theory
17	// of liability) for any loss or damage of any kind or nature related to, arising
18	// under or in connection with these materials, including for any direct, or any
19	// indirect, special, incidental, or consequential loss or damage (including loss
20	// of data, profits, goodwill, or any type of loss or damage suffered as a result
21	// of any action brought by a third party) even if such damage or loss was
22	// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
23	//
24	// CRITICAL APPLICATIONS
25	// Xilinx products are not designed or intended to be fail-safe, or for use in any
26	// application requiring fail-safe performance, such as life-support or safety
27	// devices or systems, Class III medical devices, nuclear facilities, applications
28	// related to the deployment of airbags, or any other applications that could lead
29	// to death, personal injury, or severe property or environmental damage
30	// (individually and collectively, "Critical Applications)). Customer assumes the
31	// sole risk and liability of any use of Xilinx products in Critical Applications,
32	// subject only to applicable laws and regulations governing limitations on product
33	// liability.
34	//
35	// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
36	//
37	///////////////////////////////////////////////////////////////////////////////////////////
38	//
39	// KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
40	//
41	// Version 1.1 - 4th March 2010.
42	// Derived from kcpsm6.vhd Version 1.1 (9th February 2011) by Nick Sawyer.
43	// Version 1.2 - 4th October 2012.
44	// Addition of WebTalk information.
45	// Version 1.3 - 21st May 2014.
46	// Disassembly of 'STAR sX, kk' instruction added to the simulation
47	// code. No changes to functionality or the physical implementation.
48	//
49	// Ken Chapman
50	// Xilinx Ltd
51	// Benchmark House
52	// 203 Brooklands Road
53	// Weybridge
54	// Surrey KT13 ORH
55	// United Kingdom
56	//
57	// chapman@xilinx.com
58	//
59	///////////////////////////////////////////////////////////////////////////////////////////
60	//
61	// Format of this file.
62	//
63	// The module defines the implementation of the logic using Xilinx primitives.
64	// These ensure predictable synthesis results and maximise the density of the implementation.
65	// The Unisim Library is used to define Xilinx primitives. It is also used during
66	// simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
67	//
68	///////////////////////////////////////////////////////////////////////////////////////////
69	//
70	`timescale 1ps/1ps
71	//
72	///////////////////////////////////////////////////////////////////////////////////////////
73	//
74	// Main Entity for kcpsm6 with WebTalk Attributes
75	//
76	(* CORE_GENERATION_INFO = "kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}" *)
77	module kcpsm6 (address, instruction, bram_enable, in_port, out_port, port_id, write_strobe, k_write_strobe, read_strobe, interrupt, interrupt_ack, sleep, reset, clk) ;
78
79	parameter [7:0] hwbuild = 8'h00 ;
80	parameter [11:0] interrupt_vector = 12'h3FF ;
81	parameter integer scratch_pad_memory_size = 64 ;
82
83	output [11:0] address ;
84	input [17:0] instruction ;
85	output bram_enable ;
86	input [7:0] in_port ;
87	output [7:0] out_port ;
88	output [7:0] port_id ;
89	output write_strobe ;
90	output k_write_strobe ;
91	output read_strobe ;
92	input interrupt ;
93	output interrupt_ack ;
94	input sleep ;
95	input reset ;
96	input clk ;
97	//
98	///////////////////////////////////////////////////////////////////////////////////////////
99	//
100	// Start of Main Architecture for kcpsm6
101	//
102	///////////////////////////////////////////////////////////////////////////////////////////
103	//
104	// Signals used in kcpsm6
105	//
106	///////////////////////////////////////////////////////////////////////////////////////////
107	//
108	// State Machine and Interrupt
109	//
110	wire [2:1] t_state_value ;
111	wire [2:1] t_state ;
112	wire run_value ;
113	wire run ;
114	wire internal_reset_value ;
115	wire internal_reset ;
116	wire sync_sleep ;
117	wire int_enable_type ;
118	wire interrupt_enable_value ;
119	wire interrupt_enable ;
120	wire sync_interrupt ;
121	wire active_interrupt_value ;
122	wire active_interrupt ;
123	//
124	// Arithmetic and Logical Functions
125	//
126	wire [2:0] arith_logical_sel ;
127	wire arith_carry_in ;
128	wire arith_carry_value ;
129	wire arith_carry ;
130	wire [7:0] half_arith_logical ;
131	wire [7:0] logical_carry_mask ;
132	wire [7:0] carry_arith_logical ;
133	wire [7:0] arith_logical_value ;
134	wire [7:0] arith_logical_result ;
135	//
136	// Shift and Rotate Functions
137	//
138	wire [7:0] shift_rotate_value ;
139	wire [7:0] shift_rotate_result ;
140	wire shift_in_bit ;
141	//
142	// ALU structure
143	//
144	wire [7:0] alu_result ;
145	wire [1:0] alu_mux_sel_value ;
146	wire [1:0] alu_mux_sel ;
147	//
148	// Strobes
149	//
150	wire strobe_type ;
151	wire write_strobe_value ;
152	wire k_write_strobe_value ;
153	wire read_strobe_value ;
154	//
155	// Flags
156	//
157	wire flag_enable_type ;
158	wire flag_enable_value ;
159	wire flag_enable ;
160	wire lower_parity ;
161	wire lower_parity_sel ;
162	wire carry_lower_parity ;
163	wire upper_parity ;
164	wire parity ;
165	wire shift_carry_value ;
166	wire shift_carry ;
167	wire carry_flag_value ;
168	wire carry_flag ;
169
170	wire use_zero_flag_value ;
171	wire use_zero_flag ;
172	wire drive_carry_in_zero ;
173	wire carry_in_zero ;
174	wire lower_zero ;
175	wire lower_zero_sel ;
176	wire carry_lower_zero ;
177	wire middle_zero ;
178	wire middle_zero_sel ;
179	wire carry_middle_zero ;
180	wire upper_zero_sel ;
181	wire zero_flag_value ;
182	wire zero_flag ;
183	//
184	// Scratch Pad Memory
185	//
186	wire spm_enable_value ;
187	wire spm_enable ;
188	wire [7:0] spm_ram_data ;
189	wire [7:0] spm_data ;
190	//
191	// Registers
192	//
193	wire regbank_type ;
194	wire bank_value ;
195	wire bank ;
196	wire loadstar_type ;
197	wire sx_addr4_value ;
198	wire register_enable_type ;
199	wire register_enable_value ;
200	wire register_enable ;
201	wire [4:0] sx_addr ;
202	wire [4:0] sy_addr ;
203	wire [7:0] sx ;
204	wire [7:0] sy ;
205	//
206	// Second Operand
207	//
208	wire [7:0] sy_or_kk ;
209	//
210	// Program Counter
211	//
212	wire pc_move_is_valid ;
213	wire move_type ;
214	wire returni_type ;
215	wire [2:0] pc_mode ;
216	wire [11:0] register_vector ;
217	wire [11:0] half_pc ;
218	wire [10:0] carry_pc ;
219	wire [11:0] pc_value ;
220	wire [11:0] pc ;
221	wire [11:0] pc_vector ;
222	//
223	// Program Counter Stack
224	//
225	wire push_stack ;
226	wire pop_stack ;
227	wire [11:0] stack_memory ;
228	wire [11:0] return_vector ;
229	wire stack_carry_flag ;
230	wire shadow_carry_flag ;
231	wire stack_zero_flag ;
232	wire shadow_zero_value ;
233	wire shadow_zero_flag ;
234	wire stack_bank ;
235	wire shadow_bank ;
236	wire stack_bit ;
237	wire special_bit ;
238	wire [4:0] half_pointer_value ;
239	wire [4:0] feed_pointer_value ;
240	wire [4:0] stack_pointer_carry ;
241	wire [4:0] stack_pointer_value ;
242	wire [4:0] stack_pointer ;
243	//
244	//
245	//
246	//**********************************************************************************
247	//
248	// Signals between these *** lines are only made visible during simulation
249	//
250	//synthesis translate_off
251	//
252	reg [1:152] kcpsm6_opcode ;
253	reg [1:128] kcpsm6_status ;
254	reg [7:0] sim_s0 ;
255	reg [7:0] sim_s1 ;
256	reg [7:0] sim_s2 ;
257	reg [7:0] sim_s3 ;
258	reg [7:0] sim_s4 ;
259	reg [7:0] sim_s5 ;
260	reg [7:0] sim_s6 ;
261	reg [7:0] sim_s7 ;
262	reg [7:0] sim_s8 ;
263	reg [7:0] sim_s9 ;
264	reg [7:0] sim_sA ;
265	reg [7:0] sim_sB ;
266	reg [7:0] sim_sC ;
267	reg [7:0] sim_sD ;
268	reg [7:0] sim_sE ;
269	reg [7:0] sim_sF ;
270	reg [7:0] sim_spm00 ;
271	reg [7:0] sim_spm01 ;
272	reg [7:0] sim_spm02 ;
273	reg [7:0] sim_spm03 ;
274	reg [7:0] sim_spm04 ;
275	reg [7:0] sim_spm05 ;
276	reg [7:0] sim_spm06 ;
277	reg [7:0] sim_spm07 ;
278	reg [7:0] sim_spm08 ;
279	reg [7:0] sim_spm09 ;
280	reg [7:0] sim_spm0A ;
281	reg [7:0] sim_spm0B ;
282	reg [7:0] sim_spm0C ;
283	reg [7:0] sim_spm0D ;
284	reg [7:0] sim_spm0E ;
285	reg [7:0] sim_spm0F ;
286	reg [7:0] sim_spm10 ;
287	reg [7:0] sim_spm11 ;
288	reg [7:0] sim_spm12 ;
289	reg [7:0] sim_spm13 ;
290	reg [7:0] sim_spm14 ;
291	reg [7:0] sim_spm15 ;
292	reg [7:0] sim_spm16 ;
293	reg [7:0] sim_spm17 ;
294	reg [7:0] sim_spm18 ;
295	reg [7:0] sim_spm19 ;
296	reg [7:0] sim_spm1A ;
297	reg [7:0] sim_spm1B ;
298	reg [7:0] sim_spm1C ;
299	reg [7:0] sim_spm1D ;
300	reg [7:0] sim_spm1E ;
301	reg [7:0] sim_spm1F ;
302	reg [7:0] sim_spm20 ;
303	reg [7:0] sim_spm21 ;
304	reg [7:0] sim_spm22 ;
305	reg [7:0] sim_spm23 ;
306	reg [7:0] sim_spm24 ;
307	reg [7:0] sim_spm25 ;
308	reg [7:0] sim_spm26 ;
309	reg [7:0] sim_spm27 ;
310	reg [7:0] sim_spm28 ;
311	reg [7:0] sim_spm29 ;
312	reg [7:0] sim_spm2A ;
313	reg [7:0] sim_spm2B ;
314	reg [7:0] sim_spm2C ;
315	reg [7:0] sim_spm2D ;
316	reg [7:0] sim_spm2E ;
317	reg [7:0] sim_spm2F ;
318	reg [7:0] sim_spm30 ;
319	reg [7:0] sim_spm31 ;
320	reg [7:0] sim_spm32 ;
321	reg [7:0] sim_spm33 ;
322	reg [7:0] sim_spm34 ;
323	reg [7:0] sim_spm35 ;
324	reg [7:0] sim_spm36 ;
325	reg [7:0] sim_spm37 ;
326	reg [7:0] sim_spm38 ;
327	reg [7:0] sim_spm39 ;
328	reg [7:0] sim_spm3A ;
329	reg [7:0] sim_spm3B ;
330	reg [7:0] sim_spm3C ;
331	reg [7:0] sim_spm3D ;
332	reg [7:0] sim_spm3E ;
333	reg [7:0] sim_spm3F ;
334	reg [7:0] sim_spm40 ;
335	reg [7:0] sim_spm41 ;
336	reg [7:0] sim_spm42 ;
337	reg [7:0] sim_spm43 ;
338	reg [7:0] sim_spm44 ;
339	reg [7:0] sim_spm45 ;
340	reg [7:0] sim_spm46 ;
341	reg [7:0] sim_spm47 ;
342	reg [7:0] sim_spm48 ;
343	reg [7:0] sim_spm49 ;
344	reg [7:0] sim_spm4A ;
345	reg [7:0] sim_spm4B ;
346	reg [7:0] sim_spm4C ;
347	reg [7:0] sim_spm4D ;
348	reg [7:0] sim_spm4E ;
349	reg [7:0] sim_spm4F ;
350	reg [7:0] sim_spm50 ;
351	reg [7:0] sim_spm51 ;
352	reg [7:0] sim_spm52 ;
353	reg [7:0] sim_spm53 ;
354	reg [7:0] sim_spm54 ;
355	reg [7:0] sim_spm55 ;
356	reg [7:0] sim_spm56 ;
357	reg [7:0] sim_spm57 ;
358	reg [7:0] sim_spm58 ;
359	reg [7:0] sim_spm59 ;
360	reg [7:0] sim_spm5A ;
361	reg [7:0] sim_spm5B ;
362	reg [7:0] sim_spm5C ;
363	reg [7:0] sim_spm5D ;
364	reg [7:0] sim_spm5E ;
365	reg [7:0] sim_spm5F ;
366	reg [7:0] sim_spm60 ;
367	reg [7:0] sim_spm61 ;
368	reg [7:0] sim_spm62 ;
369	reg [7:0] sim_spm63 ;
370	reg [7:0] sim_spm64 ;
371	reg [7:0] sim_spm65 ;
372	reg [7:0] sim_spm66 ;
373	reg [7:0] sim_spm67 ;
374	reg [7:0] sim_spm68 ;
375	reg [7:0] sim_spm69 ;
376	reg [7:0] sim_spm6A ;
377	reg [7:0] sim_spm6B ;
378	reg [7:0] sim_spm6C ;
379	reg [7:0] sim_spm6D ;
380	reg [7:0] sim_spm6E ;
381	reg [7:0] sim_spm6F ;
382	reg [7:0] sim_spm70 ;
383	reg [7:0] sim_spm71 ;
384	reg [7:0] sim_spm72 ;
385	reg [7:0] sim_spm73 ;
386	reg [7:0] sim_spm74 ;
387	reg [7:0] sim_spm75 ;
388	reg [7:0] sim_spm76 ;
389	reg [7:0] sim_spm77 ;
390	reg [7:0] sim_spm78 ;
391	reg [7:0] sim_spm79 ;
392	reg [7:0] sim_spm7A ;
393	reg [7:0] sim_spm7B ;
394	reg [7:0] sim_spm7C ;
395	reg [7:0] sim_spm7D ;
396	reg [7:0] sim_spm7E ;
397	reg [7:0] sim_spm7F ;
398	reg [7:0] sim_spm80 ;
399	reg [7:0] sim_spm81 ;
400	reg [7:0] sim_spm82 ;
401	reg [7:0] sim_spm83 ;
402	reg [7:0] sim_spm84 ;
403	reg [7:0] sim_spm85 ;
404	reg [7:0] sim_spm86 ;
405	reg [7:0] sim_spm87 ;
406	reg [7:0] sim_spm88 ;
407	reg [7:0] sim_spm89 ;
408	reg [7:0] sim_spm8A ;
409	reg [7:0] sim_spm8B ;
410	reg [7:0] sim_spm8C ;
411	reg [7:0] sim_spm8D ;
412	reg [7:0] sim_spm8E ;
413	reg [7:0] sim_spm8F ;
414	reg [7:0] sim_spm90 ;
415	reg [7:0] sim_spm91 ;
416	reg [7:0] sim_spm92 ;
417	reg [7:0] sim_spm93 ;
418	reg [7:0] sim_spm94 ;
419	reg [7:0] sim_spm95 ;
420	reg [7:0] sim_spm96 ;
421	reg [7:0] sim_spm97 ;
422	reg [7:0] sim_spm98 ;
423	reg [7:0] sim_spm99 ;
424	reg [7:0] sim_spm9A ;
425	reg [7:0] sim_spm9B ;
426	reg [7:0] sim_spm9C ;
427	reg [7:0] sim_spm9D ;
428	reg [7:0] sim_spm9E ;
429	reg [7:0] sim_spm9F ;
430	reg [7:0] sim_spmA0 ;
431	reg [7:0] sim_spmA1 ;
432	reg [7:0] sim_spmA2 ;
433	reg [7:0] sim_spmA3 ;
434	reg [7:0] sim_spmA4 ;
435	reg [7:0] sim_spmA5 ;
436	reg [7:0] sim_spmA6 ;
437	reg [7:0] sim_spmA7 ;
438	reg [7:0] sim_spmA8 ;
439	reg [7:0] sim_spmA9 ;
440	reg [7:0] sim_spmAA ;
441	reg [7:0] sim_spmAB ;
442	reg [7:0] sim_spmAC ;
443	reg [7:0] sim_spmAD ;
444	reg [7:0] sim_spmAE ;
445	reg [7:0] sim_spmAF ;
446	reg [7:0] sim_spmB0 ;
447	reg [7:0] sim_spmB1 ;
448	reg [7:0] sim_spmB2 ;
449	reg [7:0] sim_spmB3 ;
450	reg [7:0] sim_spmB4 ;
451	reg [7:0] sim_spmB5 ;
452	reg [7:0] sim_spmB6 ;
453	reg [7:0] sim_spmB7 ;
454	reg [7:0] sim_spmB8 ;
455	reg [7:0] sim_spmB9 ;
456	reg [7:0] sim_spmBA ;
457	reg [7:0] sim_spmBB ;
458	reg [7:0] sim_spmBC ;
459	reg [7:0] sim_spmBD ;
460	reg [7:0] sim_spmBE ;
461	reg [7:0] sim_spmBF ;
462	reg [7:0] sim_spmC0 ;
463	reg [7:0] sim_spmC1 ;
464	reg [7:0] sim_spmC2 ;
465	reg [7:0] sim_spmC3 ;
466	reg [7:0] sim_spmC4 ;
467	reg [7:0] sim_spmC5 ;
468	reg [7:0] sim_spmC6 ;
469	reg [7:0] sim_spmC7 ;
470	reg [7:0] sim_spmC8 ;
471	reg [7:0] sim_spmC9 ;
472	reg [7:0] sim_spmCA ;
473	reg [7:0] sim_spmCB ;
474	reg [7:0] sim_spmCC ;
475	reg [7:0] sim_spmCD ;
476	reg [7:0] sim_spmCE ;
477	reg [7:0] sim_spmCF ;
478	reg [7:0] sim_spmD0 ;
479	reg [7:0] sim_spmD1 ;
480	reg [7:0] sim_spmD2 ;
481	reg [7:0] sim_spmD3 ;
482	reg [7:0] sim_spmD4 ;
483	reg [7:0] sim_spmD5 ;
484	reg [7:0] sim_spmD6 ;
485	reg [7:0] sim_spmD7 ;
486	reg [7:0] sim_spmD8 ;
487	reg [7:0] sim_spmD9 ;
488	reg [7:0] sim_spmDA ;
489	reg [7:0] sim_spmDB ;
490	reg [7:0] sim_spmDC ;
491	reg [7:0] sim_spmDD ;
492	reg [7:0] sim_spmDE ;
493	reg [7:0] sim_spmDF ;
494	reg [7:0] sim_spmE0 ;
495	reg [7:0] sim_spmE1 ;
496	reg [7:0] sim_spmE2 ;
497	reg [7:0] sim_spmE3 ;
498	reg [7:0] sim_spmE4 ;
499	reg [7:0] sim_spmE5 ;
500	reg [7:0] sim_spmE6 ;
501	reg [7:0] sim_spmE7 ;
502	reg [7:0] sim_spmE8 ;
503	reg [7:0] sim_spmE9 ;
504	reg [7:0] sim_spmEA ;
505	reg [7:0] sim_spmEB ;
506	reg [7:0] sim_spmEC ;
507	reg [7:0] sim_spmED ;
508	reg [7:0] sim_spmEE ;
509	reg [7:0] sim_spmEF ;
510	reg [7:0] sim_spmF0 ;
511	reg [7:0] sim_spmF1 ;
512	reg [7:0] sim_spmF2 ;
513	reg [7:0] sim_spmF3 ;
514	reg [7:0] sim_spmF4 ;
515	reg [7:0] sim_spmF5 ;
516	reg [7:0] sim_spmF6 ;
517	reg [7:0] sim_spmF7 ;
518	reg [7:0] sim_spmF8 ;
519	reg [7:0] sim_spmF9 ;
520	reg [7:0] sim_spmFA ;
521	reg [7:0] sim_spmFB ;
522	reg [7:0] sim_spmFC ;
523	reg [7:0] sim_spmFD ;
524	reg [7:0] sim_spmFE ;
525	reg [7:0] sim_spmFF ;
526	//
527	// initialise the values
528	//
529	initial begin
530	kcpsm6_status = "A,NZ,NC,ID,Reset" ;
531	kcpsm6_opcode = "LOAD s0, s0 " ;
532
533	sim_s0 = 8'h00 ;
534	sim_s1 = 8'h00 ;
535	sim_s2 = 8'h00 ;
536	sim_s3 = 8'h00 ;
537	sim_s4 = 8'h00 ;
538	sim_s5 = 8'h00 ;
539	sim_s6 = 8'h00 ;
540	sim_s7 = 8'h00 ;
541	sim_s8 = 8'h00 ;
542	sim_s9 = 8'h00 ;
543	sim_sA = 8'h00 ;
544	sim_sB = 8'h00 ;
545	sim_sC = 8'h00 ;
546	sim_sD = 8'h00 ;
547	sim_sE = 8'h00 ;
548	sim_sF = 8'h00 ;
549
550	sim_spm00 = 8'h00 ;
551	sim_spm01 = 8'h00 ;
552	sim_spm02 = 8'h00 ;
553	sim_spm03 = 8'h00 ;
554	sim_spm04 = 8'h00 ;
555	sim_spm05 = 8'h00 ;
556	sim_spm06 = 8'h00 ;
557	sim_spm07 = 8'h00 ;
558	sim_spm08 = 8'h00 ;
559	sim_spm09 = 8'h00 ;
560	sim_spm0A = 8'h00 ;
561	sim_spm0B = 8'h00 ;
562	sim_spm0C = 8'h00 ;
563	sim_spm0D = 8'h00 ;
564	sim_spm0E = 8'h00 ;
565	sim_spm0F = 8'h00 ;
566	sim_spm10 = 8'h00 ;
567	sim_spm11 = 8'h00 ;
568	sim_spm12 = 8'h00 ;
569	sim_spm13 = 8'h00 ;
570	sim_spm14 = 8'h00 ;
571	sim_spm15 = 8'h00 ;
572	sim_spm16 = 8'h00 ;
573	sim_spm17 = 8'h00 ;
574	sim_spm18 = 8'h00 ;
575	sim_spm19 = 8'h00 ;
576	sim_spm1A = 8'h00 ;
577	sim_spm1B = 8'h00 ;
578	sim_spm1C = 8'h00 ;
579	sim_spm1D = 8'h00 ;
580	sim_spm1E = 8'h00 ;
581	sim_spm1F = 8'h00 ;
582	sim_spm20 = 8'h00 ;
583	sim_spm21 = 8'h00 ;
584	sim_spm22 = 8'h00 ;
585	sim_spm23 = 8'h00 ;
586	sim_spm24 = 8'h00 ;
587	sim_spm25 = 8'h00 ;
588	sim_spm26 = 8'h00 ;
589	sim_spm27 = 8'h00 ;
590	sim_spm28 = 8'h00 ;
591	sim_spm29 = 8'h00 ;
592	sim_spm2A = 8'h00 ;
593	sim_spm2B = 8'h00 ;
594	sim_spm2C = 8'h00 ;
595	sim_spm2D = 8'h00 ;
596	sim_spm2E = 8'h00 ;
597	sim_spm2F = 8'h00 ;
598	sim_spm30 = 8'h00 ;
599	sim_spm31 = 8'h00 ;
600	sim_spm32 = 8'h00 ;
601	sim_spm33 = 8'h00 ;
602	sim_spm34 = 8'h00 ;
603	sim_spm35 = 8'h00 ;
604	sim_spm36 = 8'h00 ;
605	sim_spm37 = 8'h00 ;
606	sim_spm38 = 8'h00 ;
607	sim_spm39 = 8'h00 ;
608	sim_spm3A = 8'h00 ;
609	sim_spm3B = 8'h00 ;
610	sim_spm3C = 8'h00 ;
611	sim_spm3D = 8'h00 ;
612	sim_spm3E = 8'h00 ;
613	sim_spm3F = 8'h00 ;
614	sim_spm40 = 8'h00 ;
615	sim_spm41 = 8'h00 ;
616	sim_spm42 = 8'h00 ;
617	sim_spm43 = 8'h00 ;
618	sim_spm44 = 8'h00 ;
619	sim_spm45 = 8'h00 ;
620	sim_spm46 = 8'h00 ;
621	sim_spm47 = 8'h00 ;
622	sim_spm48 = 8'h00 ;
623	sim_spm49 = 8'h00 ;
624	sim_spm4A = 8'h00 ;
625	sim_spm4B = 8'h00 ;
626	sim_spm4C = 8'h00 ;
627	sim_spm4D = 8'h00 ;
628	sim_spm4E = 8'h00 ;
629	sim_spm4F = 8'h00 ;
630	sim_spm50 = 8'h00 ;
631	sim_spm51 = 8'h00 ;
632	sim_spm52 = 8'h00 ;
633	sim_spm53 = 8'h00 ;
634	sim_spm54 = 8'h00 ;
635	sim_spm55 = 8'h00 ;
636	sim_spm56 = 8'h00 ;
637	sim_spm57 = 8'h00 ;
638	sim_spm58 = 8'h00 ;
639	sim_spm59 = 8'h00 ;
640	sim_spm5A = 8'h00 ;
641	sim_spm5B = 8'h00 ;
642	sim_spm5C = 8'h00 ;
643	sim_spm5D = 8'h00 ;
644	sim_spm5E = 8'h00 ;
645	sim_spm5F = 8'h00 ;
646	sim_spm60 = 8'h00 ;
647	sim_spm61 = 8'h00 ;
648	sim_spm62 = 8'h00 ;
649	sim_spm63 = 8'h00 ;
650	sim_spm64 = 8'h00 ;
651	sim_spm65 = 8'h00 ;
652	sim_spm66 = 8'h00 ;
653	sim_spm67 = 8'h00 ;
654	sim_spm68 = 8'h00 ;
655	sim_spm69 = 8'h00 ;
656	sim_spm6A = 8'h00 ;
657	sim_spm6B = 8'h00 ;
658	sim_spm6C = 8'h00 ;
659	sim_spm6D = 8'h00 ;
660	sim_spm6E = 8'h00 ;
661	sim_spm6F = 8'h00 ;
662	sim_spm70 = 8'h00 ;
663	sim_spm71 = 8'h00 ;
664	sim_spm72 = 8'h00 ;
665	sim_spm73 = 8'h00 ;
666	sim_spm74 = 8'h00 ;
667	sim_spm75 = 8'h00 ;
668	sim_spm76 = 8'h00 ;
669	sim_spm77 = 8'h00 ;
670	sim_spm78 = 8'h00 ;
671	sim_spm79 = 8'h00 ;
672	sim_spm7A = 8'h00 ;
673	sim_spm7B = 8'h00 ;
674	sim_spm7C = 8'h00 ;
675	sim_spm7D = 8'h00 ;
676	sim_spm7E = 8'h00 ;
677	sim_spm7F = 8'h00 ;
678	sim_spm80 = 8'h00 ;
679	sim_spm81 = 8'h00 ;
680	sim_spm82 = 8'h00 ;
681	sim_spm83 = 8'h00 ;
682	sim_spm84 = 8'h00 ;
683	sim_spm85 = 8'h00 ;
684	sim_spm86 = 8'h00 ;
685	sim_spm87 = 8'h00 ;
686	sim_spm88 = 8'h00 ;
687	sim_spm89 = 8'h00 ;
688	sim_spm8A = 8'h00 ;
689	sim_spm8B = 8'h00 ;
690	sim_spm8C = 8'h00 ;
691	sim_spm8D = 8'h00 ;
692	sim_spm8E = 8'h00 ;
693	sim_spm8F = 8'h00 ;
694	sim_spm90 = 8'h00 ;
695	sim_spm91 = 8'h00 ;
696	sim_spm92 = 8'h00 ;
697	sim_spm93 = 8'h00 ;
698	sim_spm94 = 8'h00 ;
699	sim_spm95 = 8'h00 ;
700	sim_spm96 = 8'h00 ;
701	sim_spm97 = 8'h00 ;
702	sim_spm98 = 8'h00 ;
703	sim_spm99 = 8'h00 ;
704	sim_spm9A = 8'h00 ;
705	sim_spm9B = 8'h00 ;
706	sim_spm9C = 8'h00 ;
707	sim_spm9D = 8'h00 ;
708	sim_spm9E = 8'h00 ;
709	sim_spm9F = 8'h00 ;
710	sim_spmA0 = 8'h00 ;
711	sim_spmA1 = 8'h00 ;
712	sim_spmA2 = 8'h00 ;
713	sim_spmA3 = 8'h00 ;
714	sim_spmA4 = 8'h00 ;
715	sim_spmA5 = 8'h00 ;
716	sim_spmA6 = 8'h00 ;
717	sim_spmA7 = 8'h00 ;
718	sim_spmA8 = 8'h00 ;
719	sim_spmA9 = 8'h00 ;
720	sim_spmAA = 8'h00 ;
721	sim_spmAB = 8'h00 ;
722	sim_spmAC = 8'h00 ;
723	sim_spmAD = 8'h00 ;
724	sim_spmAE = 8'h00 ;
725	sim_spmAF = 8'h00 ;
726	sim_spmB0 = 8'h00 ;
727	sim_spmB1 = 8'h00 ;
728	sim_spmB2 = 8'h00 ;
729	sim_spmB3 = 8'h00 ;
730	sim_spmB4 = 8'h00 ;
731	sim_spmB5 = 8'h00 ;
732	sim_spmB6 = 8'h00 ;
733	sim_spmB7 = 8'h00 ;
734	sim_spmB8 = 8'h00 ;
735	sim_spmB9 = 8'h00 ;
736	sim_spmBA = 8'h00 ;
737	sim_spmBB = 8'h00 ;
738	sim_spmBC = 8'h00 ;
739	sim_spmBD = 8'h00 ;
740	sim_spmBE = 8'h00 ;
741	sim_spmBF = 8'h00 ;
742	sim_spmC0 = 8'h00 ;
743	sim_spmC1 = 8'h00 ;
744	sim_spmC2 = 8'h00 ;
745	sim_spmC3 = 8'h00 ;
746	sim_spmC4 = 8'h00 ;
747	sim_spmC5 = 8'h00 ;
748	sim_spmC6 = 8'h00 ;
749	sim_spmC7 = 8'h00 ;
750	sim_spmC8 = 8'h00 ;
751	sim_spmC9 = 8'h00 ;
752	sim_spmCA = 8'h00 ;
753	sim_spmCB = 8'h00 ;
754	sim_spmCC = 8'h00 ;
755	sim_spmCD = 8'h00 ;
756	sim_spmCE = 8'h00 ;
757	sim_spmCF = 8'h00 ;
758	sim_spmD0 = 8'h00 ;
759	sim_spmD1 = 8'h00 ;
760	sim_spmD2 = 8'h00 ;
761	sim_spmD3 = 8'h00 ;
762	sim_spmD4 = 8'h00 ;
763	sim_spmD5 = 8'h00 ;
764	sim_spmD6 = 8'h00 ;
765	sim_spmD7 = 8'h00 ;
766	sim_spmD8 = 8'h00 ;
767	sim_spmD9 = 8'h00 ;
768	sim_spmDA = 8'h00 ;
769	sim_spmDB = 8'h00 ;
770	sim_spmDC = 8'h00 ;
771	sim_spmDD = 8'h00 ;
772	sim_spmDE = 8'h00 ;
773	sim_spmDF = 8'h00 ;
774	sim_spmE0 = 8'h00 ;
775	sim_spmE1 = 8'h00 ;
776	sim_spmE2 = 8'h00 ;
777	sim_spmE3 = 8'h00 ;
778	sim_spmE4 = 8'h00 ;
779	sim_spmE5 = 8'h00 ;
780	sim_spmE6 = 8'h00 ;
781	sim_spmE7 = 8'h00 ;
782	sim_spmE8 = 8'h00 ;
783	sim_spmE9 = 8'h00 ;
784	sim_spmEA = 8'h00 ;
785	sim_spmEB = 8'h00 ;
786	sim_spmEC = 8'h00 ;
787	sim_spmED = 8'h00 ;
788	sim_spmEE = 8'h00 ;
789	sim_spmEF = 8'h00 ;
790	sim_spmF0 = 8'h00 ;
791	sim_spmF1 = 8'h00 ;
792	sim_spmF2 = 8'h00 ;
793	sim_spmF3 = 8'h00 ;
794	sim_spmF4 = 8'h00 ;
795	sim_spmF5 = 8'h00 ;
796	sim_spmF6 = 8'h00 ;
797	sim_spmF7 = 8'h00 ;
798	sim_spmF8 = 8'h00 ;
799	sim_spmF9 = 8'h00 ;
800	sim_spmFA = 8'h00 ;
801	sim_spmFB = 8'h00 ;
802	sim_spmFC = 8'h00 ;
803	sim_spmFD = 8'h00 ;
804	sim_spmFE = 8'h00 ;
805	sim_spmFF = 8'h00 ;
806	end
807	//
808	//synthesis translate_on
809	//
810	//**********************************************************************************
811	//
812	//
813	///////////////////////////////////////////////////////////////////////////////////////////
814	//
815	//
816	// Start of kcpsm6 circuit description
817	//
818	// Summary of all primitives defined.
819	//
820	// 29 x LUT6 79 LUTs
821	// 50 x LUT6_2
822	// 48 x FD 82 flip-flops
823	// 20 x FDR (Depending on the value of 'hwbuild' up)
824	// 0 x FDS (to eight FDR will be replaced by FDS )
825	// 14 x FDRE
826	// 29 x MUXCY
827	// 27 x XORCY
828	// 4 x RAM32M (16 LUTs)
829	//
830	// 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
831	// (8 LUTs) (16 LUTs) (32 LUTs)
832	//
833	///////////////////////////////////////////////////////////////////////////////////////////
834	//
835	//
836	///////////////////////////////////////////////////////////////////////////////////////////
837	//
838	// Perform check of generic to report error as soon as possible.
839	//
840	///////////////////////////////////////////////////////////////////////////////////////////
841	//
842	initial begin
843	if (scratch_pad_memory_size != 64 && scratch_pad_memory_size != 128 && scratch_pad_memory_size != 256) begin
844	#1;
845	$display("\n\nInvalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256.\n\n");
846	$finish;
847	end
848	end
849	//
850	///////////////////////////////////////////////////////////////////////////////////////////
851	//
852	// State Machine and Control
853	//
854	//
855	// 1 x LUT6
856	// 4 x LUT6_2
857	// 9 x FD
858	//
859	///////////////////////////////////////////////////////////////////////////////////////////
860	//
861
862	(* HBLKNM = "kcpsm6_control" *)
863	LUT6_2 #(
864	.INIT (64'hFFFFF55500000EEE))
865	reset_lut(
866	.I0 (run),
867	.I1 (internal_reset),
868	.I2 (stack_pointer_carry[4]),
869	.I3 (t_state[2]),
870	.I4 (reset),
871	.I5 (1'b1),
872	.O5 (run_value),
873	.O6 (internal_reset_value));
874
875	(* HBLKNM = "kcpsm6_control" *)
876	FD run_flop (
877	.D (run_value),
878	.Q (run),
879	.C (clk));
880
881	(* HBLKNM = "kcpsm6_control" *)
882	FD internal_reset_flop(
883	.D (internal_reset_value),
884	.Q (internal_reset),
885	.C (clk));
886
887	(* HBLKNM = "kcpsm6_decode2" *)
888	FD sync_sleep_flop(
889	.D (sleep),
890	.Q (sync_sleep),
891	.C (clk));
892
893	(* HBLKNM = "kcpsm6_control" *)
894	LUT6_2 #(
895	.INIT (64'h0083000B00C4004C))
896	t_state_lut(
897	.I0 (t_state[1]),
898	.I1 (t_state[2]),
899	.I2 (sync_sleep),
900	.I3 (internal_reset),
901	.I4 (special_bit),
902	.I5 (1'b1),
903	.O5 (t_state_value[1]),
904	.O6 (t_state_value[2]));
905
906	(* HBLKNM = "kcpsm6_control" *)
907	FD t_state1_flop (
908	.D (t_state_value[1]),
909	.Q (t_state[1]),
910	.C (clk));
911
912	(* HBLKNM = "kcpsm6_control" *)
913	FD t_state2_flop (
914	.D (t_state_value[2]),
915	.Q (t_state[2]),
916	.C (clk));
917
918
919	(* HBLKNM = "kcpsm6_decode0" *)
920	LUT6_2 #(
921	.INIT (64'h0010000000000800))
922	int_enable_type_lut(
923	.I0 (instruction[13]),
924	.I1 (instruction[14]),
925	.I2 (instruction[15]),
926	.I3 (instruction[16]),
927	.I4 (instruction[17]),
928	.I5 (1'b1),
929	.O5 (loadstar_type),
930	.O6 (int_enable_type)) ;
931
932	(* HBLKNM = "kcpsm6_decode0" *)
933	LUT6 #(
934	.INIT (64'h000000000000CAAA))
935	interrupt_enable_lut(
936	.I0 (interrupt_enable),
937	.I1 (instruction[0]),
938	.I2 (int_enable_type),
939	.I3 (t_state[1]),
940	.I4 (active_interrupt),
941	.I5 (internal_reset),
942	.O (interrupt_enable_value));
943
944	(* HBLKNM = "kcpsm6_decode0" *)
945	FD interrupt_enable_flop (
946	.D (interrupt_enable_value),
947	.Q (interrupt_enable),
948	.C (clk));
949
950	(* HBLKNM = "kcpsm6_decode2" *)
951	FD sync_interrupt_flop (
952	.D (interrupt),
953	.Q (sync_interrupt),
954	.C (clk));
955
956	(* HBLKNM = "kcpsm6_control" *)
957	LUT6_2 # (
958	.INIT (64'hCC33FF0080808080))
959	active_interrupt_lut(
960	.I0 (interrupt_enable),
961	.I1 (t_state[2]),
962	.I2 (sync_interrupt),
963	.I3 (bank),
964	.I4 (loadstar_type),
965	.I5 (1'b1),
966	.O5 (active_interrupt_value),
967	.O6 (sx_addr4_value));
968
969	(* HBLKNM = "kcpsm6_control" *)
970	FD active_interrupt_flop (
971	.D (active_interrupt_value),
972	.Q (active_interrupt),
973	.C (clk));
974
975	(* HBLKNM = "kcpsm6_decode1" *)
976	FD interrupt_ack_flop (
977	.D (active_interrupt),
978	.Q (interrupt_ack),
979	.C (clk));
980	//
981	///////////////////////////////////////////////////////////////////////////////////////////
982	//
983	// Decoders
984	//
985	//
986	// 2 x LUT6
987	// 10 x LUT6_2
988	// 2 x FD
989	// 6 x FDR
990	//
991	///////////////////////////////////////////////////////////////////////////////////////////
992	//
993
994	//
995	// Decoding for Program Counter and Stack
996	//
997
998	(* HBLKNM = "kcpsm6_decode0" *)
999	LUT6 #(
1000	.INIT (64'h5A3CFFFF00000000))
1001	pc_move_is_valid_lut(
1002	.I0 (carry_flag),
1003	.I1 (zero_flag),
1004	.I2 (instruction[14]),
1005	.I3 (instruction[15]),
1006	.I4 (instruction[16]),
1007	.I5 (instruction[17]),
1008	.O (pc_move_is_valid)) ;
1009
1010	(* HBLKNM = "kcpsm6_decode0" *)
1011	LUT6_2 # (
1012	.INIT (64'h7777027700000200))
1013	move_type_lut(
1014	.I0 (instruction[12]),
1015	.I1 (instruction[13]),
1016	.I2 (instruction[14]),
1017	.I3 (instruction[15]),
1018	.I4 (instruction[16]),
1019	.I5 (1'b1),
1020	.O5 (returni_type),
1021	.O6 (move_type)) ;
1022
1023	(* HBLKNM = "kcpsm6_vector1" *)
1024	LUT6_2 # (
1025	.INIT (64'h0000F000000023FF))
1026	pc_mode1_lut(
1027	.I0 (instruction[12]),
1028	.I1 (returni_type),
1029	.I2 (move_type),
1030	.I3 (pc_move_is_valid),
1031	.I4 (active_interrupt),
1032	.I5 (1'b1),
1033	.O5 (pc_mode[0]),
1034	.O6 (pc_mode[1])) ;
1035
1036	(* HBLKNM = "kcpsm6_vector1" *)
1037	LUT6 # (
1038	.INIT (64'hFFFFFFFF00040000))
1039	pc_mode2_lut(
1040	.I0 (instruction[12]),
1041	.I1 (instruction[14]),
1042	.I2 (instruction[15]),
1043	.I3 (instruction[16]),
1044	.I4 (instruction[17]),
1045	.I5 (active_interrupt),
1046	.O (pc_mode[2])) ;
1047
1048	(* HBLKNM = "kcpsm6_stack1" *)
1049	LUT6_2 # (
1050	.INIT (64'hFFFF100000002000))
1051	push_pop_lut(
1052	.I0 (instruction[12]),
1053	.I1 (instruction[13]),
1054	.I2 (move_type),
1055	.I3 (pc_move_is_valid),
1056	.I4 (active_interrupt),
1057	.I5 (1'b1),
1058	.O5 (pop_stack),
1059	.O6 (push_stack)) ;
1060
1061	//
1062	// Decoding for ALU
1063	//
1064
1065	(* HBLKNM = "kcpsm6_decode2" *)
1066	LUT6_2 #(
1067	.INIT (64'h03CA000004200000))
1068	alu_decode0_lut(
1069	.I0 (instruction[13]),
1070	.I1 (instruction[14]),
1071	.I2 (instruction[15]),
1072	.I3 (instruction[16]),
1073	.I4 (1'b1),
1074	.I5 (1'b1),
1075	.O5 (alu_mux_sel_value[0]),
1076	.O6 (arith_logical_sel[0])) ;
1077
1078	(* HBLKNM = "kcpsm6_decode2" *)
1079	FD alu_mux_sel0_flop(
1080	.D (alu_mux_sel_value[0]),
1081	.Q (alu_mux_sel[0]),
1082	.C (clk)) ;
1083
1084	(* HBLKNM = "kcpsm6_decode1" *)
1085	LUT6_2 #(
1086	.INIT (64'h7708000000000F00))
1087	alu_decode1_lut(
1088	.I0 (carry_flag),
1089	.I1 (instruction[13]),
1090	.I2 (instruction[14]),
1091	.I3 (instruction[15]),
1092	.I4 (instruction[16]),
1093	.I5 (1'b1),
1094	.O5 (alu_mux_sel_value[1]),
1095	.O6 (arith_carry_in)) ;
1096
1097	(* HBLKNM = "kcpsm6_decode1" *)
1098	FD alu_mux_sel1_flop (
1099	.D (alu_mux_sel_value[1]),
1100	.Q (alu_mux_sel[1]),
1101	.C (clk)) ;
1102
1103
1104	(* HBLKNM = "kcpsm6_decode2" *)
1105	LUT6_2 # (
1106	.INIT (64'hD000000002000000))
1107	alu_decode2_lut(
1108	.I0 (instruction[14]),
1109	.I1 (instruction[15]),
1110	.I2 (instruction[16]),
1111	.I3 (1'b1),
1112	.I4 (1'b1),
1113	.I5 (1'b1),
1114	.O5 (arith_logical_sel[1]),
1115	.O6 (arith_logical_sel[2])) ;
1116
1117	//
1118	// Decoding for strobes and enables
1119	//
1120
1121	(* HBLKNM = "kcpsm6_strobes" *)
1122	LUT6_2 # (
1123	.INIT (64'h00013F3F0010F7CE))
1124	register_enable_type_lut(
1125	.I0 (instruction[13]),
1126	.I1 (instruction[14]),
1127	.I2 (instruction[15]),
1128	.I3 (instruction[16]),
1129	.I4 (instruction[17]),
1130	.I5 (1'b1),
1131	.O5 (flag_enable_type),
1132	.O6 (register_enable_type)) ;
1133
1134	(* HBLKNM = "kcpsm6_strobes" *)
1135	LUT6_2 # (
1136	.INIT (64'hC0CC0000A0AA0000))
1137	register_enable_lut(
1138	.I0 (flag_enable_type),
1139	.I1 (register_enable_type),
1140	.I2 (instruction[12]),
1141	.I3 (instruction[17]),
1142	.I4 (t_state[1]),
1143	.I5 (1'b1),
1144	.O5 (flag_enable_value),
1145	.O6 (register_enable_value)) ;
1146
1147	(* HBLKNM = "kcpsm6_strobes" *)
1148	FDR flag_enable_flop (
1149	.D (flag_enable_value),
1150	.Q (flag_enable),
1151	.R (active_interrupt),
1152	.C (clk)) ;
1153
1154	(* HBLKNM = "kcpsm6_strobes" *)
1155	FDR register_enable_flop (
1156	.D (register_enable_value),
1157	.Q (register_enable),
1158	.R (active_interrupt),
1159	.C (clk)) ;
1160
1161	(* HBLKNM = "kcpsm6_strobes" *)
1162	LUT6_2 # (
1163	.INIT (64'h8000000020000000))
1164	spm_enable_lut(
1165	.I0 (instruction[13]),
1166	.I1 (instruction[14]),
1167	.I2 (instruction[17]),
1168	.I3 (strobe_type),
1169	.I4 (t_state[1]),
1170	.I5 (1'b1),
1171	.O5 (k_write_strobe_value),
1172	.O6 (spm_enable_value)) ;
1173
1174	(* HBLKNM = "kcpsm6_strobes" *)
1175	FDR k_write_strobe_flop (
1176	.D (k_write_strobe_value),
1177	.Q (k_write_strobe),
1178	.R (active_interrupt),
1179	.C (clk)) ;
1180
1181	(* HBLKNM = "kcpsm6_strobes" *)
1182	FDR spm_enable_flop (
1183	.D (spm_enable_value),
1184	.Q (spm_enable),
1185	.R (active_interrupt),
1186	.C (clk)) ;
1187
1188	(* HBLKNM = "kcpsm6_strobes" *)
1189	LUT6_2 # (
1190	.INIT (64'h4000000001000000))
1191	read_strobe_lut(
1192	.I0 (instruction[13]),
1193	.I1 (instruction[14]),
1194	.I2 (instruction[17]),
1195	.I3 (strobe_type),
1196	.I4 (t_state[1]),
1197	.I5 (1'b1),
1198	.O5 (read_strobe_value),
1199	.O6 (write_strobe_value)) ;
1200
1201	(* HBLKNM = "kcpsm6_strobes" *)
1202	FDR write_strobe_flop (
1203	.D (write_strobe_value),
1204	.Q (write_strobe),
1205	.R (active_interrupt),
1206	.C (clk)) ;
1207
1208	(* HBLKNM = "kcpsm6_strobes" *)
1209	FDR read_strobe_flop (
1210	.D (read_strobe_value),
1211	.Q (read_strobe),
1212	.R (active_interrupt),
1213	.C (clk)) ;
1214	//
1215	///////////////////////////////////////////////////////////////////////////////////////////
1216	//
1217	// Register bank control
1218	//
1219	//
1220	// 2 x LUT6
1221	// 1 x FDR
1222	// 1 x FD
1223	//
1224	///////////////////////////////////////////////////////////////////////////////////////////
1225	//
1226	(* HBLKNM = "kcpsm6_stack1" *)
1227	LUT6 # (
1228	.INIT (64'h0080020000000000))
1229	regbank_type_lut(
1230	.I0 (instruction[12]),
1231	.I1 (instruction[13]),
1232	.I2 (instruction[14]),
1233	.I3 (instruction[15]),
1234	.I4 (instruction[16]),
1235	.I5 (instruction[17]),
1236	.O (regbank_type)) ;
1237
1238	(* HBLKNM = "kcpsm6_stack1" *)
1239	LUT6 # (
1240	.INIT (64'hACACFF00FF00FF00))
1241	bank_lut(
1242	.I0 (instruction[0]),
1243	.I1 (shadow_bank),
1244	.I2 (instruction[16]),
1245	.I3 (bank),
1246	.I4 (regbank_type),
1247	.I5 (t_state[1]),
1248	.O (bank_value)) ;
1249
1250	(* HBLKNM = "kcpsm6_stack1" *)
1251	FDR bank_flop (
1252	.D (bank_value),
1253	.Q (bank),
1254	.R (internal_reset),
1255	.C (clk)) ;
1256
1257	(* HBLKNM = "kcpsm6_control" *)
1258	FD sx_addr4_flop (
1259	.D (sx_addr4_value),
1260	.Q (sx_addr[4]),
1261	.C (clk)) ;
1262
1263	assign sx_addr[3:0] = instruction[11:8] ;
1264	assign sy_addr = {bank, instruction[7:4]} ;
1265
1266	//
1267	///////////////////////////////////////////////////////////////////////////////////////////
1268	//
1269	// Flags
1270	//
1271	//
1272	// 3 x LUT6
1273	// 5 x LUT6_2
1274	// 3 x FD
1275	// 2 x FDRE
1276	// 2 x XORCY
1277	// 5 x MUXCY
1278	//
1279	///////////////////////////////////////////////////////////////////////////////////////////
1280	//
1281
1282	(* HBLKNM = "kcpsm6_control" *)
1283	XORCY arith_carry_xorcy (
1284	.LI (1'b0),
1285	.CI (carry_arith_logical[7]),
1286	.O (arith_carry_value)) ;
1287
1288	(* HBLKNM = "kcpsm6_control" *)
1289	FD arith_carry_flop (
1290	.D (arith_carry_value),
1291	.Q (arith_carry),
1292	.C (clk)) ;
1293
1294	(* HBLKNM = "kcpsm6_decode2" *)
1295	LUT6_2 # (
1296	.INIT (64'h0000000087780000))
1297	lower_parity_lut(
1298	.I0 (instruction[13]),
1299	.I1 (carry_flag),
1300	.I2 (arith_logical_result[0]),
1301	.I3 (arith_logical_result[1]),
1302	.I4 (1'b1),
1303	.I5 (1'b1),
1304	.O5 (lower_parity),
1305	.O6 (lower_parity_sel)) ;
1306
1307	(* HBLKNM = "kcpsm6_decode2" *)
1308	MUXCY parity_muxcy (
1309	.DI (lower_parity),
1310	.CI (1'b0),
1311	.S (lower_parity_sel),
1312	.O (carry_lower_parity)) ;
1313
1314	(* HBLKNM = "kcpsm6_decode2" *)
1315	LUT6 #(
1316	.INIT (64'h6996966996696996))
1317	upper_parity_lut(
1318	.I0 (arith_logical_result[2]),
1319	.I1 (arith_logical_result[3]),
1320	.I2 (arith_logical_result[4]),
1321	.I3 (arith_logical_result[5]),
1322	.I4 (arith_logical_result[6]),
1323	.I5 (arith_logical_result[7]),
1324	.O (upper_parity)) ;
1325
1326	(* HBLKNM = "kcpsm6_decode2" *)
1327	XORCY parity_xorcy(
1328	.LI (upper_parity),
1329	.CI (carry_lower_parity),
1330	.O (parity)) ;
1331
1332	(* HBLKNM = "kcpsm6_decode1" *)
1333	LUT6 #(
1334	.INIT (64'hFFFFAACCF0F0F0F0))
1335	shift_carry_lut(
1336	.I0 (sx[0]),
1337	.I1 (sx[7]),
1338	.I2 (shadow_carry_flag),
1339	.I3 (instruction[3]),
1340	.I4 (instruction[7]),
1341	.I5 (instruction[16]),
1342	.O (shift_carry_value)) ;
1343
1344	(* HBLKNM = "kcpsm6_decode1" *)
1345	FD shift_carry_flop(
1346	.D (shift_carry_value),
1347	.Q (shift_carry),
1348	.C (clk)) ;
1349
1350	(* HBLKNM = "kcpsm6_flags" *)
1351	LUT6_2 #(
1352	.INIT (64'h3333AACCF0AA0000))
1353	carry_flag_lut(
1354	.I0 (shift_carry),
1355	.I1 (arith_carry),
1356	.I2 (parity),
1357	.I3 (instruction[14]),
1358	.I4 (instruction[15]),
1359	.I5 (instruction[16]),
1360	.O5 (drive_carry_in_zero),
1361	.O6 (carry_flag_value)) ;
1362
1363	(* HBLKNM = "kcpsm6_flags" *)
1364	FDRE carry_flag_flop(
1365	.D (carry_flag_value),
1366	.Q (carry_flag),
1367	.CE (flag_enable),
1368	.R (internal_reset),
1369	.C (clk)) ;
1370
1371	(* HBLKNM = "kcpsm6_flags" *)
1372	MUXCY init_zero_muxcy(
1373	.DI (drive_carry_in_zero),
1374	.CI (1'b0),
1375	.S (carry_flag_value),
1376	.O (carry_in_zero)) ;
1377
1378	(* HBLKNM = "kcpsm6_decode1" *)
1379	LUT6_2 # (
1380	.INIT (64'hA280000000F000F0))
1381	use_zero_flag_lut(
1382	.I0 (instruction[13]),
1383	.I1 (instruction[14]),
1384	.I2 (instruction[15]),
1385	.I3 (instruction[16]),
1386	.I4 (1'b1),
1387	.I5 (1'b1),
1388	.O5 (strobe_type),
1389	.O6 (use_zero_flag_value)) ;
1390
1391	(* HBLKNM = "kcpsm6_decode1" *)
1392	FD use_zero_flag_flop(
1393	.D (use_zero_flag_value),
1394	.Q (use_zero_flag),
1395	.C (clk)) ;
1396
1397	(* HBLKNM = "kcpsm6_flags" *)
1398	LUT6_2 #(
1399	.INIT (64'h0000000000000001))
1400	lower_zero_lut(
1401	.I0 (alu_result[0]),
1402	.I1 (alu_result[1]),
1403	.I2 (alu_result[2]),
1404	.I3 (alu_result[3]),
1405	.I4 (alu_result[4]),
1406	.I5 (1'b1),
1407	.O5 (lower_zero),
1408	.O6 (lower_zero_sel)) ;
1409
1410	(* HBLKNM = "kcpsm6_flags" *)
1411	MUXCY lower_zero_muxcy(
1412	.DI (lower_zero),
1413	.CI (carry_in_zero),
1414	.S (lower_zero_sel),
1415	.O (carry_lower_zero)) ;
1416
1417	(* HBLKNM = "kcpsm6_flags" *)
1418	LUT6_2 # (
1419	.INIT (64'h0000000D00000000))
1420	middle_zero_lut(
1421	.I0 (use_zero_flag),
1422	.I1 (zero_flag),
1423	.I2 (alu_result[5]),
1424	.I3 (alu_result[6]),
1425	.I4 (alu_result[7]),
1426	.I5 (1'b1),
1427	.O5 (middle_zero),
1428	.O6 (middle_zero_sel)) ;
1429
1430	(* HBLKNM = "kcpsm6_flags" *)
1431	MUXCY middle_zero_muxcy(
1432	.DI (middle_zero),
1433	.CI (carry_lower_zero),
1434	.S (middle_zero_sel),
1435	.O (carry_middle_zero)) ;
1436
1437	(* HBLKNM = "kcpsm6_flags" *)
1438	LUT6 #(
1439	.INIT (64'hFBFF000000000000))
1440	upper_zero_lut(
1441	.I0 (instruction[14]),
1442	.I1 (instruction[15]),
1443	.I2 (instruction[16]),
1444	.I3 (1'b1),
1445	.I4 (1'b1),
1446	.I5 (1'b1),
1447	.O (upper_zero_sel)) ;
1448
1449	(* HBLKNM = "kcpsm6_flags" *)
1450	MUXCY upper_zero_muxcy(
1451	.DI (shadow_zero_flag),
1452	.CI (carry_middle_zero),
1453	.S (upper_zero_sel),
1454	.O (zero_flag_value)) ;
1455
1456	(* HBLKNM = "kcpsm6_flags" *)
1457	FDRE zero_flag_flop(
1458	.D (zero_flag_value),
1459	.Q (zero_flag),
1460	.CE (flag_enable),
1461	.R (internal_reset),
1462	.C (clk)) ;
1463
1464	//
1465	///////////////////////////////////////////////////////////////////////////////////////////
1466	//
1467	// 12-bit Program Address Generation
1468	//
1469	///////////////////////////////////////////////////////////////////////////////////////////
1470	//
1471
1472	//
1473	// Prepare 12-bit vector from the sX and sY register outputs.
1474	//
1475
1476	assign register_vector = {sx[3:0], sy} ;
1477
1478	genvar i ;
1479
1480	generate
1481	for (i = 0 ; i <= 11 ; i = i+1)
1482	begin : address_loop
1483	parameter [7:0] id4 = 8'h30 + i/4 ;
1484	parameter [7:0] id8 = 8'h30 + i/8 ;
1485	parameter [7:0] ip4d8 = 8'h30 + (i+4)/8 ;
1486	//
1487	///////////////////////////////////////////////////////////////////////////////////////////
1488	//
1489	// Selection of vector to load program counter
1490	//
1491	// instruction[12]
1492	// 0 Constant aaa from instruction(11:0)
1493	// 1 Return vector from stack
1494	//
1495	// 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
1496	// Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
1497	//
1498	// 6 x LUT6_2
1499	// 12 x FD
1500	//
1501	///////////////////////////////////////////////////////////////////////////////////////////
1502	//
1503
1504	//
1505	// Pipeline output of the stack memory
1506	//
1507	(* HBLKNM = {"kcpsm6_stack_ram",ip4d8} *)
1508	FD return_vector_flop(
1509	.D (stack_memory[i]),
1510	.Q (return_vector[i]),
1511	.C (clk));
1512	//
1513	// Multiplex instruction constant address and output from stack.
1514	// 2 bits per LUT so only generate when 'i' is even.
1515	//
1516	if (i % 2 == 0) begin: output_data
1517
1518	(* HBLKNM = {"kcpsm6_vector",id8} *)
1519	LUT6_2 #(
1520	.INIT (64'hFF00F0F0CCCCAAAA))
1521	pc_vector_mux_lut(
1522	.I0 (instruction[i]),
1523	.I1 (return_vector[i]),
1524	.I2 (instruction[i+1]),
1525	.I3 (return_vector[i+1]),
1526	.I4 (instruction[12]),
1527	.I5 (1'b1),
1528	.O5 (pc_vector[i]),
1529	.O6 (pc_vector[i+1]));
1530
1531	end //output_data
1532
1533	//
1534	///////////////////////////////////////////////////////////////////////////////////////////
1535	//
1536	// Program Counter
1537	//
1538	// Reset by internal_reset has highest priority.
1539	// Enabled by t_state[1] has second priority.
1540	//
1541	// The function performed is defined by pc_mode(2:0).
1542	//
1543	// pc_mode [2] [1] [0]
1544	// 0 0 1 pc+1 for normal program flow.
1545	// 1 0 0 Forces interrupt vector value (+0) during active interrupt.
1546	// The vector is defined by a generic with default value FF0 hex.
1547	// 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
1548	// 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
1549	// 0 1 1 pc_vector+1 for 'RETURN'.
1550	//
1551	// Note that pc_mode[0] is High during operations that require an increment to occur.
1552	// The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
1553	// pc_mode[0] also has to be connected to the start of the carry chain.
1554	//
1555	// 3 Slices
1556	// 12 x LUT6
1557	// 11 x MUXCY
1558	// 12 x XORCY
1559	// 12 x FDRE
1560	//
1561	///////////////////////////////////////////////////////////////////////////////////////////
1562	//
1563	(* HBLKNM = {"kcpsm6_pc",id4} *)
1564	FDRE pc_flop(
1565	.D (pc_value[i]),
1566	.Q (pc[i]),
1567	.R (internal_reset),
1568	.CE (t_state[1]),
1569	.C (clk));
1570
1571	if (i == 0) begin: lsb_pc
1572
1573	//
1574	// Logic of LSB must invert selected value when pc_mode[0] is High.
1575	// The interrupt vector is defined by a generic.
1576	//
1577
1578	if (interrupt_vector[i] == 1'b0) begin: low_int_vector
1579
1580	(* HBLKNM = {"kcpsm6_pc",id4} *)
1581	LUT6 #(
1582	.INIT (64'h00AA000033CC0F00))
1583	pc_lut(
1584	.I0 (register_vector[i]),
1585	.I1 (pc_vector[i]),
1586	.I2 (pc[i]),
1587	.I3 (pc_mode[0]),
1588	.I4 (pc_mode[1]),
1589	.I5 (pc_mode[2]),
1590	.O (half_pc[i]));
1591
1592	end //low_int_vector
1593
1594	if (interrupt_vector[i] == 1'b1) begin: high_int_vector
1595
1596	(* HBLKNM = {"kcpsm6_pc",id4} *)
1597	LUT6 #(
1598	.INIT (64'h00AA00FF33CC0F00))
1599	pc_lut(
1600	.I0 (register_vector[i]),
1601	.I1 (pc_vector[i]),
1602	.I2 (pc[i]),
1603	.I3 (pc_mode[0]),
1604	.I4 (pc_mode[1]),
1605	.I5 (pc_mode[2]),
1606	.O (half_pc[i]));
1607
1608	end //high_int_vector
1609
1610	//
1611	// pc_mode[0] connected to first MUXCY and carry input is 1'b0
1612	//
1613
1614	(* HBLKNM = {"kcpsm6_pc",id4} *)
1615	XORCY pc_xorcy(
1616	.LI (half_pc[i]),
1617	.CI (1'b0),
1618	.O (pc_value[i]));
1619
1620	(* HBLKNM = {"kcpsm6_pc",id4} *)
1621	MUXCY pc_muxcy(
1622	.DI (pc_mode[0]),
1623	.CI (1'b0),
1624	.S (half_pc[i]),
1625	.O (carry_pc[i]));
1626
1627	end //lsb_pc
1628
1629	if (i > 0) begin : upper_pc
1630
1631	//
1632	// Logic of upper section selects required value.
1633	// The interrupt vector is defined by a generic.
1634	//
1635
1636	if (interrupt_vector[i] == 1'b0) begin: low_int_vector
1637
1638	(* HBLKNM = {"kcpsm6_pc",id4} *)
1639	LUT6 #(
1640	.INIT (64'h00AA0000CCCCF000))
1641	pc_lut(
1642	.I0 (register_vector[i]),
1643	.I1 (pc_vector[i]),
1644	.I2 (pc[i]),
1645	.I3 (pc_mode[0]),
1646	.I4 (pc_mode[1]),
1647	.I5 (pc_mode[2]),
1648	.O (half_pc[i]));
1649
1650	end //low_int_vector
1651
1652	if (interrupt_vector[i] == 1'b1) begin: high_int_vector
1653
1654	(* HBLKNM = {"kcpsm6_pc",id4} *)
1655	LUT6 #(
1656	.INIT (64'h00AA00FFCCCCF000))
1657	pc_lut(
1658	.I0 (register_vector[i]),
1659	.I1 (pc_vector[i]),
1660	.I2 (pc[i]),
1661	.I3 (pc_mode[0]),
1662	.I4 (pc_mode[1]),
1663	.I5 (pc_mode[2]),
1664	.O (half_pc[i]));
1665
1666	end //high_int_vector
1667
1668	//
1669	// Carry chain implementing remainder of increment function
1670	//
1671	(* HBLKNM = {"kcpsm6_pc",id4} *)
1672	XORCY pc_xorcy(
1673	.LI (half_pc[i]),
1674	.CI (carry_pc[i-1]),
1675	.O (pc_value[i]));
1676
1677
1678	//
1679	// No MUXCY required at the top of the chain
1680	//
1681	if (i < 11) begin: mid_pc
1682
1683	(* HBLKNM = {"kcpsm6_pc",id4} *)
1684	MUXCY pc_muxcy(
1685	.DI (1'b0),
1686	.CI (carry_pc[i-1]),
1687	.S (half_pc[i]),
1688	.O (carry_pc[i]));
1689
1690	end //mid_pc
1691
1692	end //upper_pc
1693
1694
1695	//
1696	///////////////////////////////////////////////////////////////////////////////////////////
1697	//
1698	end //address_loop
1699	endgenerate
1700	//
1701	///////////////////////////////////////////////////////////////////////////////////////////
1702	//
1703	// Stack
1704	// Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
1705	// Also preserves flags and bank selection during interrupt.
1706	//
1707	// 2 x RAM32M
1708	// 4 x FD
1709	// 5 x FDR
1710	// 1 x LUT6
1711	// 4 x LUT6_2
1712	// 5 x XORCY
1713	// 5 x MUXCY
1714	//
1715	///////////////////////////////////////////////////////////////////////////////////////////
1716	//
1717
1718	(* HBLKNM = "kcpsm6_stack_ram0" *)
1719	FD shadow_carry_flag_flop(
1720	.D (stack_carry_flag),
1721	.Q (shadow_carry_flag),
1722	.C (clk)) ;
1723
1724	(* HBLKNM = "kcpsm6_stack_ram0" *)
1725	FD stack_zero_flop(
1726	.D (stack_zero_flag),
1727	.Q (shadow_zero_value),
1728	.C (clk)) ;
1729
1730	(* HBLKNM = "kcpsm6_decode1" *)
1731	FD shadow_zero_flag_flop(
1732	.D (shadow_zero_value),
1733	.Q (shadow_zero_flag),
1734	.C (clk)) ;
1735
1736	(* HBLKNM = "kcpsm6_stack_ram0" *)
1737	FD shadow_bank_flop(
1738	.D (stack_bank),
1739	.Q (shadow_bank),
1740	.C (clk)) ;
1741
1742	(* HBLKNM = "kcpsm6_stack_ram0" *)
1743	FD stack_bit_flop(
1744	.D (stack_bit),
1745	.Q (special_bit),
1746	.C (clk)) ;
1747
1748	(* HBLKNM = "kcpsm6_stack_ram0" *)
1749	RAM32M #(
1750	.INIT_A (64'h0000000000000000),
1751	.INIT_B (64'h0000000000000000),
1752	.INIT_C (64'h0000000000000000),
1753	.INIT_D (64'h0000000000000000))
1754	stack_ram_low (
1755	.DOA ({stack_zero_flag, stack_carry_flag}),
1756	.DOB ({stack_bit, stack_bank}),
1757	.DOC (stack_memory[1:0]),
1758	.DOD (stack_memory[3:2]),
1759	.ADDRA (stack_pointer[4:0]),
1760	.ADDRB (stack_pointer[4:0]),
1761	.ADDRC (stack_pointer[4:0]),
1762	.ADDRD (stack_pointer[4:0]),
1763	.DIA ({zero_flag, carry_flag}),
1764	.DIB ({run, bank}),
1765	.DIC (pc[1:0]),
1766	.DID (pc[3:2]),
1767	.WE (t_state[1]),
1768	.WCLK (clk));
1769
1770	(* HBLKNM = "kcpsm6_stack_ram1" *)
1771	RAM32M #(
1772	.INIT_A (64'h0000000000000000),
1773	.INIT_B (64'h0000000000000000),
1774	.INIT_C (64'h0000000000000000),
1775	.INIT_D (64'h0000000000000000))
1776	stack_ram_high(
1777	.DOA (stack_memory[5:4]),
1778	.DOB (stack_memory[7:6]),
1779	.DOC (stack_memory[9:8]),
1780	.DOD (stack_memory[11:10]),
1781	.ADDRA (stack_pointer[4:0]),
1782	.ADDRB (stack_pointer[4:0]),
1783	.ADDRC (stack_pointer[4:0]),
1784	.ADDRD (stack_pointer[4:0]),
1785	.DIA (pc[5:4]),
1786	.DIB (pc[7:6]),
1787	.DIC (pc[9:8]),
1788	.DID (pc[11:10]),
1789	.WE (t_state[1]),
1790	.WCLK (clk));
1791
1792	generate
1793	for (i = 0 ; i <= 4 ; i = i+1)
1794	begin : stack_loop
1795
1796	parameter [7:0] id4 = 8'h30 + i/4 ;
1797
1798	if (i == 0) begin: lsb_stack
1799
1800	(* HBLKNM = {"kcpsm6_stack",id4} *)
1801	FDR pointer_flop(
1802	.D (stack_pointer_value[i]),
1803	.Q (stack_pointer[i]),
1804	.R (internal_reset),
1805	.C (clk)) ;
1806
1807	(* HBLKNM = {"kcpsm6_stack",id4} *)
1808	LUT6_2 #(
1809	.INIT (64'h001529AAAAAAAAAA))
1810	stack_pointer_lut(
1811	.I0 (stack_pointer[i]),
1812	.I1 (pop_stack),
1813	.I2 (push_stack),
1814	.I3 (t_state[1]),
1815	.I4 (t_state[2]),
1816	.I5 (1'b1),
1817	.O5 (feed_pointer_value[i]),
1818	.O6 (half_pointer_value[i]));
1819
1820	(* HBLKNM = {"kcpsm6_stack",id4} *)
1821	XORCY stack_xorcy(
1822	.LI (half_pointer_value[i]),
1823	.CI (1'b0),
1824	.O (stack_pointer_value[i]));
1825
1826	(* HBLKNM = {"kcpsm6_stack",id4} *)
1827	MUXCY stack_muxcy(
1828	.DI (feed_pointer_value[i]),
1829	.CI (1'b0),
1830	.S (half_pointer_value[i]),
1831	.O (stack_pointer_carry[i]));
1832
1833	end //lsb_stack
1834
1835	if (i > 0) begin: upper_stack
1836
1837	(* HBLKNM = {"kcpsm6_stack",id4} *)
1838	FDR pointer_flop(
1839	.D (stack_pointer_value[i]),
1840	.Q (stack_pointer[i]),
1841	.R (internal_reset),
1842	.C (clk)) ;
1843
1844	(* HBLKNM = {"kcpsm6_stack",id4} *)
1845	LUT6_2 #(
1846	.INIT (64'h002A252AAAAAAAAA))
1847	stack_pointer_lut(
1848	.I0 (stack_pointer[i]),
1849	.I1 (pop_stack),
1850	.I2 (push_stack),
1851	.I3 (t_state[1]),
1852	.I4 (t_state[2]),
1853	.I5 (1'b1),
1854	.O5 (feed_pointer_value[i]),
1855	.O6 (half_pointer_value[i]));
1856
1857	(* HBLKNM = {"kcpsm6_stack",id4} *)
1858	XORCY stack_xorcy(
1859	.LI (half_pointer_value[i]),
1860	.CI (stack_pointer_carry[i-1]),
1861	.O (stack_pointer_value[i]));
1862
1863	(* HBLKNM = {"kcpsm6_stack",id4} *)
1864	MUXCY stack_muxcy(
1865	.DI (feed_pointer_value[i]),
1866	.CI (stack_pointer_carry[i-1]),
1867	.S (half_pointer_value[i]),
1868	.O (stack_pointer_carry[i]));
1869
1870	end //upper_stack
1871
1872	end //stack_loop
1873	endgenerate
1874
1875	//
1876	///////////////////////////////////////////////////////////////////////////////////////////
1877	//
1878	// 8-bit Data Path
1879	//
1880	///////////////////////////////////////////////////////////////////////////////////////////
1881	//
1882	generate
1883	for (i = 0 ; i <= 7 ; i = i+1)
1884	begin : data_path_loop
1885	parameter [7:0] id1 = 8'h30 + i ;
1886	parameter [7:0] id2 = 8'h30 + i/2 ;
1887	parameter [7:0] id4 = 8'h30 + i/4 ;
1888	//
1889	///////////////////////////////////////////////////////////////////////////////////////////
1890	//
1891	// Selection of second operand to ALU and port_id
1892	//
1893	// instruction[12]
1894	// 0 Register sY
1895	// 1 Constant kk
1896	//
1897	// 4 x LUT6_2
1898	//
1899	///////////////////////////////////////////////////////////////////////////////////////////
1900	//
1901	//
1902	// 2 bits per LUT so only generate when 'i' is even
1903	//
1904	if (i % 2 == 0) begin: output_data
1905
1906	(* HBLKNM = "kcpsm6_port_id" *)
1907	LUT6_2 #(
1908	.INIT (64'hFF00F0F0CCCCAAAA))
1909	sy_kk_mux_lut(
1910	.I0 (sy[i]),
1911	.I1 (instruction[i]),
1912	.I2 (sy[i+1]),
1913	.I3 (instruction[i+1]),
1914	.I4 (instruction[12]),
1915	.I5 (1'b1),
1916	.O5 (sy_or_kk[i]),
1917	.O6 (sy_or_kk[i+1]));
1918
1919	end //output_data
1920
1921	//
1922	///////////////////////////////////////////////////////////////////////////////////////////
1923	//
1924	// Selection of out_port value
1925	//
1926	// instruction[13]
1927	// 0 Register sX
1928	// 1 Constant kk from instruction(11:4)
1929	//
1930	// 4 x LUT6_2
1931	//
1932	///////////////////////////////////////////////////////////////////////////////////////////
1933	//
1934	//
1935	// 2 bits per LUT so only generate when 'i' is even
1936	//
1937
1938	if (i % 2 == 0) begin: second_operand
1939
1940	(* HBLKNM = "kcpsm6_out_port" *)
1941	LUT6_2 #(
1942	.INIT (64'hFF00F0F0CCCCAAAA))
1943	out_port_lut(
1944	.I0 (sx[i]),
1945	.I1 (instruction[i+4]),
1946	.I2 (sx[i+1]),
1947	.I3 (instruction[i+5]),
1948	.I4 (instruction[13]),
1949	.I5 (1'b1),
1950	.O5 (out_port[i]),
1951	.O6 (out_port[i+1]));
1952
1953	end //second_operand;
1954
1955	//
1956	///////////////////////////////////////////////////////////////////////////////////////////
1957	//
1958	// Arithmetic and Logical operations
1959	//
1960	// Definition of....
1961	// ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
1962	// LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
1963	//
1964	// arith_logical_sel [2] [1] [0]
1965	// 0 0 0 - LOAD
1966	// 0 0 1 - AND
1967	// 0 1 0 - OR
1968	// 0 1 1 - XOR
1969	// 1 X 0 - SUB
1970	// 1 X 1 - ADD
1971	//
1972	// Includes pipeline stage.
1973	//
1974	// 2 Slices
1975	// 8 x LUT6_2
1976	// 8 x MUXCY
1977	// 8 x XORCY
1978	// 8 x FD
1979	//
1980	///////////////////////////////////////////////////////////////////////////////////////////
1981	//
1982
1983	(* HBLKNM = {"kcpsm6_add",id4} *)
1984	LUT6_2 #(
1985	.INIT (64'h69696E8ACCCC0000))
1986	arith_logical_lut(
1987	.I0 (sy_or_kk[i]),
1988	.I1 (sx[i]),
1989	.I2 (arith_logical_sel[0]),
1990	.I3 (arith_logical_sel[1]),
1991	.I4 (arith_logical_sel[2]),
1992	.I5 (1'b1),
1993	.O5 (logical_carry_mask[i]),
1994	.O6 (half_arith_logical[i]));
1995
1996	(* HBLKNM = {"kcpsm6_add",id4} *)
1997	FD arith_logical_flop(
1998	.D (arith_logical_value[i]),
1999	.Q (arith_logical_result[i]),
2000	.C (clk)) ;
2001
2002	if (i == 0) begin: lsb_arith_logical
2003	//
2004	// Carry input to first MUXCY and XORCY
2005	//
2006	(* HBLKNM = {"kcpsm6_add",id4} *)
2007	MUXCY arith_logical_muxcy(
2008	.DI (logical_carry_mask[i]),
2009	.CI (arith_carry_in),
2010	.S (half_arith_logical[i]),
2011	.O (carry_arith_logical[i]));
2012
2013	(* HBLKNM = {"kcpsm6_add",id4} *)
2014	XORCY arith_logical_xorcy(
2015	.LI (half_arith_logical[i]),
2016	.CI (arith_carry_in),
2017	.O (arith_logical_value[i]));
2018
2019	end //lsb_arith_logical
2020
2021	if (i > 0) begin: upper_arith_logical
2022	//
2023	// Main carry chain
2024	//
2025	(* HBLKNM = {"kcpsm6_add",id4} *)
2026	MUXCY arith_logical_muxcy(
2027	.DI (logical_carry_mask[i]),
2028	.CI (carry_arith_logical[i-1]),
2029	.S (half_arith_logical[i]),
2030	.O (carry_arith_logical[i]));
2031
2032	(* HBLKNM = {"kcpsm6_add",id4} *)
2033	XORCY arith_logical_xorcy(
2034	.LI (half_arith_logical[i]),
2035	.CI (carry_arith_logical[i-1]),
2036	.O (arith_logical_value[i]));
2037
2038	end //upper_arith_logical;
2039
2040
2041	//
2042	///////////////////////////////////////////////////////////////////////////////////////////
2043	//
2044	// Shift and Rotate operations
2045	//
2046	// Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
2047	//
2048	// instruction [3] [2] [1] [0]
2049	// 0 1 1 0 - SL0
2050	// 0 1 1 1 - SL1
2051	// 0 1 0 0 - SLX
2052	// 0 0 0 0 - SLA
2053	// 0 0 1 0 - RL
2054	// 1 1 1 0 - SR0
2055	// 1 1 1 1 - SR1
2056	// 1 0 1 0 - SRX
2057	// 1 0 0 0 - SRA
2058	// 1 1 0 0 - RR
2059	//
2060	// instruction[3]
2061	// 0 - Left
2062	// 1 - Right
2063	//
2064	// instruction [2] [1] Bit shifted in
2065	// 0 0 Carry_flag
2066	// 0 1 sX[7]
2067	// 1 0 sX[0]
2068	// 1 1 instruction[0]
2069	//
2070	// Includes pipeline stage.
2071	//
2072	// 4 x LUT6_2
2073	// 1 x LUT6
2074	// 8 x FD
2075	//
2076	///////////////////////////////////////////////////////////////////////////////////////////
2077	//
2078
2079	if (hwbuild[i] == 1'b0) begin: low_hwbuild
2080	//
2081	// Reset Flip-flop to form 1'b0 for this bit of HWBUILD
2082	//
2083	(* HBLKNM = "kcpsm6_sandr" *)
2084	FDR shift_rotate_flop(
2085	.D (shift_rotate_value[i]),
2086	.Q (shift_rotate_result[i]),
2087	.R (instruction[7]),
2088	.C (clk)) ;
2089
2090	end // low_hwbuild;
2091
2092	if (hwbuild[i] == 1'b1) begin: high_hwbuild
2093	//
2094	// Set Flip-flop to form 1'b1 for this bit of HWBUILD
2095	//
2096	(* HBLKNM = "kcpsm6_sandr" *)
2097	FDS shift_rotate_flop(
2098	.D (shift_rotate_value[i]),
2099	.Q (shift_rotate_result[i]),
2100	.S (instruction[7]),
2101	.C (clk)) ;
2102
2103	end // high_hwbuild;
2104
2105	if (i == 0) begin: lsb_shift_rotate
2106	//
2107	// Select bit to be shifted or rotated into result
2108	//
2109	(* HBLKNM = "kcpsm6_decode1" *)
2110	LUT6 #(
2111	.INIT (64'hBFBC8F8CB3B08380))
2112	shift_bit_lut(
2113	.I0 (instruction[0]),
2114	.I1 (instruction[1]),
2115	.I2 (instruction[2]),
2116	.I3 (carry_flag),
2117	.I4 (sx[0]),
2118	.I5 (sx[7]),
2119	.O (shift_in_bit));
2120
2121	//
2122	// Define lower bits of result
2123	//
2124	(* HBLKNM = "kcpsm6_sandr" *)
2125	LUT6_2 #(
2126	.INIT (64'hFF00F0F0CCCCAAAA))
2127	shift_rotate_lut(
2128	.I0 (shift_in_bit),
2129	.I1 (sx[i+1]),
2130	.I2 (sx[i]),
2131	.I3 (sx[i+2]),
2132	.I4 (instruction[3]),
2133	.I5 (1'b1),
2134	.O5 (shift_rotate_value[i]),
2135	.O6 (shift_rotate_value[i+1]));
2136
2137	end // lsb_shift_rotate;
2138
2139	if (i == 2 \|\| i == 4) begin: mid_shift_rotate
2140	//
2141	// Define middle bits of result
2142	//
2143	(* HBLKNM = "kcpsm6_sandr" *)
2144	LUT6_2 #(
2145	.INIT (64'hFF00F0F0CCCCAAAA))
2146	shift_rotate_lut(
2147	.I0 (sx[i-1]),
2148	.I1 (sx[i+1]),
2149	.I2 (sx[i]),
2150	.I3 (sx[i+2]),
2151	.I4 (instruction[3]),
2152	.I5 (1'b1),
2153	.O5 (shift_rotate_value[i]),
2154	.O6 (shift_rotate_value[i+1]));
2155
2156	end // mid_shift_rotate;
2157
2158	if (i == 6) begin: msb_shift_rotate
2159	//
2160	// Define upper bits of result
2161	//
2162	(* HBLKNM = "kcpsm6_sandr" *)
2163	LUT6_2 #(
2164	.INIT (64'hFF00F0F0CCCCAAAA))
2165	shift_rotate_lut(
2166	.I0 (sx[i-1]),
2167	.I1 (sx[i+1]),
2168	.I2 (sx[i]),
2169	.I3 (shift_in_bit),
2170	.I4 (instruction[3]),
2171	.I5 (1'b1),
2172	.O5 (shift_rotate_value[i]),
2173	.O6 (shift_rotate_value[i+1]));
2174
2175	end // msb_shift_rotate;
2176
2177	//
2178	///////////////////////////////////////////////////////////////////////////////////////////
2179	//
2180	// Multiplex outputs from ALU functions, scratch pad memory and input port.
2181	//
2182	// alu_mux_sel [1] [0]
2183	// 0 0 Arithmetic and Logical Instructions
2184	// 0 1 Shift and Rotate Instructions
2185	// 1 0 Input Port
2186	// 1 1 Scratch Pad Memory
2187	//
2188	// 8 x LUT6
2189	//
2190	///////////////////////////////////////////////////////////////////////////////////////////
2191	//
2192
2193	(* HBLKNM = {"kcpsm6_alu",id4} *)
2194	LUT6 #(
2195	.INIT (64'hFF00F0F0CCCCAAAA))
2196	alu_mux_lut(
2197	.I0 (arith_logical_result[i]),
2198	.I1 (shift_rotate_result[i]),
2199	.I2 (in_port[i]),
2200	.I3 (spm_data[i]),
2201	.I4 (alu_mux_sel[0]),
2202	.I5 (alu_mux_sel[1]),
2203	.O (alu_result[i]));
2204
2205	//
2206	///////////////////////////////////////////////////////////////////////////////////////////
2207	//
2208	// Scratchpad Memory with output register.
2209	//
2210	// The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
2211	// The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
2212	// bytes at an additional cost of 2 and 6 Slices.
2213	//
2214	//
2215	// 8 x RAM256X1S (256 bytes).
2216	// 8 x RAM128X1S (128 bytes).
2217	// 2 x RAM64M (64 bytes).
2218	//
2219	// 8 x FD.
2220	//
2221	///////////////////////////////////////////////////////////////////////////////////////////
2222	//
2223
2224	if (scratch_pad_memory_size == 64) begin : small_spm
2225
2226	(* HBLKNM = {"kcpsm6_spm",id4} *)
2227	FD spm_flop(
2228	.D (spm_ram_data[i]),
2229	.Q (spm_data[i]),
2230	.C (clk)) ;
2231
2232	if (i == 0 \|\| i == 4) begin: small_spm_ram
2233
2234	RAM64M #(
2235	.INIT_A (64'h0000000000000000),
2236	.INIT_B (64'h0000000000000000),
2237	.INIT_C (64'h0000000000000000),
2238	.INIT_D (64'h0000000000000000))
2239	spm_ram(
2240	.DOA (spm_ram_data[i]),
2241	.DOB (spm_ram_data[i+1]),
2242	.DOC (spm_ram_data[i+2]),
2243	.DOD (spm_ram_data[i+3]),
2244	.ADDRA (sy_or_kk[5:0]),
2245	.ADDRB (sy_or_kk[5:0]),
2246	.ADDRC (sy_or_kk[5:0]),
2247	.ADDRD (sy_or_kk[5:0]),
2248	.DIA (sx[i]),
2249	.DIB (sx[i+1]),
2250	.DIC (sx[i+2]),
2251	.DID (sx[i+3]),
2252	.WE (spm_enable),
2253	.WCLK (clk));
2254
2255	end // small_spm_ram;
2256
2257	end // small_spm;
2258
2259	if (scratch_pad_memory_size == 128) begin : medium_spm
2260
2261	(* HBLKNM = {"kcpsm6_spm",id2} *)
2262	RAM128X1S #(
2263	.INIT (128'h00000000000000000000000000000000))
2264	spm_ram(
2265	.D (sx[i]),
2266	.WE (spm_enable),
2267	.WCLK (clk),
2268	.A0 (sy_or_kk[0]),
2269	.A1 (sy_or_kk[1]),
2270	.A2 (sy_or_kk[2]),
2271	.A3 (sy_or_kk[3]),
2272	.A4 (sy_or_kk[4]),
2273	.A5 (sy_or_kk[5]),
2274	.A6 (sy_or_kk[6]),
2275	.O (spm_ram_data[i]));
2276
2277	(* HBLKNM = {"kcpsm6_spm",id2} *)
2278	FD spm_flop(
2279	.D (spm_ram_data[i]),
2280	.Q (spm_data[i]),
2281	.C (clk)) ;
2282
2283	end // medium_spm;
2284
2285	if (scratch_pad_memory_size == 256) begin : large_spm
2286
2287	(* HBLKNM = {"kcpsm6_spm",id1} *)
2288	RAM256X1S #(
2289	.INIT (256'h0000000000000000000000000000000000000000000000000000000000000000))
2290	spm_ram (
2291	.D (sx[i]),
2292	.WE (spm_enable),
2293	.WCLK (clk),
2294	.A (sy_or_kk),
2295	.O (spm_ram_data[i]));
2296
2297	(* HBLKNM = {"kcpsm6_spm",id1} *)
2298	FD spm_flop(
2299	.D (spm_ram_data[i]),
2300	.Q (spm_data[i]),
2301	.C (clk)) ;
2302
2303	end // large_spm;
2304
2305	//
2306	///////////////////////////////////////////////////////////////////////////////////////////
2307	//
2308
2309	end // data_path_loop;
2310	endgenerate
2311
2312
2313
2314	//
2315	///////////////////////////////////////////////////////////////////////////////////////////
2316	//
2317	// Two Banks of 16 General Purpose Registers.
2318	//
2319	// sx_addr - Address for sX is formed by bank select and instruction[11:8]
2320	// sy_addr - Address for sY is formed by bank select and instruction[7:4]
2321	//
2322	// 2 Slices
2323	// 2 x RAM32M
2324	//
2325	///////////////////////////////////////////////////////////////////////////////////////////
2326	//
2327
2328	(* HBLKNM = "kcpsm6_reg0" *)
2329	RAM32M #(
2330	.INIT_A (64'h0000000000000000),
2331	.INIT_B (64'h0000000000000000),
2332	.INIT_C (64'h0000000000000000),
2333	.INIT_D (64'h0000000000000000))
2334	lower_reg_banks(
2335	.DOA (sy[1:0]),
2336	.DOB (sx[1:0]),
2337	.DOC (sy[3:2]),
2338	.DOD (sx[3:2]),
2339	.ADDRA (sy_addr),
2340	.ADDRB (sx_addr),
2341	.ADDRC (sy_addr),
2342	.ADDRD (sx_addr),
2343	.DIA (alu_result[1:0]),
2344	.DIB (alu_result[1:0]),
2345	.DIC (alu_result[3:2]),
2346	.DID (alu_result[3:2]),
2347	.WE (register_enable),
2348	.WCLK (clk));
2349
2350	(* HBLKNM = "kcpsm6_reg1" *)
2351	RAM32M #(
2352	.INIT_A (64'h0000000000000000),
2353	.INIT_B (64'h0000000000000000),
2354	.INIT_C (64'h0000000000000000),
2355	.INIT_D (64'h0000000000000000))
2356	upper_reg_banks(
2357	.DOA (sy[5:4]),
2358	.DOB (sx[5:4]),
2359	.DOC (sy[7:6]),
2360	.DOD (sx[7:6]),
2361	.ADDRA (sy_addr),
2362	.ADDRB (sx_addr),
2363	.ADDRC (sy_addr),
2364	.ADDRD (sx_addr),
2365	.DIA (alu_result[5:4]),
2366	.DIB (alu_result[5:4]),
2367	.DIC (alu_result[7:6]),
2368	.DID (alu_result[7:6]),
2369	.WE (register_enable),
2370	.WCLK (clk));
2371
2372	//
2373	///////////////////////////////////////////////////////////////////////////////////////////
2374	//
2375	// Connections to KCPSM6 outputs.
2376	//
2377	///////////////////////////////////////////////////////////////////////////////////////////
2378	//
2379
2380
2381	assign address = pc;
2382	assign bram_enable = t_state[2];
2383
2384	//
2385	///////////////////////////////////////////////////////////////////////////////////////////
2386	//
2387	// Connections KCPSM6 Outputs.
2388	//
2389	///////////////////////////////////////////////////////////////////////////////////////////
2390	//
2391
2392	assign port_id = sy_or_kk;
2393
2394	//
2395	///////////////////////////////////////////////////////////////////////////////////////////
2396	//
2397	// End of description for kcpsm6 macro.
2398	//
2399	///////////////////////////////////////////////////////////////////////////////////////////
2400	//
2401	// *****************************************************
2402	// * Code for simulation purposes only after this line *
2403	// *****************************************************
2404	//
2405	//
2406	// Disassemble the instruction codes to form a text string for display.
2407	// Determine status of reset and flags and present in the form of a text string.
2408	// Provide signals to simulate the contents of each register and scratch pad memory
2409	// location.
2410	//
2411	///////////////////////////////////////////////////////////////////////////////////////////
2412	//
2413	//All of this section is ignored during synthesis.
2414	//synthesis translate_off
2415	//
2416	//
2417	// Variables for contents of each register in each bank
2418	//
2419	reg [7:0] bank_a_s0 ;
2420	reg [7:0] bank_a_s1 ;
2421	reg [7:0] bank_a_s2 ;
2422	reg [7:0] bank_a_s3 ;
2423	reg [7:0] bank_a_s4 ;
2424	reg [7:0] bank_a_s5 ;
2425	reg [7:0] bank_a_s6 ;
2426	reg [7:0] bank_a_s7 ;
2427	reg [7:0] bank_a_s8 ;
2428	reg [7:0] bank_a_s9 ;
2429	reg [7:0] bank_a_sa ;
2430	reg [7:0] bank_a_sb ;
2431	reg [7:0] bank_a_sc ;
2432	reg [7:0] bank_a_sd ;
2433	reg [7:0] bank_a_se ;
2434	reg [7:0] bank_a_sf ;
2435	reg [7:0] bank_b_s0 ;
2436	reg [7:0] bank_b_s1 ;
2437	reg [7:0] bank_b_s2 ;
2438	reg [7:0] bank_b_s3 ;
2439	reg [7:0] bank_b_s4 ;
2440	reg [7:0] bank_b_s5 ;
2441	reg [7:0] bank_b_s6 ;
2442	reg [7:0] bank_b_s7 ;
2443	reg [7:0] bank_b_s8 ;
2444	reg [7:0] bank_b_s9 ;
2445	reg [7:0] bank_b_sa ;
2446	reg [7:0] bank_b_sb ;
2447	reg [7:0] bank_b_sc ;
2448	reg [7:0] bank_b_sd ;
2449	reg [7:0] bank_b_se ;
2450	reg [7:0] bank_b_sf ;
2451	//
2452	initial begin
2453	bank_a_s0 = 8'h00 ;
2454	bank_a_s1 = 8'h00 ;
2455	bank_a_s2 = 8'h00 ;
2456	bank_a_s3 = 8'h00 ;
2457	bank_a_s4 = 8'h00 ;
2458	bank_a_s5 = 8'h00 ;
2459	bank_a_s6 = 8'h00 ;
2460	bank_a_s7 = 8'h00 ;
2461	bank_a_s8 = 8'h00 ;
2462	bank_a_s9 = 8'h00 ;
2463	bank_a_sa = 8'h00 ;
2464	bank_a_sb = 8'h00 ;
2465	bank_a_sc = 8'h00 ;
2466	bank_a_sd = 8'h00 ;
2467	bank_a_se = 8'h00 ;
2468	bank_a_sf = 8'h00 ;
2469	bank_b_s0 = 8'h00 ;
2470	bank_b_s1 = 8'h00 ;
2471	bank_b_s2 = 8'h00 ;
2472	bank_b_s3 = 8'h00 ;
2473	bank_b_s4 = 8'h00 ;
2474	bank_b_s5 = 8'h00 ;
2475	bank_b_s6 = 8'h00 ;
2476	bank_b_s7 = 8'h00 ;
2477	bank_b_s8 = 8'h00 ;
2478	bank_b_s9 = 8'h00 ;
2479	bank_b_sa = 8'h00 ;
2480	bank_b_sb = 8'h00 ;
2481	bank_b_sc = 8'h00 ;
2482	bank_b_sd = 8'h00 ;
2483	bank_b_se = 8'h00 ;
2484	bank_b_sf = 8'h00 ;
2485	end
2486	//
2487	// Temporary variables for instruction decoding
2488	//
2489	wire [1:16] sx_decode ; //sX register specification
2490	wire [1:16] sy_decode ; //sY register specification
2491	wire [1:16] kk_decode ; //constant value specification
2492	wire [1:24] aaa_decode ; //address specification
2493	wire clk_del ; // Delayed clock for simulation
2494	//
2495	/////////////////////////////////////////////////////////////////////////////////////////
2496	//
2497	// Function to convert 4-bit binary nibble to hexadecimal character
2498	//
2499	/////////////////////////////////////////////////////////////////////////////////////////
2500	//
2501	function [1:8] hexcharacter ;
2502	input [3:0] nibble ;
2503	begin
2504	case (nibble)
2505	4'b0000 : hexcharacter = "0" ;
2506	4'b0001 : hexcharacter = "1" ;
2507	4'b0010 : hexcharacter = "2" ;
2508	4'b0011 : hexcharacter = "3" ;
2509	4'b0100 : hexcharacter = "4" ;
2510	4'b0101 : hexcharacter = "5" ;
2511	4'b0110 : hexcharacter = "6" ;
2512	4'b0111 : hexcharacter = "7" ;
2513	4'b1000 : hexcharacter = "8" ;
2514	4'b1001 : hexcharacter = "9" ;
2515	4'b1010 : hexcharacter = "A" ;
2516	4'b1011 : hexcharacter = "B" ;
2517	4'b1100 : hexcharacter = "C" ;
2518	4'b1101 : hexcharacter = "D" ;
2519	4'b1110 : hexcharacter = "E" ;
2520	4'b1111 : hexcharacter = "F" ;
2521	endcase
2522	end
2523	endfunction
2524	//
2525	/////////////////////////////////////////////////////////////////////////////////////////
2526	//
2527	// decode first register sX
2528
2529	assign sx_decode[1:8] = "s";
2530	assign sx_decode[9:16] = hexcharacter(instruction[11:8]);
2531
2532	// decode second register sY
2533	assign sy_decode[1:8] = "s";
2534	assign sy_decode[9:16] = hexcharacter(instruction[7:4]);
2535
2536	// decode constant value
2537	assign kk_decode[1:8] = hexcharacter(instruction[7:4]);
2538	assign kk_decode[9:16] = hexcharacter(instruction[3:0]);
2539
2540	// address value
2541	assign aaa_decode[1:8] = hexcharacter(instruction[11:8]);
2542	assign aaa_decode[9:16] = hexcharacter(instruction[7:4]);
2543	assign aaa_decode[17:24] = hexcharacter(instruction[3:0]);
2544
2545	assign #200 clk_del = clk ;
2546	// decode instruction
2547	//always @ (clk or instruction or carry_flag or zero_flag or bank or interrupt_enable)
2548	always @ (posedge clk_del)
2549	begin : simulation
2550	case (instruction[17:12])
2551	6'b000000 : kcpsm6_opcode <= {"LOAD ", sx_decode, ", ", sy_decode, " "} ;
2552	6'b000001 : kcpsm6_opcode <= {"LOAD ", sx_decode, ", ", kk_decode, " "} ;
2553	6'b010110 : kcpsm6_opcode <= {"STAR ", sx_decode, ", ", sy_decode, " "} ;
2554	6'b010111 : kcpsm6_opcode <= {"STAR ", sx_decode, ", ", kk_decode, " "} ;
2555	6'b000010 : kcpsm6_opcode <= {"AND ", sx_decode, ", ", sy_decode, " "} ;
2556	6'b000011 : kcpsm6_opcode <= {"AND ", sx_decode, ", ", kk_decode, " "} ;
2557	6'b000100 : kcpsm6_opcode <= {"OR ", sx_decode, ", ", sy_decode, " "} ;
2558	6'b000101 : kcpsm6_opcode <= {"OR ", sx_decode, ", ", kk_decode, " "} ;
2559	6'b000110 : kcpsm6_opcode <= {"XOR ", sx_decode, ", ", sy_decode, " "} ;
2560	6'b000111 : kcpsm6_opcode <= {"XOR ", sx_decode, ", ", kk_decode, " "} ;
2561	6'b001100 : kcpsm6_opcode <= {"TEST ", sx_decode, ", ", sy_decode, " "} ;
2562	6'b001101 : kcpsm6_opcode <= {"TEST ", sx_decode, ", ", kk_decode, " "} ;
2563	6'b001110 : kcpsm6_opcode <= {"TESTCY ", sx_decode, ", ", sy_decode, " "} ;
2564	6'b001111 : kcpsm6_opcode <= {"TESTCY ", sx_decode, ", ", kk_decode, " "} ;
2565	6'b010000 : kcpsm6_opcode <= {"ADD ", sx_decode, ", ", sy_decode, " "} ;
2566	6'b010001 : kcpsm6_opcode <= {"ADD ", sx_decode, ", ", kk_decode, " "} ;
2567	6'b010010 : kcpsm6_opcode <= {"ADDCY ", sx_decode, ", ", sy_decode, " "} ;
2568	6'b010011 : kcpsm6_opcode <= {"ADDCY ", sx_decode, ", ", kk_decode, " "} ;
2569	6'b011000 : kcpsm6_opcode <= {"SUB ", sx_decode, ", ", sy_decode, " "} ;
2570	6'b011001 : kcpsm6_opcode <= {"SUB ", sx_decode, ", ", kk_decode, " "} ;
2571	6'b011010 : kcpsm6_opcode <= {"SUBCY ", sx_decode, ", ", sy_decode, " "} ;
2572	6'b011011 : kcpsm6_opcode <= {"SUBCY ", sx_decode, ", ", kk_decode, " "} ;
2573	6'b011100 : kcpsm6_opcode <= {"COMPARE ", sx_decode, ", ", sy_decode, " "} ;
2574	6'b011101 : kcpsm6_opcode <= {"COMPARE ", sx_decode, ", ", kk_decode, " "} ;
2575	6'b011110 : kcpsm6_opcode <= {"COMPARECY ", sx_decode, ", ", sy_decode, " "} ;
2576	6'b011111 : kcpsm6_opcode <= {"COMPARECY ", sx_decode, ", ", kk_decode, " "} ;
2577	6'b010100 : begin
2578	if (instruction[7] == 1'b1)
2579	kcpsm6_opcode <= {"HWBUILD ", sx_decode, " "} ;
2580	else
2581	case (instruction[3:0])
2582	4'b0110 : kcpsm6_opcode <= {"SL0 ", sx_decode, " "} ;
2583	4'b0111 : kcpsm6_opcode <= {"SL1 ", sx_decode, " "} ;
2584	4'b0100 : kcpsm6_opcode <= {"SLX ", sx_decode, " "} ;
2585	4'b0000 : kcpsm6_opcode <= {"SLA ", sx_decode, " "} ;
2586	4'b0010 : kcpsm6_opcode <= {"RL ", sx_decode, " "} ;
2587	4'b1110 : kcpsm6_opcode <= {"SR0 ", sx_decode, " "} ;
2588	4'b1111 : kcpsm6_opcode <= {"SR1 ", sx_decode, " "} ;
2589	4'b1010 : kcpsm6_opcode <= {"SRX ", sx_decode, " "} ;
2590	4'b1000 : kcpsm6_opcode <= {"SRA ", sx_decode, " "} ;
2591	4'b1100 : kcpsm6_opcode <= {"RR ", sx_decode, " "} ;
2592	default : kcpsm6_opcode <= "Invalid Instruction";
2593	endcase
2594	end
2595	6'b101100 : kcpsm6_opcode <= {"OUTPUT ", sx_decode, ", (", sy_decode, ") "} ;
2596	6'b101101 : kcpsm6_opcode <= {"OUTPUT ", sx_decode, ", ", kk_decode, " "} ;
2597	6'b101011 : kcpsm6_opcode <= {"OUTPUTK ", aaa_decode[1:16], ", ", aaa_decode[17:24], " " };
2598	6'b001000 : kcpsm6_opcode <= {"INPUT ", sx_decode, ", (", sy_decode, ") "} ;
2599	6'b001001 : kcpsm6_opcode <= {"INPUT ", sx_decode, ", ", kk_decode, " "} ;
2600	6'b101110 : kcpsm6_opcode <= {"STORE ", sx_decode, ", (", sy_decode, ") "} ;
2601	6'b101111 : kcpsm6_opcode <= {"STORE ", sx_decode, ", ", kk_decode, " "} ;
2602	6'b001010 : kcpsm6_opcode <= {"FETCH ", sx_decode, ", (", sy_decode, ") "} ;
2603	6'b001011 : kcpsm6_opcode <= {"FETCH ", sx_decode, ", ", kk_decode, " "} ;
2604	6'b100010 : kcpsm6_opcode <= {"JUMP ", aaa_decode, " "} ;
2605	6'b110010 : kcpsm6_opcode <= {"JUMP Z, ", aaa_decode, " "} ;
2606	6'b110110 : kcpsm6_opcode <= {"JUMP NZ, ", aaa_decode, " "} ;
2607	6'b111010 : kcpsm6_opcode <= {"JUMP C, ", aaa_decode, " "} ;
2608	6'b111110 : kcpsm6_opcode <= {"JUMP NC, ", aaa_decode, " "} ;
2609	6'b100110 : kcpsm6_opcode <= {"JUMP@ (", sx_decode, ", ", sy_decode, ") "} ;
2610	6'b100000 : kcpsm6_opcode <= {"CALL ", aaa_decode, " "} ;
2611	6'b110000 : kcpsm6_opcode <= {"CALL Z, ", aaa_decode, " "} ;
2612	6'b110100 : kcpsm6_opcode <= {"CALL NZ, ", aaa_decode, " "} ;
2613	6'b111000 : kcpsm6_opcode <= {"CALL C, ", aaa_decode, " "} ;
2614	6'b111100 : kcpsm6_opcode <= {"CALL NC, ", aaa_decode, " "} ;
2615	6'b100100 : kcpsm6_opcode <= {"CALL@ (", sx_decode, ", ", sy_decode, ") "} ;
2616	6'b100101 : kcpsm6_opcode <= {"RETURN "} ;
2617	6'b110001 : kcpsm6_opcode <= {"RETURN Z "} ;
2618	6'b110101 : kcpsm6_opcode <= {"RETURN NZ "} ;
2619	6'b111001 : kcpsm6_opcode <= {"RETURN C "} ;
2620	6'b111101 : kcpsm6_opcode <= {"RETURN NC "} ;
2621	6'b100001 : kcpsm6_opcode <= {"LOAD&RETURN ", sx_decode, ", ", kk_decode, " "} ;
2622	6'b101001 : begin
2623	case (instruction[0])
2624	1'b0 : kcpsm6_opcode <= "RETURNI DISABLE ";
2625	1'b1 : kcpsm6_opcode <= "RETURNI ENABLE ";
2626	default : kcpsm6_opcode <= "Invalid Instruction";
2627	endcase
2628	end
2629	6'b101000 : begin
2630	case (instruction[0])
2631	1'b0 : kcpsm6_opcode <= "DISABLE INTERRUPT ";
2632	1'b1 : kcpsm6_opcode <= "ENABLE INTERRUPT ";
2633	default : kcpsm6_opcode <= "Invalid Instruction";
2634	endcase
2635	end
2636	6'b110111 : begin
2637	case (instruction[0])
2638	1'b0 : kcpsm6_opcode <= "REGBANK A ";
2639	1'b1 : kcpsm6_opcode <= "REGBANK B ";
2640	default : kcpsm6_opcode <= "Invalid Instruction";
2641	endcase
2642	end
2643	default : kcpsm6_opcode <= "Invalid Instruction";
2644	endcase
2645
2646
2647
2648	// Flag status information
2649
2650	if (zero_flag == 1'b0)
2651	kcpsm6_status[17:40] <= "NZ,";
2652	else
2653	kcpsm6_status[17:40] <= " Z,";
2654
2655
2656	if (carry_flag == 1'b0)
2657	kcpsm6_status[41:64] <= "NC,";
2658	else
2659	kcpsm6_status[41:64] <= " C,";
2660
2661
2662	if (interrupt_enable == 1'b0)
2663	kcpsm6_status[65:80] <= "ID";
2664	else
2665	kcpsm6_status[65:80] <= "IE";
2666
2667
2668	// Operational status
2669
2670	if (clk) begin
2671	if (internal_reset == 1'b1)
2672	kcpsm6_status[81 : 128] <= ",Reset";
2673	else
2674	if (sync_sleep == 1'b1 && t_state == 2'b00)
2675	kcpsm6_status[81 : 128] <= ",Sleep";
2676	else
2677	kcpsm6_status[81 : 128] <= " ";
2678	end
2679
2680
2681	// Simulation of register contents
2682	if (clk) begin
2683	if (register_enable == 1'b1) begin
2684	case (sx_addr)
2685	5'b00000 : bank_a_s0 <= alu_result ;
2686	5'b00001 : bank_a_s1 <= alu_result ;
2687	5'b00010 : bank_a_s2 <= alu_result ;
2688	5'b00011 : bank_a_s3 <= alu_result ;
2689	5'b00100 : bank_a_s4 <= alu_result ;
2690	5'b00101 : bank_a_s5 <= alu_result ;
2691	5'b00110 : bank_a_s6 <= alu_result ;
2692	5'b00111 : bank_a_s7 <= alu_result ;
2693	5'b01000 : bank_a_s8 <= alu_result ;
2694	5'b01001 : bank_a_s9 <= alu_result ;
2695	5'b01010 : bank_a_sa <= alu_result ;
2696	5'b01011 : bank_a_sb <= alu_result ;
2697	5'b01100 : bank_a_sc <= alu_result ;
2698	5'b01101 : bank_a_sd <= alu_result ;
2699	5'b01110 : bank_a_se <= alu_result ;
2700	5'b01111 : bank_a_sf <= alu_result ;
2701	5'b10000 : bank_b_s0 <= alu_result ;
2702	5'b10001 : bank_b_s1 <= alu_result ;
2703	5'b10010 : bank_b_s2 <= alu_result ;
2704	5'b10011 : bank_b_s3 <= alu_result ;
2705	5'b10100 : bank_b_s4 <= alu_result ;
2706	5'b10101 : bank_b_s5 <= alu_result ;
2707	5'b10110 : bank_b_s6 <= alu_result ;
2708	5'b10111 : bank_b_s7 <= alu_result ;
2709	5'b11000 : bank_b_s8 <= alu_result ;
2710	5'b11001 : bank_b_s9 <= alu_result ;
2711	5'b11010 : bank_b_sa <= alu_result ;
2712	5'b11011 : bank_b_sb <= alu_result ;
2713	5'b11100 : bank_b_sc <= alu_result ;
2714	5'b11101 : bank_b_sd <= alu_result ;
2715	5'b11110 : bank_b_se <= alu_result ;
2716	5'b11111 : bank_b_sf <= alu_result ;
2717	endcase
2718	end
2719
2720	//simulation of scratch pad memory contents
2721	if (spm_enable == 1'b1) begin
2722	case (sy_or_kk)
2723	8'b00000000 : sim_spm00 <= sx;
2724	8'b00000001 : sim_spm01 <= sx;
2725	8'b00000010 : sim_spm02 <= sx;
2726	8'b00000011 : sim_spm03 <= sx;
2727	8'b00000100 : sim_spm04 <= sx;
2728	8'b00000101 : sim_spm05 <= sx;
2729	8'b00000110 : sim_spm06 <= sx;
2730	8'b00000111 : sim_spm07 <= sx;
2731	8'b00001000 : sim_spm08 <= sx;
2732	8'b00001001 : sim_spm09 <= sx;
2733	8'b00001010 : sim_spm0A <= sx;
2734	8'b00001011 : sim_spm0B <= sx;
2735	8'b00001100 : sim_spm0C <= sx;
2736	8'b00001101 : sim_spm0D <= sx;
2737	8'b00001110 : sim_spm0E <= sx;
2738	8'b00001111 : sim_spm0F <= sx;
2739	8'b00010000 : sim_spm10 <= sx;
2740	8'b00010001 : sim_spm11 <= sx;
2741	8'b00010010 : sim_spm12 <= sx;
2742	8'b00010011 : sim_spm13 <= sx;
2743	8'b00010100 : sim_spm14 <= sx;
2744	8'b00010101 : sim_spm15 <= sx;
2745	8'b00010110 : sim_spm16 <= sx;
2746	8'b00010111 : sim_spm17 <= sx;
2747	8'b00011000 : sim_spm18 <= sx;
2748	8'b00011001 : sim_spm19 <= sx;
2749	8'b00011010 : sim_spm1A <= sx;
2750	8'b00011011 : sim_spm1B <= sx;
2751	8'b00011100 : sim_spm1C <= sx;
2752	8'b00011101 : sim_spm1D <= sx;
2753	8'b00011110 : sim_spm1E <= sx;
2754	8'b00011111 : sim_spm1F <= sx;
2755	8'b00100000 : sim_spm20 <= sx;
2756	8'b00100001 : sim_spm21 <= sx;
2757	8'b00100010 : sim_spm22 <= sx;
2758	8'b00100011 : sim_spm23 <= sx;
2759	8'b00100100 : sim_spm24 <= sx;
2760	8'b00100101 : sim_spm25 <= sx;
2761	8'b00100110 : sim_spm26 <= sx;
2762	8'b00100111 : sim_spm27 <= sx;
2763	8'b00101000 : sim_spm28 <= sx;
2764	8'b00101001 : sim_spm29 <= sx;
2765	8'b00101010 : sim_spm2A <= sx;
2766	8'b00101011 : sim_spm2B <= sx;
2767	8'b00101100 : sim_spm2C <= sx;
2768	8'b00101101 : sim_spm2D <= sx;
2769	8'b00101110 : sim_spm2E <= sx;
2770	8'b00101111 : sim_spm2F <= sx;
2771	8'b00110000 : sim_spm30 <= sx;
2772	8'b00110001 : sim_spm31 <= sx;
2773	8'b00110010 : sim_spm32 <= sx;
2774	8'b00110011 : sim_spm33 <= sx;
2775	8'b00110100 : sim_spm34 <= sx;
2776	8'b00110101 : sim_spm35 <= sx;
2777	8'b00110110 : sim_spm36 <= sx;
2778	8'b00110111 : sim_spm37 <= sx;
2779	8'b00111000 : sim_spm38 <= sx;
2780	8'b00111001 : sim_spm39 <= sx;
2781	8'b00111010 : sim_spm3A <= sx;
2782	8'b00111011 : sim_spm3B <= sx;
2783	8'b00111100 : sim_spm3C <= sx;
2784	8'b00111101 : sim_spm3D <= sx;
2785	8'b00111110 : sim_spm3E <= sx;
2786	8'b00111111 : sim_spm3F <= sx;
2787	8'b01000000 : sim_spm40 <= sx;
2788	8'b01000001 : sim_spm41 <= sx;
2789	8'b01000010 : sim_spm42 <= sx;
2790	8'b01000011 : sim_spm43 <= sx;
2791	8'b01000100 : sim_spm44 <= sx;
2792	8'b01000101 : sim_spm45 <= sx;
2793	8'b01000110 : sim_spm46 <= sx;
2794	8'b01000111 : sim_spm47 <= sx;
2795	8'b01001000 : sim_spm48 <= sx;
2796	8'b01001001 : sim_spm49 <= sx;
2797	8'b01001010 : sim_spm4A <= sx;
2798	8'b01001011 : sim_spm4B <= sx;
2799	8'b01001100 : sim_spm4C <= sx;
2800	8'b01001101 : sim_spm4D <= sx;
2801	8'b01001110 : sim_spm4E <= sx;
2802	8'b01001111 : sim_spm4F <= sx;
2803	8'b01010000 : sim_spm50 <= sx;
2804	8'b01010001 : sim_spm51 <= sx;
2805	8'b01010010 : sim_spm52 <= sx;
2806	8'b01010011 : sim_spm53 <= sx;
2807	8'b01010100 : sim_spm54 <= sx;
2808	8'b01010101 : sim_spm55 <= sx;
2809	8'b01010110 : sim_spm56 <= sx;
2810	8'b01010111 : sim_spm57 <= sx;
2811	8'b01011000 : sim_spm58 <= sx;
2812	8'b01011001 : sim_spm59 <= sx;
2813	8'b01011010 : sim_spm5A <= sx;
2814	8'b01011011 : sim_spm5B <= sx;
2815	8'b01011100 : sim_spm5C <= sx;
2816	8'b01011101 : sim_spm5D <= sx;
2817	8'b01011110 : sim_spm5E <= sx;
2818	8'b01011111 : sim_spm5F <= sx;
2819	8'b01100000 : sim_spm60 <= sx;
2820	8'b01100001 : sim_spm61 <= sx;
2821	8'b01100010 : sim_spm62 <= sx;
2822	8'b01100011 : sim_spm63 <= sx;
2823	8'b01100100 : sim_spm64 <= sx;
2824	8'b01100101 : sim_spm65 <= sx;
2825	8'b01100110 : sim_spm66 <= sx;
2826	8'b01100111 : sim_spm67 <= sx;
2827	8'b01101000 : sim_spm68 <= sx;
2828	8'b01101001 : sim_spm69 <= sx;
2829	8'b01101010 : sim_spm6A <= sx;
2830	8'b01101011 : sim_spm6B <= sx;
2831	8'b01101100 : sim_spm6C <= sx;
2832	8'b01101101 : sim_spm6D <= sx;
2833	8'b01101110 : sim_spm6E <= sx;
2834	8'b01101111 : sim_spm6F <= sx;
2835	8'b01110000 : sim_spm70 <= sx;
2836	8'b01110001 : sim_spm71 <= sx;
2837	8'b01110010 : sim_spm72 <= sx;
2838	8'b01110011 : sim_spm73 <= sx;
2839	8'b01110100 : sim_spm74 <= sx;
2840	8'b01110101 : sim_spm75 <= sx;
2841	8'b01110110 : sim_spm76 <= sx;
2842	8'b01110111 : sim_spm77 <= sx;
2843	8'b01111000 : sim_spm78 <= sx;
2844	8'b01111001 : sim_spm79 <= sx;
2845	8'b01111010 : sim_spm7A <= sx;
2846	8'b01111011 : sim_spm7B <= sx;
2847	8'b01111100 : sim_spm7C <= sx;
2848	8'b01111101 : sim_spm7D <= sx;
2849	8'b01111110 : sim_spm7E <= sx;
2850	8'b01111111 : sim_spm7F <= sx;
2851	8'b10000000 : sim_spm80 <= sx;
2852	8'b10000001 : sim_spm81 <= sx;
2853	8'b10000010 : sim_spm82 <= sx;
2854	8'b10000011 : sim_spm83 <= sx;
2855	8'b10000100 : sim_spm84 <= sx;
2856	8'b10000101 : sim_spm85 <= sx;
2857	8'b10000110 : sim_spm86 <= sx;
2858	8'b10000111 : sim_spm87 <= sx;
2859	8'b10001000 : sim_spm88 <= sx;
2860	8'b10001001 : sim_spm89 <= sx;
2861	8'b10001010 : sim_spm8A <= sx;
2862	8'b10001011 : sim_spm8B <= sx;
2863	8'b10001100 : sim_spm8C <= sx;
2864	8'b10001101 : sim_spm8D <= sx;
2865	8'b10001110 : sim_spm8E <= sx;
2866	8'b10001111 : sim_spm8F <= sx;
2867	8'b10010000 : sim_spm90 <= sx;
2868	8'b10010001 : sim_spm91 <= sx;
2869	8'b10010010 : sim_spm92 <= sx;
2870	8'b10010011 : sim_spm93 <= sx;
2871	8'b10010100 : sim_spm94 <= sx;
2872	8'b10010101 : sim_spm95 <= sx;
2873	8'b10010110 : sim_spm96 <= sx;
2874	8'b10010111 : sim_spm97 <= sx;
2875	8'b10011000 : sim_spm98 <= sx;
2876	8'b10011001 : sim_spm99 <= sx;
2877	8'b10011010 : sim_spm9A <= sx;
2878	8'b10011011 : sim_spm9B <= sx;
2879	8'b10011100 : sim_spm9C <= sx;
2880	8'b10011101 : sim_spm9D <= sx;
2881	8'b10011110 : sim_spm9E <= sx;
2882	8'b10011111 : sim_spm9F <= sx;
2883	8'b10100000 : sim_spmA0 <= sx;
2884	8'b10100001 : sim_spmA1 <= sx;
2885	8'b10100010 : sim_spmA2 <= sx;
2886	8'b10100011 : sim_spmA3 <= sx;
2887	8'b10100100 : sim_spmA4 <= sx;
2888	8'b10100101 : sim_spmA5 <= sx;
2889	8'b10100110 : sim_spmA6 <= sx;
2890	8'b10100111 : sim_spmA7 <= sx;
2891	8'b10101000 : sim_spmA8 <= sx;
2892	8'b10101001 : sim_spmA9 <= sx;
2893	8'b10101010 : sim_spmAA <= sx;
2894	8'b10101011 : sim_spmAB <= sx;
2895	8'b10101100 : sim_spmAC <= sx;
2896	8'b10101101 : sim_spmAD <= sx;
2897	8'b10101110 : sim_spmAE <= sx;
2898	8'b10101111 : sim_spmAF <= sx;
2899	8'b10110000 : sim_spmB0 <= sx;
2900	8'b10110001 : sim_spmB1 <= sx;
2901	8'b10110010 : sim_spmB2 <= sx;
2902	8'b10110011 : sim_spmB3 <= sx;
2903	8'b10110100 : sim_spmB4 <= sx;
2904	8'b10110101 : sim_spmB5 <= sx;
2905	8'b10110110 : sim_spmB6 <= sx;
2906	8'b10110111 : sim_spmB7 <= sx;
2907	8'b10111000 : sim_spmB8 <= sx;
2908	8'b10111001 : sim_spmB9 <= sx;
2909	8'b10111010 : sim_spmBA <= sx;
2910	8'b10111011 : sim_spmBB <= sx;
2911	8'b10111100 : sim_spmBC <= sx;
2912	8'b10111101 : sim_spmBD <= sx;
2913	8'b10111110 : sim_spmBE <= sx;
2914	8'b10111111 : sim_spmBF <= sx;
2915	8'b11000000 : sim_spmC0 <= sx;
2916	8'b11000001 : sim_spmC1 <= sx;
2917	8'b11000010 : sim_spmC2 <= sx;
2918	8'b11000011 : sim_spmC3 <= sx;
2919	8'b11000100 : sim_spmC4 <= sx;
2920	8'b11000101 : sim_spmC5 <= sx;
2921	8'b11000110 : sim_spmC6 <= sx;
2922	8'b11000111 : sim_spmC7 <= sx;
2923	8'b11001000 : sim_spmC8 <= sx;
2924	8'b11001001 : sim_spmC9 <= sx;
2925	8'b11001010 : sim_spmCA <= sx;
2926	8'b11001011 : sim_spmCB <= sx;
2927	8'b11001100 : sim_spmCC <= sx;
2928	8'b11001101 : sim_spmCD <= sx;
2929	8'b11001110 : sim_spmCE <= sx;
2930	8'b11001111 : sim_spmCF <= sx;
2931	8'b11010000 : sim_spmD0 <= sx;
2932	8'b11010001 : sim_spmD1 <= sx;
2933	8'b11010010 : sim_spmD2 <= sx;
2934	8'b11010011 : sim_spmD3 <= sx;
2935	8'b11010100 : sim_spmD4 <= sx;
2936	8'b11010101 : sim_spmD5 <= sx;
2937	8'b11010110 : sim_spmD6 <= sx;
2938	8'b11010111 : sim_spmD7 <= sx;
2939	8'b11011000 : sim_spmD8 <= sx;
2940	8'b11011001 : sim_spmD9 <= sx;
2941	8'b11011010 : sim_spmDA <= sx;
2942	8'b11011011 : sim_spmDB <= sx;
2943	8'b11011100 : sim_spmDC <= sx;
2944	8'b11011101 : sim_spmDD <= sx;
2945	8'b11011110 : sim_spmDE <= sx;
2946	8'b11011111 : sim_spmDF <= sx;
2947	8'b11100000 : sim_spmE0 <= sx;
2948	8'b11100001 : sim_spmE1 <= sx;
2949	8'b11100010 : sim_spmE2 <= sx;
2950	8'b11100011 : sim_spmE3 <= sx;
2951	8'b11100100 : sim_spmE4 <= sx;
2952	8'b11100101 : sim_spmE5 <= sx;
2953	8'b11100110 : sim_spmE6 <= sx;
2954	8'b11100111 : sim_spmE7 <= sx;
2955	8'b11101000 : sim_spmE8 <= sx;
2956	8'b11101001 : sim_spmE9 <= sx;
2957	8'b11101010 : sim_spmEA <= sx;
2958	8'b11101011 : sim_spmEB <= sx;
2959	8'b11101100 : sim_spmEC <= sx;
2960	8'b11101101 : sim_spmED <= sx;
2961	8'b11101110 : sim_spmEE <= sx;
2962	8'b11101111 : sim_spmEF <= sx;
2963	8'b11110000 : sim_spmF0 <= sx;
2964	8'b11110001 : sim_spmF1 <= sx;
2965	8'b11110010 : sim_spmF2 <= sx;
2966	8'b11110011 : sim_spmF3 <= sx;
2967	8'b11110100 : sim_spmF4 <= sx;
2968	8'b11110101 : sim_spmF5 <= sx;
2969	8'b11110110 : sim_spmF6 <= sx;
2970	8'b11110111 : sim_spmF7 <= sx;
2971	8'b11111000 : sim_spmF8 <= sx;
2972	8'b11111001 : sim_spmF9 <= sx;
2973	8'b11111010 : sim_spmFA <= sx;
2974	8'b11111011 : sim_spmFB <= sx;
2975	8'b11111100 : sim_spmFC <= sx;
2976	8'b11111101 : sim_spmFD <= sx;
2977	8'b11111110 : sim_spmFE <= sx;
2978	8'b11111111 : sim_spmFF <= sx;
2979	endcase
2980	end
2981
2982	end
2983
2984	//
2985	// Assignment of internal register variables to active registers
2986	//
2987	if (bank == 1'b0) begin
2988	kcpsm6_status[1:16] <= "A,";
2989	sim_s0 <= bank_a_s0 ;
2990	sim_s1 <= bank_a_s1 ;
2991	sim_s2 <= bank_a_s2 ;
2992	sim_s3 <= bank_a_s3 ;
2993	sim_s4 <= bank_a_s4 ;
2994	sim_s5 <= bank_a_s5 ;
2995	sim_s6 <= bank_a_s6 ;
2996	sim_s7 <= bank_a_s7 ;
2997	sim_s8 <= bank_a_s8 ;
2998	sim_s9 <= bank_a_s9 ;
2999	sim_sA <= bank_a_sa ;
3000	sim_sB <= bank_a_sb ;
3001	sim_sC <= bank_a_sc ;
3002	sim_sD <= bank_a_sd ;
3003	sim_sE <= bank_a_se ;
3004	sim_sF <= bank_a_sf ;
3005	end
3006	else begin
3007	kcpsm6_status[1:16] <= "B,";
3008	sim_s0 <= bank_b_s0 ;
3009	sim_s1 <= bank_b_s1 ;
3010	sim_s2 <= bank_b_s2 ;
3011	sim_s3 <= bank_b_s3 ;
3012	sim_s4 <= bank_b_s4 ;
3013	sim_s5 <= bank_b_s5 ;
3014	sim_s6 <= bank_b_s6 ;
3015	sim_s7 <= bank_b_s7 ;
3016	sim_s8 <= bank_b_s8 ;
3017	sim_s9 <= bank_b_s9 ;
3018	sim_sA <= bank_b_sa ;
3019	sim_sB <= bank_b_sb ;
3020	sim_sC <= bank_b_sc ;
3021	sim_sD <= bank_b_sd ;
3022	sim_sE <= bank_b_se ;
3023	sim_sF <= bank_b_sf ;
3024	end
3025	//
3026	//
3027	end //process simulation;
3028
3029	//synthesis translate_on
3030	//
3031	// **************************
3032	// * End of simulation code *
3033	// **************************
3034	//
3035	//
3036	///////////////////////////////////////////////////////////////////////////////////////////
3037	//
3038	endmodule
3039	//
3040	///////////////////////////////////////////////////////////////////////////////////////////
3041	//
3042	// END OF FILE kcpsm6.v
3043	//
3044	///////////////////////////////////////////////////////////////////////////////////////////

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source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/kcpsm6.v

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