1 | ;*************************************************************************************** |
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2 | ;RF ref clk buffer (AD9512): |
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3 | ; CLK1: Input from on-board 80MHz oscillator |
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4 | ; CLK2: Input from clock module |
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5 | ; OUT0: LVPECL output to clock module |
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6 | ; OUT1: Unused LVPECL output (not terminated) |
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7 | ; OUT2: Unused LVPECL output (not terminated) |
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8 | ; OUT3: LVCMOS outputs to RFA/RFB MAX2829 (p: RFB, n: RFA) |
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9 | ; OUT4: LVDS output to FMC slot |
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10 | ; |
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11 | ; All configs not listed below are handled post-boot by MicroBlaze application |
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12 | ; |
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13 | ; No Clock Module: |
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14 | ; Do nothing - all config handled post-boot by MicroBlaze application |
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15 | ; |
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16 | ; CM-MMCX Configs: |
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17 | ; A/B/C: Do nothing |
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18 | ; |
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19 | ; CM-PLL Configs: |
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20 | ; A: Select CLK1 input (on-board osc), enable OUT0 (output to clock module) as 10MHz full-scale LVPECL |
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21 | ; B/C: Do nothing |
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22 | ; |
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23 | ; Relevant registers: |
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24 | ; 45: Selects clock input: 00 for off-board, 01 for on-board |
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25 | ; 4A: 33 sets divider on OUT0 (output to clk mod) to 8, 50% duty cycle |
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26 | ; 4B: 00 enables divider on OUT0 (output to clk mod) |
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27 | ; 3D: 08 configures LVPECL output OUT0 (output to clk mod) for max drive |
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28 | ; 5A: Trigger device update from SPI registers (self-clearing) |
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29 | ;*************************************************************************************** |
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30 | TABLE TBL_CFG_NOCM_RFREF_ADDR#, [FF] |
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31 | TABLE TBL_CFG_NOCM_RFREF_DATA#, [FF] |
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32 | |
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33 | TABLE TBL_CFG_CMMMCX_A_RFREF_ADDR#, [FF] |
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34 | TABLE TBL_CFG_CMMMCX_A_RFREF_DATA#, [FF] |
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35 | |
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36 | TABLE TBL_CFG_CMMMCX_B_RFREF_ADDR#, [FF] |
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37 | TABLE TBL_CFG_CMMMCX_B_RFREF_DATA#, [FF] |
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38 | |
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39 | TABLE TBL_CFG_CMMMCX_C_RFREF_ADDR#, [FF] |
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40 | TABLE TBL_CFG_CMMMCX_C_RFREF_DATA#, [FF] |
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41 | |
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42 | TABLE TBL_CFG_CMPLL_A_RFREF_ADDR#, [45, 4A, 4B, 3D, 5A, FF] |
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43 | TABLE TBL_CFG_CMPLL_A_RFREF_DATA#, [01, 33, 00, 08, 01, FF] |
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44 | |
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45 | TABLE TBL_CFG_CMPLL_B_RFREF_ADDR#, [FF] |
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46 | TABLE TBL_CFG_CMPLL_B_RFREF_DATA#, [FF] |
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47 | |
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48 | TABLE TBL_CFG_CMPLL_C_RFREF_ADDR#, [FF] |
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49 | TABLE TBL_CFG_CMPLL_C_RFREF_DATA#, [FF] |
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50 | |
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51 | ;*************************************************************************************** |
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52 | ;Samp clk buffer (AD9512): |
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53 | ; CLK1: Input from on-board 80MHz oscillator |
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54 | ; CLK2: Input from clock module |
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55 | ; OUT0: LVPECL output to RFB AD9963 |
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56 | ; OUT1: LVPECL output to clock module |
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57 | ; OUT2: LVPECL output to RFA AD9963 |
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58 | ; OUT3: LVDS output to FPGA |
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59 | ; OUT4: LVDS output to FMC slot |
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60 | ; |
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61 | ; All configs not listed below are handled post-boot by MicroBlaze application |
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62 | ; |
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63 | ; No Clock Module: |
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64 | ; -Select CLK1 |
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65 | ; -Enable OUT3 as 80MHz LVDS |
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66 | ; |
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67 | ; CM-MMCX Configs: |
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68 | ; A: Same as No Clock Module |
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69 | ; |
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70 | ; B/C: -Select CLK2 |
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71 | ; -Enable OUT3 as 80MHz LVDS |
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72 | ; |
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73 | ; CM-PLL Configs: |
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74 | ; A/B/C: -Select CLK2 (input from clock module) |
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75 | ; -Enable OUT3 (output to FPGA) as 80MHz LVDS |
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76 | ; |
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77 | ; Relevant registers: |
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78 | ; 45: Selects clock input: 00 for off-board, 01 for on-board |
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79 | ; 51: 80 bypasses OUT3 divider (output to FPGA) |
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80 | ; 5A: Trigger device update from SPI registers (self-clearing) |
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81 | ;***************************************************************************************/ |
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82 | TABLE TBL_CFG_NOCM_SAMP_ADDR#, [45, 51, 5A, FF] |
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83 | TABLE TBL_CFG_NOCM_SAMP_DATA#, [01, 80, 01, FF] |
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84 | |
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85 | TABLE TBL_CFG_CMMMCX_A_SAMP_ADDR#, [45, 51, 5A, FF] |
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86 | TABLE TBL_CFG_CMMMCX_A_SAMP_DATA#, [01, 80, 01, FF] |
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87 | |
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88 | TABLE TBL_CFG_CMMMCX_B_SAMP_ADDR#, [45, 51, 5A, FF] |
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89 | TABLE TBL_CFG_CMMMCX_B_SAMP_DATA#, [00, 80, 01, FF] |
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90 | |
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91 | TABLE TBL_CFG_CMMMCX_C_SAMP_ADDR#, [45, 51, 5A, FF] |
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92 | TABLE TBL_CFG_CMMMCX_C_SAMP_DATA#, [00, 80, 01, FF] |
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93 | |
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94 | TABLE TBL_CFG_CMPLL_A_SAMP_ADDR#, [45, 51, 5A, FF] |
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95 | TABLE TBL_CFG_CMPLL_A_SAMP_DATA#, [00, 80, 01, FF] |
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96 | |
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97 | TABLE TBL_CFG_CMPLL_B_SAMP_ADDR#, [45, 51, 5A, FF] |
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98 | TABLE TBL_CFG_CMPLL_B_SAMP_DATA#, [00, 80, 01, FF] |
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99 | |
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100 | TABLE TBL_CFG_CMPLL_C_SAMP_ADDR#, [45, 51, 5A, FF] |
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101 | TABLE TBL_CFG_CMPLL_C_SAMP_DATA#, [00, 80, 01, FF] |
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102 | |
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103 | ;*************************************************************************************** |
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104 | ;CM-PLL Buffer/PLL (AD9511): |
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105 | ; CLK1: Input from off-board reference, bypasses PLL |
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106 | ; CLK2: Input from on-board 80MHz VCXO |
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107 | ; OUT0/1/2: Unused LVPECL outputs (unterminated) |
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108 | ; OUT3: LVDS output to clock module header RFCLKBUF pins (rf ref clk buf CLK2 input) |
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109 | ; OUT4: LVDS output to clock module header SAMPCLKBUF pins (samp clk buf CLK2 input) |
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110 | ; |
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111 | ; All configs not listed below are handled post-boot by MicroBlaze application |
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112 | ; |
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113 | ; No Clock Module: |
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114 | ; Toggle reset, power down PLL core and all outputs |
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115 | ; This handles the case of the CM-PLL being mounted but its switches being set to 00 |
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116 | ; It's better to do SPI writes to open pins (i.e. no CM) than let the PLL run free |
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117 | ; |
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118 | ; CM-MMCX Configs: |
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119 | ; Do nothing - no PLL |
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120 | ; |
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121 | ; CM-PLL Configs: |
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122 | ; Common: |
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123 | ; -Toggle reset |
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124 | ; -Disable OUT0/1/2 (unused) |
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125 | ; -Enable OUT4 as 80MHz max-drive LVDS |
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126 | ; |
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127 | ; A: -Configure PLL for 10MHz reference (see below) |
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128 | ; -Disable OUT3 (output to RF ref clk buf) |
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129 | ; |
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130 | ; B: -Configure PLL for 10MHz reference (see below) |
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131 | ; -Enable OUT3 (output to RF ref clk buf) |
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132 | ; |
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133 | ; C: -Configure PLL for 80MHz reference (see below) |
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134 | ; -Enable OUT3 (output to RF ref clk buf) |
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135 | ; |
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136 | ; Relevant registers: |
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137 | ; 00: 30 resets, 10 un-resets |
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138 | ; 04: A counter b[5:0] |
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139 | ; 05: B counter b[12:8] |
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140 | ; 06: B counter b[7:0] |
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141 | ; 0B: R counter b[13:8] |
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142 | ; 0C: R counter b[7:0] |
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143 | ; 07: 00 disables loss-of-reference state machine |
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144 | ; 08: 47 enables charge pump, sets STATUS=lock_det, sets positive PFD polarity |
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145 | ; 09: 70 sets max charge pump current |
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146 | ; 0A: 08 for normal operation, 10MHz ref; 040 for normal operation, 80MHz ref) |
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147 | ; b[1:0]: PLL powerdown (00 or 10=normal operation, 01 or 11=powe down) |
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148 | ; b[4:2]: Prescaler mode (see datasheet for full list) |
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149 | ; 000: FD, div by 1 |
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150 | ; 010: DM, (P/P+1)=2/3 |
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151 | ; 3D/3E/3F: 03 powers down LVPECL outputs OUT0/1/2 |
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152 | ; 40/41: 01 disables OUT3/4, 02 enables LVDS output OUT3/4 |
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153 | ; 51/53: 80 disables divider (W3 board wants 80MHz inputs from clk module) |
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154 | ; 45: 02 selects CLK2 (VCXO clk src), powers down CLK1 input, powers up all other I/O |
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155 | ; 5A: Trigger device update from SPI registers (self-clearing) |
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156 | ; |
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157 | ; Common reference frequency configs: |
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158 | ; 10MHz: |
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159 | ; PFD freq: 10MHz |
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160 | ; R divider: 1 |
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161 | ; N divider: 8 (implies DM mode, prescaler mode (2/3), A=2, B=3) |
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162 | ; |
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163 | ; 80MHz: |
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164 | ; PFD freq: 80MHz |
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165 | ; R divider: 1 |
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166 | ; N divider: 1 (implies FD mode, prescaler mode div 1, B=1 (bypassed)) |
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167 | ; |
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168 | ; See AD9511 datasheet Table 16 for PLL settings for other valid divider settings |
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169 | ; |
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170 | ;***************************************************************************************/ |
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171 | |
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172 | TABLE TBL_CFG_NOCM_PLL_ADDR#, [00, 00, 0A, 3D, 3E, 3F, 40, 41, FF] |
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173 | TABLE TBL_CFG_NOCM_PLL_DATA#, [30, 10, 11, 03, 03, 03, 01, 01, FF] |
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174 | |
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175 | TABLE TBL_CFG_CMPLL_A_PLL_ADDR#, [00, 00, 04, 05, 06, 0B, 0C, 07, 08, 09, 0A, 3D, 3E, 3F, 40, 41, 51, 53, 45, 5A, FF] |
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176 | TABLE TBL_CFG_CMPLL_A_PLL_DATA#, [30, 10, 02, 00, 03, 00, 01, 00, 47, 70, 08, 03, 03, 03, 01, 02, 80, 80, 02, 01, FF] |
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177 | |
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178 | TABLE TBL_CFG_CMPLL_B_PLL_ADDR#, [00, 00, 04, 05, 06, 0B, 0C, 07, 08, 09, 0A, 3D, 3E, 3F, 40, 41, 51, 53, 45, 5A, FF] |
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179 | TABLE TBL_CFG_CMPLL_B_PLL_DATA#, [30, 10, 02, 00, 03, 00, 01, 00, 47, 70, 08, 03, 03, 03, 02, 02, 80, 80, 02, 01, FF] |
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180 | |
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181 | TABLE TBL_CFG_CMPLL_C_PLL_ADDR#, [00, 00, 04, 05, 06, 0B, 0C, 07, 08, 09, 0A, 3D, 3E, 3F, 40, 41, 51, 53, 45, 5A, FF] |
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182 | TABLE TBL_CFG_CMPLL_C_PLL_DATA#, [30, 10, 02, 00, 03, 00, 01, 00, 47, 70, 40, 03, 03, 03, 02, 02, 80, 80, 02, 01, FF] |
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