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i2c_routines.psm

Last change on this file was 4304, checked in by murphpo, 9 years ago
Adding assembly includes for clk config picoblaze program
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45	;
46	;
47	; PicoBlaze Reference Design.
48	;
49	;
50	; Routines for General Purpose I2C Communication
51	;
52	; Ken Chapman - Xilinx Ltd
53	;
54	; 9th March 2012 - Initial Version
55	; 12th October 2012 - Adjustments to values assigned to constant directives
56	; 16th October 2012 - Code optimisation (lowest level signal drive routines)
57	; 25th October 2012 - Correct definition of a binary value (functionally identical)
58	; 6th November 2012 - Correction to comment only
59	;
60	;
61	; NOTE - This is not a standalone PSM file. Include this file in a program that
62	; then calls these routines and works with the values in scratch pad memory.
63	;
64	; INCLUDE "i2c_routines.psm"
65	;
66	;
67	; IMPORTANT - These routines interact with input and output ports which must
68	; be appropriately defined to drive and read the physical I2C
69	; signals. Four CONSTANT directives must define values consistent
70	; with your port definitions and a further CONSTANT must be defined
71	; that is related to the frequency of the clock being applied to
72	; KCPSM6 in your design (Please see descriptions below).
73	;
74	;
75	; INTRODUCTION
76	; ------------
77	;
78	; The following routines implement an I2C 'Master' with a communication data rate
79	; approaching (but not exceeding) 100KHz. The I2C bus connects to the FPGA I/O
80	; pins which must in turn be connected to KCPSM6 input and output ports. Therefore
81	; your hardware design must be appropriate before these routines can be used and
82	; these routines need to know which ports you have allocated for I2C in your design.
83	;
84	; With the hardware in place, the routines provide the ability to perform each of the
85	; actions generally required for an I2C transaction including bus idle, Start (S),
86	; Repeated Start (Sr), Stop (P), Transmission of Acknowledge (ACK) or No Acknowledge
87	; (NACK), receiving and testing of Acknowledge (ACK) from a slave and of course the
88	; ability to transmit and receive bytes used for addressing, commands and data.
89	;
90	; It is assumed that you are familiar with I2C, so the descriptions contained in this
91	; file are concerned primarily with how KCPSM6 is used to implement the signaling and
92	; elements of the transactions rather than to teach I2C itself. In the end, it is the
93	; sequence in which these routines are invoked that will result in successful
94	; communication with a slave device and that requires an understanding of the needs
95	; of each particular slave to implement correctly (i.e. a study of data sheets for
96	; slave devices when writing higher level code).
97	;
98	; NOTE - As provided, these routines assume that KCPSM6 is the only I2C master connected
99	; to the bus. A multiple master implementation would be possible but these routines
100	; are not suitable in such arrangements.
101	;
102	;
103	;
104	; Code typical of an I2C write of data to a slave using the routines provided...
105	;
106	; CALL I2C_initialise
107	; CALL I2C_start
108	; LOAD s5, slave_address ;7-bit slave address
109	; SL0 s5 ;Write operation signified by LSB = 0
110	; CALL I2C_Tx_byte
111	; CALL I2C_Rx_ACK
112	; JUMP C, communication_fail ;did the slave respond?
113	; LOAD s5, data_byte1
114	; CALL I2C_Tx_byte
115	; CALL I2C_Rx_ACK
116	; LOAD s5, data_byte2
117	; CALL I2C_Tx_byte
118	; CALL I2C_Rx_ACK
119	; CALL I2C_stop
120	;
121	;
122	; Code typical of an I2C read of data from a slave using the routines provided...
123	;
124	; CALL I2C_initialise
125	; CALL I2C_start
126	; LOAD s5, slave_address ;7-bit slave address
127	; SL0 s5 ;Write operation signified by LSB = 0
128	; CALL I2C_Tx_byte
129	; CALL I2C_Rx_ACK
130	; JUMP C, communication_fail ;did the slave respond?
131	; LOAD s5, slave_command
132	; CALL I2C_Tx_byte
133	; CALL I2C_Rx_ACK
134	; CALL I2C_start ;bus restart (Sr)
135	; LOAD s5, slave_address ;7-bit slave address
136	; SL1 s5 ;Read operation signified by LSB = 1
137	; CALL I2C_Tx_byte
138	; CALL I2C_Rx_ACK
139	; CALL I2C_Rx_byte
140	; STORE s5, data1
141	; CALL I2C_Tx_ACK
142	; CALL I2C_Rx_byte
143	; STORE s5, data2
144	; CALL I2C_Tx_NACK ;transmit NACK before Stop
145	; CALL I2C_stop
146	;
147	;
148	;------------------------------------------------------------------------------------------
149	; Hardware
150	;------------------------------------------------------------------------------------------
151	;
152	; Clock
153	; -----
154	;
155	; All KCPSM6 instructions take 2 clock cycles to execute and it is this predictability
156	; that these routines exploit to ensure that the I2C communication rate does not exceed
157	; 100KHz. However, these routines will only implement the correct timing if something
158	; related to the frequency of the clock provide to KCPSM6 is known and the CONSTANT
159	; directive below must be defined correctly to achieve that.
160	;
161	CONSTANT I2C_time_reference, 49'd
162	;
163	; I2C_time_reference = ( fclk - 6 ) / 4
164	;
165	; Where...
166	; 'fclk' is the clock frequency applied to KCPSM6 in MHz.
167	; Any non-integer result should be rounded up.
168	; Typical values....
169	;
170	; fclk (MHz) I2C_time_reference
171	; 50 11'd
172	; 80 19'd
173	; 100 24'd
174	; 200 49'd
175	;
176	;
177	;
178	; I2C Bus and KCPSM6 ports
179	; ------------------------
180	;
181	; An I2C bus consists of two signals called 'CLK' and 'DATA' or something similar. Both
182	; signals need to be connected to the FPGA via 'open collector' style bidirectional I/O
183	; pins with a pull-up resistor (typically an external resistor but the built in pull-up
184	; resistor of the IOB may also be enabled in some cases). These I/O pins must then be
185	; connected to a KCPSM6 input port and KCPSM6 output port such that both signals can
186	; be both driven and read.
187	;
188	; The input port used to read the logic levels on the CLK and DATA signals external
189	; to the FPGA.
190	;
191	; The output port is used to control the output drive of the CLK and DATA pins.
192	; Since the pins are 'open collector' style then when KCPSM6 outputs...
193	; '0' will result in the signal being driven Low.
194	; '1' will result in the pin becoming tri-state (Z) so the signal will be pulled
195	; High by the resistor or can be driven or held low by a slave device.
196	;
197	; In a typical VHDL based design the following snippets of code could be inserted at the
198	; appropriate places to define the I2C pins and connection to KCPSM6...
199	;
200	; entity <name>
201	; Port ( i2c_clk : inout std_logic;
202	; i2c_data : inout std_logic;
203	;
204	;
205	; signal drive_i2c_clk : std_logic;
206	; signal drive_i2c_data : std_logic;
207	;
208	;
209	; i2c_clk <= '0' when drive_i2c_clk = '0' else 'Z';
210	; i2c_data <= '0' when drive_i2c_data = '0' else 'Z';
211	;
212	;
213	; input_ports: process(clk)
214	; begin
215	; if clk'event and clk = '1' then
216	; case port_id(1 downto 0) is
217	;
218	; -- Read I2C Bus at port address 02 hex
219	; when "10" => in_port(0) <= i2c_clk;
220	; in_port(1) <= i2c_data;
221	;
222	;
223	; output_ports: process(clk)
224	; begin
225	; if clk'event and clk = '1' then
226	; if write_strobe = '1' then
227	;
228	; -- Write to I2C Bus at port address 08 hex
229	; if port_id(3) = '1' then
230	; drive_i2c_clk <= out_port(0);
231	; drive_i2c_data <= out_port(1);
232	; end if;
233	;
234	;
235	;
236	; To correspond with the definition of the input and output ports, the four CONSTANT
237	; directives below must be set correctly before these I2C routines are used. The
238	; values shown below correspond with the VHDL snippets above.
239	;
240	CONSTANT I2C_clk, 00000001'b ;Bit to which CLK is assigned on both ports
241	CONSTANT I2C_data, 00000010'b ;Bit to which DATA is assigned on both ports
242	;
243	;
244	;------------------------------------------------------------------------------------------
245	; Registers
246	;------------------------------------------------------------------------------------------
247	;
248	; The following registers within the currently active bank are used by these routines....
249	;
250	; s0, s1, s5 and sF
251	;
252	;
253	; IMPORTANT - Register 'sF' is used to control and remember the drive values of the CLK
254	; and DATA signals so its contents MUST NOT be altered between calls to the
255	; various routines used to construct a complete I2C transaction. The routine
256	; called 'I2C_initialise' is typically used before starting any transaction
257	; as it will initialise 'sF' as well as the actual I2C interface.
258	;
259	;
260	;------------------------------------------------------------------------------------------
261	; Routine to initialise the CLK and DATA signals (and 'sF')
262	;------------------------------------------------------------------------------------------
263	;
264	; Places CLK and DATA into tri-state (Z) so that both lines reach idle High level.
265	; This also initialises register sF ready for other routines forming a transaction.
266	;
267	; This routine MUST be used before starting the first I2C transaction and before any
268	; further transaction if the contents of register 'sF' have been compromised since the
269	; end of the last I2C transaction.
270	;
271	I2C_initialise: LOAD sF, I2C_clk ;CLK = Z
272	OR sF, I2C_data ;DATA = Z
273	OUTPUT sF, port_IIC_OUT
274	RETURN
275	;
276	;
277	;------------------------------------------------------------------------------------------
278	; Routine issue an I2C Start (S) or Repeated Start (Sr) condition.
279	;------------------------------------------------------------------------------------------
280	;
281	; Used to begin any I2C transaction or performed during a transaction when changing the
282	; from an write to a read.
283	;
284	; The Start (S) or Repeated Start (Sr) condition is signified by a High to Low transition
285	; of the DATA line whilst the CLK line is High.
286	;
287	I2C_start: CALL I2C_data_Z ;DATA = Z (High)
288	CALL I2C_clk_Z ;CLK = Z (waits until definitely High)
289	CALL I2C_delay_5us ;delay before start (S)
290	CALL I2C_data_Low ;High to How transition on DATA whilst CLK is High
291	CALL I2C_delay_4us
292	CALL I2C_clk_Low ;CLK = 0 (plus 5us delay)
293	RETURN
294	;
295	;
296	;------------------------------------------------------------------------------------------
297	; Routine issue an I2C Stop (P) condition
298	;------------------------------------------------------------------------------------------
299	;
300	; Used to end any I2C transaction.
301	;
302	; The Stop (S) condition is signified by a Low to High transition of the DATA line whilst
303	; the CLK line is High.
304	;
305	; Note that following this routine the CARRY flag is '0' and can be used to confirm a
306	; good I2C communication (see 'I2C_Rx_ACK' routine).
307	;
308	I2C_stop: CALL I2C_data_Low ;DATA = 0
309	CALL I2C_delay_5us
310	CALL I2C_clk_Z ;CLK = Z (waits until definitely High)
311	CALL I2C_delay_4us
312	CALL I2C_data_Z ;DATA = Z (High)
313	RETURN
314	;
315	;
316	;------------------------------------------------------------------------------------------
317	; Routine to transmit one byte from the KCPSM6 master to a slave
318	;------------------------------------------------------------------------------------------
319	;
320	; The byte to be transmitted must be provided in register 's5'.
321	;
322	; The byte is transmitted most significant bit (MSB) first. As each of the 8 bits are
323	; presented to the DATA line the CLK line is pulsed High.
324	;
325	I2C_Tx_byte: LOAD s1, 10000000'b ;8-bits to transmit starting with MSB
326	I2C_Tx_next_bit: TEST s5, s1 ;test data bit for High or Low
327	JUMP NZ, I2C_Tx1
328	CALL I2C_data_Low ;DATA = 0
329	JUMP I2C_Tx_tsu
330	I2C_Tx1: CALL I2C_data_Z ;DATA = Z (High)
331	I2C_Tx_tsu: CALL I2C_clk_pulse ;generate clock pulse with delays
332	SR0 s1 ;move to next bit
333	RETURN C ;have 8 bits been transmitted?
334	JUMP I2C_Tx_next_bit
335	;
336	;
337	;------------------------------------------------------------------------------------------
338	; Routine to receive one byte from a slave
339	;------------------------------------------------------------------------------------------
340	;
341	; The byte received will be returned in register 's5'.
342	;
343	; The byte is received most significant bit (MSB) first. Each of the 8 bits are sampled
344	; as the CLK line is pulsed High.
345	;
346	I2C_Rx_byte: LOAD s1, 8'd ;8-bits to receive
347	I2C_Rx_next_bit: CALL I2C_Rx_bit ;receive and shift bit into LSB of s5
348	SUB s1, 1'd ;count bits received
349	JUMP NZ, I2C_Rx_next_bit
350	RETURN
351	;
352	;
353	;------------------------------------------------------------------------------------------
354	; Routine to transmit Acknowledge (ACK) from KCPSM6 master to a slave
355	;------------------------------------------------------------------------------------------
356	;
357	; An Acknowledge (ACK) bit is transmitted to a slave after receiving a byte of data.
358	;
359	; ACK is simply the transmission of a '0' requiring the DATA line to be driven Low whilst
360	; the CLK line is pulsed High.
361	;
362	I2C_Tx_ACK: CALL I2C_data_Low ;DATA = 0
363	;
364	I2C_clk_pulse: CALL I2C_delay_5us
365	CALL I2C_clk_Z ;CLK = Z (waits until definitely High)
366	CALL I2C_delay_4us ;clock pulse width
367	CALL I2C_clk_Low ;end of CLK clock pulse includes 5us delay
368	RETURN
369	;
370	;
371	;------------------------------------------------------------------------------------------
372	; Routine to transmit No Acknowledge (NACK) from KCPSM6 master to a slave
373	;------------------------------------------------------------------------------------------
374	;
375	; A No Acknowledge (NACK) bit is transmitted to a slave after receiving a byte of data and
376	; typically used to signify to a slave that a read transaction has been completed.
377	;
378	; NACK is simply the transmission of a '1' requiring the DATA line to be driven High
379	; whilst the CLK line is pulsed High.
380	;
381	I2C_Tx_NACK: CALL I2C_data_Z ;DATA = Z (High)
382	JUMP I2C_clk_pulse ;generate clock pulse (includes return)
383	;
384	;
385	;------------------------------------------------------------------------------------------
386	; Routine to receive and test the Acknowledge (ACK) from a slave
387	;------------------------------------------------------------------------------------------
388	;
389	; The KCPSM6 master will receive an Acknowledge (ACK) bit from a slave following the
390	; transmitted of a byte to the slave. Receiving an ACK indicates that the slave responded
391	; as expected but receiving a No Acknowledge (NACK) implies that something went wrong!
392	;
393	; The KCPSM6 master will pulse the CLK line High and receive the acknowledge bit from the
394	; slave. The received ACK bit will be returned in the least significant bit (LSB) of the
395	; 's5' register. Furthermore, a test will be performed such that the CARRY flag will also
396	; reveal if the bit was ACK or NACK.
397	;
398	; Received ACK bit Meaning CARRY(C)
399	; 0 ACK 0
400	; 1 NACK 1
401	;
402	; Note that following the 'I2C_stop' routine the CARRY flag is '0'.
403	;
404	I2C_Rx_ACK: CALL I2C_Rx_bit ;receive ACK bit into LSB of s5
405	TEST s5, 00000001'b ;set flags
406	RETURN
407	;
408	;
409	;------------------------------------------------------------------------------------------
410	; Subroutines used by the main I2C routines above
411	;------------------------------------------------------------------------------------------
412	;
413	; These routines actually control the I2C signals an ensure that timing specifications
414	; consistent with maximum bit rate of 100KHz are not exceeded.
415	;
416	;
417	; Drive CLK Low and wait for 5us before doing anything else.
418	;
419	I2C_clk_Low: AND sF, ~I2C_clk ;CLK = 0
420	OUTPUT sF, port_IIC_OUT
421	CALL I2C_delay_5us
422	RETURN
423	;
424	;
425	; Place CLK into tri-state (Z) so that it can go High.
426	; Then wait for CLK to actually become High before returning because a slave
427	; has the ability to stretch a clock to slow communication down.
428	;
429	I2C_clk_Z: OR sF, I2C_clk ;CLK = Z
430	OUTPUT sF, port_IIC_OUT
431	I2C_wait_clk_High: INPUT s0, port_IIC_IN ;read external signals
432	TEST s0, I2C_clk ;test CLK bit
433	JUMP Z, I2C_wait_clk_High ;wait if CLK held Low by slave
434	RETURN
435	;
436	;
437	; Drive DATA Low and wait for 5us before doing anything else.
438	;
439	I2C_data_Low: AND sF, ~I2C_data ;DATA = 0
440	OUTPUT sF, port_IIC_OUT
441	RETURN
442	;
443	;
444	; Place DATA into tri-state (Z) so that it can go High.
445	; This can be used to transmit or receive a '1' but can also be used by the
446	; slave to return a '0' by holding the data line Low against the pull-up resistor.
447	;
448	I2C_data_Z: OR sF, I2C_data ;DATA = Z
449	OUTPUT sF, port_IIC_OUT
450	RETURN
451	;
452	;
453	; Receive one bit of data
454	;
455	; The bit received is shifted into the LSB of register 's5'.
456	;
457	; This the routine must be executed from the condition CLK low.
458	;
459	; The DATA line is released to allow a slave to transmit. There will be a
460	; 5us delay before the CLK is released to start a clock pulse. The start of
461	; the clock pulse can be delayed by a slave but a High duration of 4us is
462	; guaranteed. The value of the DATA line is sampled at the mid-point of the
463	; 4us high period (i.e. after 2us). The CLK clock pulse is followed by a
464	; delay of 5us before anything else can happen.
465	;
466	I2C_Rx_bit: CALL I2C_data_Z ;DATA = Z (slave can now drive)
467	CALL I2C_delay_5us
468	CALL I2C_clk_Z ;CLK = Z (waits until definitely High)
469	CALL I2C_delay_2us ;middle of SCL clock pulse
470	INPUT s0, port_IIC_IN ;read external signals
471	TEST s0, I2C_data ;set carry flag with value of DATA
472	SLA s5 ;shift received bit into LSB of s5
473	CALL I2C_delay_2us ;complete 4us SCL clock pulse
474	CALL I2C_clk_Low ;end of clock pulse includes 5us delay
475	RETURN
476	;
477	;
478	; Software Delays for I2C Signal Timing
479	;
480	I2C_delay_5us: CALL I2C_delay_1us
481	I2C_delay_4us: CALL I2C_delay_1us
482	CALL I2C_delay_1us
483	I2C_delay_2us: CALL I2C_delay_1us
484	CALL I2C_delay_1us
485	RETURN
486	;
487	; The base delay is 1us and takes ((4 x I2C_time_reference) + 6) clock cycles
488	; to execute including the CALL instruction required to invoke it.
489	;
490	; For example, if the clock frequency is 100MHz then 'I2C_time_reference' should be set
491	; to 24'd. This will result in 24 iterations of the 'SUB' and 'JUMP NZ' loop resulting
492	; in the execution of 48 instructions. The invoking 'CALL', the 'LOAD' and the 'RETURN'
493	; bringing the total number of instructions to 51. All instructions take 2 clock cycles
494	; to execute so that is a total of 102 clock cycles which take 1.02us at 100MHz.
495	; i.e. ((4 x I2C_time_reference) + 6) = ((4 x 24) + 6) = 102 clock cycles
496	;
497	I2C_delay_1us: LOAD s0, I2C_time_reference
498	I2C_delay_loop: SUB s0, 1'd
499	JUMP NZ, I2C_delay_loop
500	RETURN
501	;
502	;
503	;------------------------------------------------------------------------------------------
504	; End of 'i2c_routines.psm'
505	;------------------------------------------------------------------------------------------
506	;

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