[4287] | 1 | #ifndef WARP_CLOCK_CONTROLLER_H |
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| 2 | #define WARP_CLOCK_CONTROLLER_H |
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| 3 | |
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| 4 | #include "xbasic_types.h" |
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| 5 | #include "xstatus.h" |
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| 6 | #include "xil_io.h" |
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| 7 | |
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| 8 | #define WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET (0x00000000) |
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| 9 | |
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| 10 | #define WARP_CLOCK_CONTROLLER_SLV_REG0_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000000) |
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| 11 | #define WARP_CLOCK_CONTROLLER_SLV_REG1_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000004) |
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| 12 | #define WARP_CLOCK_CONTROLLER_SLV_REG2_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000008) |
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| 13 | #define WARP_CLOCK_CONTROLLER_SLV_REG3_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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| 14 | #define WARP_CLOCK_CONTROLLER_SLV_REG4_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000010) |
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| 15 | #define WARP_CLOCK_CONTROLLER_SLV_REG5_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000014) |
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| 16 | #define WARP_CLOCK_CONTROLLER_SLV_REG6_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000018) |
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| 17 | #define WARP_CLOCK_CONTROLLER_SLV_REG7_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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| 18 | |
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| 19 | /* Address map: |
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| 20 | HDL is coded [MSB:LSB] = [31:0] |
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| 21 | regX[31] maps to 0x80000000 in C driver |
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| 22 | regX[0] maps to 0x00000001 in C driver |
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| 23 | |
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| 24 | 0: Config: |
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| 25 | [ 2: 0] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x00000003 |
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| 26 | [ 3] Reserved |
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| 27 | [ 4] samp buf reset (active low) 0x00000010 |
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| 28 | [ 5] rf ref buf reset (active low) 0x00000020 |
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| 29 | [15: 6] Reserved 0x0000FFC0 |
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| 30 | [31:16] Clock module status 0xFFFF0000 |
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| 31 | |
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| 32 | 1: SPI Tx |
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| 33 | [ 7: 0] Tx data byte |
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| 34 | [14: 8] 7-bit register address (0x00 to 0xFF all valid) |
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| 35 | [20:15] 6'b0 (always zero) |
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| 36 | [22:21] Num bytes to Tx/Rx; must be 2'b0 for 1-byte Tx/Rx |
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| 37 | [ 23] RW# 1=Read, 0=Write |
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| 38 | [ 24] samp clock buffer chip select mask |
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| 39 | [ 25] rf ref clk buffer chip select mask |
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| 40 | [ 26] clock module clk buffer chip select mask |
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| 41 | [31:27] Reserved |
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| 42 | |
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| 43 | 2: SPI Rx: {samp_rxByte, rfref_rxByte, 16'b0} |
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| 44 | [ 7: 0] SPI Rx byte for samp buf 0x0000FF |
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| 45 | [15: 8] SPI Rx byte for rf ref buf 0x00FF00 |
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| 46 | [23:16] SPI Rx byte for clock module 0xFF0000 |
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[4305] | 47 | [31:24] Reserved 0xFF000000 |
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[4287] | 48 | |
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| 49 | 3: RW: User reset outputs |
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| 50 | [0] usr_reset0 |
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| 51 | [1] usr_reset1 |
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| 52 | [2] usr_reset2 |
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| 53 | [3] usr_reset3 |
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| 54 | [31:4] reserved |
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| 55 | |
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| 56 | 4: RO: User status inputs |
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| 57 | [31: 0] usr_status input |
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| 58 | |
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| 59 | 5-15: Reserved |
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| 60 | */ |
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| 61 | |
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| 62 | #define CLKCTRL_REG_CONFIG WARP_CLOCK_CONTROLLER_SLV_REG0_OFFSET |
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| 63 | #define CLKCTRL_REG_SPITX WARP_CLOCK_CONTROLLER_SLV_REG1_OFFSET |
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| 64 | #define CLKCTRL_REG_SPIRX WARP_CLOCK_CONTROLLER_SLV_REG2_OFFSET |
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| 65 | #define CLKCTRL_REG_USR_RESETS WARP_CLOCK_CONTROLLER_SLV_REG3_OFFSET |
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| 66 | #define CLKCTRL_REG_STATUS WARP_CLOCK_CONTROLLER_SLV_REG4_OFFSET |
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| 67 | |
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| 68 | #define CLKCTRL_REG_CONFIG_MASK_CLKDIV 0x03 |
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| 69 | #define CLKCTRL_REG_CONFIG_MASK_SAMP_FUNC 0x10 |
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| 70 | #define CLKCTRL_REG_CONFIG_MASK_RFREF_FUNC 0x20 |
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| 71 | |
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| 72 | #define CLKCTRL_REG_SPITX_SAMP_CS 0x01000000 |
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| 73 | #define CLKCTRL_REG_SPITX_RFREF_CS 0x02000000 |
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| 74 | #define CLKCTRL_REG_SPITX_CMPLL_CS 0x04000000 |
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| 75 | #define CLKCTRL_REG_SPITX_RNW 0x00800000 |
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| 76 | |
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| 77 | #define CLK_SAMP_CS CLKCTRL_REG_SPITX_SAMP_CS |
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| 78 | #define CLK_RFREF_CS CLKCTRL_REG_SPITX_RFREF_CS |
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| 79 | #define CMPLL_CS CLKCTRL_REG_SPITX_CMPLL_CS |
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| 80 | |
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| 81 | #define CLK_SAMP_OUTSEL_FMC 0x01 |
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| 82 | #define CLK_SAMP_OUTSEL_CLKMODHDR 0x02 |
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| 83 | #define CLK_SAMP_OUTSEL_FPGA 0x04 |
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| 84 | #define CLK_SAMP_OUTSEL_AD_RFA 0x08 |
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| 85 | #define CLK_SAMP_OUTSEL_AD_RFB 0x10 |
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| 86 | |
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| 87 | #define CLK_RFREF_OUTSEL_FMC 0x20 |
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| 88 | #define CLK_RFREF_OUTSEL_CLKMODHDR 0x40 |
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| 89 | #define CLK_RFREF_OUTSEL_RFAB 0x80 |
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| 90 | |
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| 91 | #define CLK_OUTPUT_ON 1 |
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| 92 | #define CLK_OUTPUT_OFF 2 |
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| 93 | |
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| 94 | #define CLK_INSEL_ONBOARD 1 |
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| 95 | #define CLK_INSEL_CLKMOD 2 |
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| 96 | |
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[4305] | 97 | //CM switch interpretation |
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| 98 | // Clock modules pull switch signals to GND when switch is asserted |
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| 99 | // FPGA pulls up sw[2:0] to [111] |
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| 100 | // CM-PLL pulls sw[2] to GND, sw[1:0] set by LSB of DIP switch ("up" = 0) |
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| 101 | // CM-PLL: sw[2:0] = [2,1,0] => CFG_[A,B,C] |
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| 102 | // CM-MMCX floats sw[2] (IOB pulls up), sw[1:0] set by SIP switch ("down" = 0) |
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| 103 | // CM-MMCX: sw[2:0] = [6,5,4] => CFG_[A,B,C] |
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| 104 | |
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| 105 | #define CM_STATUS_SW 0x7 |
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| 106 | |
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| 107 | #define CM_STATUS_DET_NOCM 0x7 |
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| 108 | |
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| 109 | #define CM_STATUS_DET_CMMMCX_CFG_A 0x6 |
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| 110 | #define CM_STATUS_DET_CMMMCX_CFG_B 0x5 |
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| 111 | #define CM_STATUS_DET_CMMMCX_CFG_C 0x4 |
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| 112 | |
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| 113 | #define CM_STATUS_DET_CMPLL_BYPASS 0x3 |
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| 114 | #define CM_STATUS_DET_CMPLL_CFG_A 0x2 |
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| 115 | #define CM_STATUS_DET_CMPLL_CFG_B 0x1 |
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| 116 | #define CM_STATUS_DET_CMPLL_CFG_C 0x0 |
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| 117 | |
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| 118 | #define CM_STATUS_CMPLL_LOCKED 0x8 |
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| 119 | |
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[4287] | 120 | u32 clk_spi_read(u32 baseaddr, u32 csMask, u8 regAddr); |
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| 121 | void clk_spi_write(u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte); |
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| 122 | |
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| 123 | int clk_init(u32 baseaddr, u8 clkDiv); |
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| 124 | |
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| 125 | int clk_config_outputs(u32 baseaddr, u8 clkOutMode, u32 clkOutSel); |
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| 126 | int clk_config_dividers(u32 baseaddr, u8 clkDiv, u32 clkOutSel); |
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| 127 | int clk_config_input_rf_ref(u32 baseaddr, u8 clkInSel); |
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[4305] | 128 | inline u32 clk_config_read_clkmod_status(u32 baseaddr); |
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[4287] | 129 | |
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| 130 | #endif /** WARP_CLOCK_CONTROLLER_H */ |
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